KR20010061521A - Electrostatic discharge circuit of semiconductor device - Google Patents

Abstract

PURPOSE: An electrostatic discharge(ESD) protection circuit of a semiconductor device is provided to improve a characteristic and to effectively prevent an ESD fail, by forming the ESD protection circuit of a triple structure composed of the first and second N wells. CONSTITUTION: The first and second N wells are formed in a semiconductor substrate(30), wherein a P well is formed in the second N well. A P-channel field transistor is formed in the first N well, connected to a pad(44) and a power supply terminal. An N-channel field transistor is formed in the P well, connected to the pad and a ground terminal. The first pick-up region(41) is formed in the first N well, connected to the power supply terminal. The second pick-up region(42) is formed in the P well, connected to the ground terminal. The third pick-up region(43) is formed in the second N well, connected to the power supply terminal. An N-type junction part(45) is formed in the second N well, connected to the P-channel field transistor.

Description

Electrostatic discharge circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit of a semiconductor device. In particular, the present invention relates to a flash that can improve ESD zapping characteristics by reducing current crowding in the ESD protection circuit. The present invention relates to an ESD protection circuit of a memory device.

In general, MOS circuits are designed to operate internally at voltages of around 5V. However, due to various causes, exposure to higher voltages may occur. In such a situation, the gate oxide of the MOS device may be destroyed, the junction spiking may occur, or the device may be completely destroyed. Damage and seriously affect the reliability of the device. As such, the exposure of the device to high voltage can have various causes. As a result, the ground state such as the static electricity generated in the human body or the semiconductor device equipment is unstable, and an electric charge flows into the device momentarily through the pin. I will go. In order to prevent such damage, the ESD protection circuit is configured before the circuit input stage. Therefore, ESD boro circuits require a more stable level of static discharge in order to effectively prevent the inflow of static electricity from the outside.

Referring to the accompanying drawings, an ESD protection circuit of a conventional semiconductor device is as follows.

1 is a cross-sectional view of a device for explaining an ESD protection circuit of a conventional semiconductor device.

Referring to FIG. 1, field oxide films 16 and 11 are formed on a semiconductor substrate 10 having a P well, and the first and second sources 13 and 17 and the first and second sources, which are junction regions, are formed by an ion implantation process. And second drains 12 and 18, first and second pickup regions 15 and 20 to form first N channel field transistor 14 and second N channel transistor 19. In addition, the first and second drains 12 and 18 are connected to the pad 21, the first source 13 is connected to the power supply terminal Vcc, and the second source 17 and the second pickup area 20 are connected to each other. ) Is connected to the ground terminal (Vss).

The conventional ESD protection circuit has four major problems. First, a break down to the first drain 12 connected to the pad 21 in a mode in which a positive power is applied to the power supply terminal Vcc. The first drain 12 is weakened when a snap-back A occurs from the first source 13 toward the first drain 12 after the? Second, in the mode in which negative power is applied to the power supply terminal Vcc, the current is discharged in the forward direction in the P-well at N +. However, in FIG. 1, since the p well is floating, the first drain ( In 12), a snap-back B is generated from the first source 13 to weaken the first source 13. Third, even when a positive power is applied to the ground terminal Vss, a breakdown occurs first in the second drain 18 connected to the pad 21, and then snaps from the second source 17 toward the second drain 18. Bag C occurs. Fourth, in contrast to the third problem, when negative power is applied to the ground terminal Vss, snap-back occurs from the second drain 18 to the second source 17. Therefore, the conventional ESD protection circuit has a problem that becomes vulnerable to ESD because there is a discharge after snap-back occurs.

Accordingly, an object of the present invention is to provide an electrostatic discharge protection circuit of a semiconductor device which can prevent an ESD fail due to a problem such as snap-back and can improve the characteristics of an ESD protection circuit.

The electrostatic discharge protection circuit of the semiconductor device according to the present invention for achieving the above object is connected to a semiconductor substrate, a pad and a power supply terminal having first and second N wells formed with P wells in the second N wells. A P channel field transistor formed in the first N well, an N channel field transistor formed in the P well and connected to the pad and a ground terminal, a first pickup region connected to the power supply terminal and formed in the first N well; A second pick-up region connected to the ground terminal and formed in the P well, a third pick-up region connected to the power terminal and formed in the second N well, and formed in the second N well and the P channel field transistor. It characterized in that it comprises an N-type junction connected with.

1 is a cross-sectional view of a device for explaining an ESD protection circuit of a conventional semiconductor device.

2 is a cross-sectional view of a device for explaining an ESD protection circuit of a semiconductor device according to the present invention.

3 is a conceptual diagram of an operation schematically showing a cross-sectional view of the device shown in FIG.

<Description of Signs of Major Parts of Drawings>

10 and 30: semiconductor substrate 11, 16 and 34: field oxide film

12 and 36: first drain 13 and 35: first source

14; First N-Channel Transistors 15 and 41: First Pickup Region

17 and 38: second source 18 and 39: second drain

19: second N-channel transistor 20 and 42: second pickup region

21 and 44: pad 37: P channel transistor

40: N-channel transistor 43: third pickup region

45: N type joint

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a device for explaining an electrostatic discharge protection circuit of a semiconductor device according to the present invention.

Referring to FIG. 2, first and second N wells 31 and 32 are formed in the semiconductor substrate 30, and a P well 33 is formed in the second N well 32, and the first N well 31 is formed. ) Forms a P-channel field transistor 37 and a first pickup region 41. The P channel field transistor 37 is composed of a field oxide film 34, a first source 35 and a first drain 36, and the first source 35 and the first drain 36 are P-type junctions.

The N channel field transistor 40 and the second pickup region 42 are formed in the P well 33, and the N channel field transistor 40 includes the field oxide layer 34, the second source 38, and the second drain ( 39, the second source 38 and the second drain 39 are N-type junctions.

A third pickup region 43 and an N-type junction 45 are formed in the second N well 32, but the N-type junction 45 is connected to the first drain 36, and the first source 35 and the first junction 35 are formed. The first pick-up area 43 and the second pick-up area 42 are connected to the power supply terminal Vcc. The first drain 36 of the P-channel field transistor 37 and the second drain 39 of the N-channel field transistor 40 are connected to the pad 44, and the second source 38 and the second pickup region ( 42 is connected to the ground terminal Vss.

In the ESD protection circuit of the present invention, in the case of positive zapping of the power supply terminal Vcc, the discharge does not occur in the conventional snap-back mode, but is a path that is forward in the P-type junction of the first N well 31. And a new path E to the second N well 32 is made to improve the positive pumping characteristics of the power supply terminal Vcc.

For negative chipping of the power supply terminal Vcc, the snap-back mode G path from the first drain 36 of the first N well 31 to the first source 35 and to the second N well 32 A new discharge path (opposite the E path) occurs. This new discharge path (opposite to the E path) reduces the burden on the N-type junction when discharging with conventional snap-back (G) paths only, which improves the negative chipping characteristics of the power supply terminal (Vcc).

In addition, the second N well 32 is always floated at the time of positive chipping to the ground terminal Vss, so that snap-back F is easily generated.

3 is a conceptual view schematically illustrating a cross-sectional view of the device illustrated in FIG. 2, in which a power supply terminal Vcc and a second N well 32 are connected 50 to each other, and a P channel field transistor 37 And an N channel field transistor 40 are formed.

As described above, the present invention forms an ESD protection circuit in a triple structure of the first and second N wells, thereby improving the characteristics of the ESD protection circuit and effectively preventing the ESD failure.

Claims (1)

A semiconductor substrate having first and second N wells formed therein and a P well formed therein; A P-channel field transistor connected to a pad and a power supply terminal and formed in the first N well; An N-channel field transistor connected to the pad and the ground terminal and formed in the P well; A first pickup region connected to the power terminal and formed in the first N well; A second pickup region connected to the ground terminal and formed in the P well; A third pickup region connected to the power supply terminal and formed in the second N well; And an N-type junction formed in the second N well and connected to the P channel field transistor.