KR20010061473A - Source bias supply circuit of flash memory - Google Patents

Abstract

PURPOSE: A source bias supplying circuit of a flash memory is provided to offsets threshold voltage drop by applying more than fixed positive voltage to a source line of each cell. CONSTITUTION: In a read operation, because a program signal(PROGRAM) and a recovery signal(RECOVERY) are low signals, an NMOS transistor(N2) is turned off. And, because a read signal(READ) and an erase signal(ERASE) are low signals, a PMOS transistor(P1) is turned on, and an NMOS transistor(N1) is turned on. For this reason, a potential of a node A is the sum of threshold voltages of a diode(D1) and an NMOS transistor(N1), and the node A applies a voltage(Vs) by being connected to a source line. When a fixed voltage is applied to the source line, a threshold voltage of a cell is increased as much as the fixed voltage. In conclusion, when the threshold voltage is increased, a drop of the threshold voltage is offset.

Description

Source bias supply circuit of flash memory

The present invention relates to a flash memory, and more particularly, to a source bias supply circuit of a flash memory for raising a threshold voltage of a recovery cell to a positive voltage.

In general, in order to solve the over erase problem caused by over erased bits of a stack gate cell in a flash memory, as shown in FIG. 1, a soft program is applied by applying a bias to a cell. Recovery is performed by That is, the ground is applied to the control gate and the source, and a voltage of about 5 volts is applied to the drain to perform the recovery.

Referring to FIGS. 2A and 2B, while the cells are over-erased before performing the recovery, there are cells whose threshold voltage is negative (that is, the over-erased cells). However, after the recovery is performed by the bias application described above, the threshold voltage is performed. You can see that this becomes a positive recovery. After the recovery, a recovery verify, a read operation, is performed to determine whether the recovery was successful.

To perform recovery verification, a recovery bias is applied to the cell as shown in FIG. 3A. That is, the restoration verification is performed by applying ground to the control gate and the source and applying a positive voltage of about 1 volt to the drain. When the drain current of the cell falls below a few kilowatts (3 to 5 mA), it is determined that the recovery is completed.

The relationship between the current and VPG at this time is shown in a graph as shown in FIG. 3B.

However, even when the recovery is performed so that the drain current becomes 0 Ω or less when applied to ground (0 volt) to the control gate of the cell, that is, the threshold voltage of the cell becomes 0 volts, the threshold voltage of the cell increases The negative voltage is lowered.

When the threshold voltage of the cell is lowered, the drain current ID, which should not flow when 0 volts is applied to the bit line, increases to ID '. This phenomenon occurs among many cells connected to the same bit line, so that a very large leakage current is generated, which makes normal read operation impossible. In addition, when a high bias of about 5 volts is applied, there is a problem that 5 volts are coupled to the floating gate and cells to be turned off are turned on.

Accordingly, an object of the present invention is to provide a source bias supply circuit of a flash memory that applies a predetermined positive voltage or more to a source line of each cell at the time of reading.

In order to achieve the above object, a source bias supply circuit of a flash memory according to the present invention includes a first PMOS transistor connected between a source line of a cell array and a power supply voltage, a diode connected between a node A and a ground; A first NMOS transistor, a second NMOS transistor connected between the node A and the ground, and a logic gate portion for switching the second NMMOS transistor in accordance with a program signal and a recovery signal are included. The logic gate unit includes a NOR gate receiving a program signal through one input terminal and a recovery signal through the other input terminal, an input terminal connected to an output terminal of the NOR gate, and an output terminal connected to a gate of a second NMOS transistor. The read signal is input to the gate of the 1PMOS transistor, the output terminal of the inverter I1 is connected to the gate of the first NMOS transistor, and the erase signal is input to the input terminal of the inverter I1.

1 is a diagram for explaining a conventional soft program.

2A and 2B are graphs for explaining cell states before and after a conventional recovery;

3A and 3B are views for explaining a conventional restoration verification.

4 is a view for explaining a conventional drain coupling.

5 is a graph for explaining the purpose of the present invention.

6 is a view for explaining read bias application according to the present invention.

7 is a source bias supply circuit according to the present invention.

8 is a graph illustrating a cell state before and after recovery according to the present invention.

Explanation of symbols on the main parts of the drawings

10: cell array

20: source bias supply circuit

21: logic gate part

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

Referring to Figure 5 looks at the object of the present invention.

5 is a distribution of threshold voltages of cells after erasing, b is distribution of threshold voltages of cells after recovery by a conventional method, and c is a threshold of cells required to solve a conventional problem. The distribution of voltages. That is, after recovery, the threshold voltage of the cell should be at least 0.5 volts. In this embodiment, 0.6 volts is supplied to the source line to set the threshold voltage to 0.6 volts.

The read bias according to the present invention will be described with reference to FIG. 6.

To read a cell array, a word line and a bit line where a cell to be read is located must be selected.

A voltage of about 5 volts is applied to the first word line W / L1 selected to read the programmed cell A, and ground level, that is, zero volts, is applied to the other word lines W / L2 to W / Ln. Apply (0V). One volt is applied to the first bit line BL1 selected to read the programmed cell A, and zero volts is applied to the other bit lines BL2 to BLn, and a source bias circuit is applied to the source of each cell. Supply the generated voltage (Vs).

A source bias circuit according to the present invention described above with reference to FIG. 7 will be described.

A first PMOS transistor P1 is connected between the power supply voltage Vcc and node A, and a read signal READ is input to a gate of the first PMOS transistor P1. In addition, a diode D1 and a first NMOS transistor are connected between node A and ground. In this case, the gate of the first NMOS transistor N1 is connected to the output terminal of the inverter I1, and the erase signal ERASE is input to the input terminal of the inverter I1.

A second NMOS transistor N2 is connected between node A and ground, and a logic gate portion 21 is connected to a gate of the second NMOS transistor N2. The logic gate unit 21 serves to switch the second NMOS transistor N2 in response to a program signal and a recovery signal, and includes an inverter I2 and a NOR gate NO1. The output terminal of the inverter I2 is connected to the gate of the second NMOS transistor N2, and the input terminal of the inverter I2 is connected to the output terminal of the NOR gate NO1. At this time, a program signal PROGRAM is input to one input terminal of the NOR gate NO1 and a recovery signal RECOVERY is input to the other input terminal. The node A of the circuit described above is connected to the source of the cell array to supply the voltage Vs.

Hereinafter, the operation of the circuit having the above-described configuration will be described.

5 volts is applied to the word line W / L1 to be read, and a ground level, that is, 0 volts is applied to the other word lines W / L2 to W / Ln. One volt is applied to the bit line BL1 to be read, and zero volts is applied to the other bit lines BL2 to BLn.

At the time of reading, since the program signal PROGRAM and the recovery signal RECOVERY are both low signals, the NOR gate NO1 outputs a high signal. When a high signal is output from the NOR gate NO1, the inverter I2 converts the high signal into a low signal. When the low signal is output from the inverter I2, the NMOS transistor N2 is turned off.

On the other hand, the read signal READ and the erase signal ERASE become low signals during reading. When the read signal which is the low signal is applied to the gate of the PMOS transistor P1, the PMOS transistor P1 is turned on. When the erase signal ERASE, which is a low signal, is input to the inverter I1, the inverter I1 converts the input low signal into a high signal. Accordingly, the NMOS transistor N1 is turned on.

When the PMOS transistor P1 and the NMOS transistor N1 are turned on, the node A has a voltage (approximately 0.6 volts) equal to the threshold voltage of the diode D1 and the NMOS transistor N1 at the power supply voltage Vcc (1 volt). NodeA is connected to the source line of the cell array to supply the voltage Vs.

When a voltage of about 0.6 volts is applied to the source line, the voltage appears at -0.6 volts in the Vgs of each unselected cell, increasing the threshold voltage of the cell by about 0.6 volts. Referring to FIG. 8, it can be seen that the threshold voltage distribution ① of the cell before applying the source bias has moved in the positive direction by 0.6 volt after applying the source bias (②).

Accordingly, when the threshold voltage of the cell rises, the decrease in the threshold voltage due to the temperature or the drain coupling effect may be offset.

According to the source bias supply circuit of the flash memory according to the present invention, when a threshold voltage of a cell is increased by applying a predetermined positive voltage (about 0.5 volt) or more to the source line of each cell during reading, a temperature or drain coupling effect The threshold voltage drop due to this can be canceled out.

Claims (4)

A first PMOS transistor connected between a node A connected to a source line of the cell array and a power supply voltage, A diode and a first NMOS transistor connected between the node A and ground, A second NMOS transistor connected between the node A and ground, And a logic gate portion for switching the second NMMOS transistor according to a program signal and a recovery signal. The method of claim 1, The logic gate unit may include a NOR gate receiving a program signal to one input terminal and a recovery signal to the other input terminal, an input terminal connected to an output terminal of the NOR gate, and an output terminal connected to a gate of the second NMOS transistor. Source bias supply circuit for flash memory. The method of claim 1, And a read signal is input to a gate of the first PMOS transistor. The method of claim 1, An output terminal of the inverter (I1) is connected to a gate of the first NMOS transistor, and an erase signal is input to an input terminal of the inverter (I1).