KR20010061387A - Semiconductor memory device having diverse output signal in test operation - Google Patents

Abstract

PURPOSE: A semiconductor memory device having several output signals at a test operation is provided to improve a fault coverage in several data outputting forms at the test operation. CONSTITUTION: The semiconductor memory device includes a device to embody a parallel test mode. The device to embody the parallel test mode includes a comparing array(210) and first and second test outputting portions(230,250). The comparing array generates a comparison array outputting signal to respectively receive the first array outputting signal and the second array outputting signal, through the first input signal node and the second input signal node in response to a test mode enabling signal(tm_en) and compare them. The first test outputting portion receives the first array outputting signal through an array output signal node in response to the comparison array outputting signal from an output enabling signal and an error detecting signal node, and outputs the same a signal as the first array outputting signal or a high impedance signal as the first test outputting signal. The second test outputting portion receives the second array outputting signal through an array output signal node in response to the test mode enabling signal inputted from the output enabling signal and the error detecting signal node and outputs the same a signal as the second array outputting signal or a high impedance signal as the second test outputting signal.

Description

Semiconductor memory device having various output signals in test operation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having improved fault coverage through various output signals during a test operation.

In general, as semiconductor memory devices are highly integrated with the development of process technology, tests are performed for a long time with expensive test equipment after manufacturing to ensure chip reliability. In order to test such a memory device, in order to reduce the time and cost of the test, a self test circuit is built in the chip in advance in the design stage.

In normal mode, a row address and a column address are selected in combination with a row address and a column address in order to access a cell. The data is written or read so that the output data appears in three forms: "high", "low", and "high impedance (high-z)".

On the other hand, in the test mode, the data of each cell array can be either "low" or "high", but the output by the operation of the parallel mode circuit is the same or the same. If not, it distinguishes a pass and a fail as "high" or "low".

1 is a test mode block diagram according to the prior art, an input mode selector 10 which selects one of a normal mode and a test mode and transfers the input data DI to a cell array, and stores input data and output data. Selects a mode at the output terminal and outputs data to the outside according to the selected mode. The cell array 20 generates a comparison unit, the comparison unit 30 generates a comparison output signal com_out comparing the outputs of the cell arrays 20. It consists of an output mode selection unit 40 for outputting or outputting a test result.

The operation of the test mode block diagram of FIG. 1 configured as described above will be described.

The conventional memory test apparatus includes two general modes of writing and reading data to each memory cell array 20 and a parallel test mode of simultaneously writing and reading data to a plurality of memory cell arrays.

First, in the normal mode, in order to access a cell in the same manner as a normal memory operation, a bit line corresponding to the number of bits of one word line and an input / output of one cell array is selected by a combination of a low address and a column address. The data of is written or read.

The test mode is selected as the test mode by the input mode selector 10 to write the same data to a plurality of cell arrays, and during a read operation, the test mode is applied to the comparator before the output stage so that all data of each cell array is "low". Or both are "high", the comparator output (com_out) is "high", as shown in Table 1 below, otherwise "low". The data com_out is buffered while passing through the output mode selector and transferred to the output terminal.

As a result, the output data DQ is logic “high” during normal operation, in which the data of all four cell arrays are the same, and logic “low” is output to determine whether the memory is operating.

c1 c2 c3 c4 D0 0 0 0 0 One One One One One others 0

Since the test mode as described above is determined by the internal configuration of the actual device, there are differences for each device, but some bits of the row address or column address are ignored by the number of parallel cell arrays that access the cell and compare them for one input / output. do. For example, if four parallel cell arrays are compared simultaneously for one input and output, the address is reduced by 2 bits and the test time is reduced by 25% compared to normal mode. In the same way, if there are two comparison cell arrays, one bit is reduced.

However, there is a problem when outputting inverted data in the semiconductor memory device test block configured as described above. Compares the output data between the cell arrays rather than the data first entered, so writes a logic "high" to each cell array and outputs a logic "low" or reads a logic "low" during read operation. Outputting a logic "high" causes a problem that determines that it is operating normally.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a semiconductor memory device which improves fault coverage with various data output forms during a test operation.

1 is a test mode block diagram according to the prior art.

2 is a test mode block diagram in accordance with an embodiment of the present invention.

3 is a detailed circuit diagram of a test output unit according to an embodiment of the present invention.

4 is a detailed circuit diagram of a comparison array according to an embodiment of the present invention.

5 is a simulation result of the comparative array according to an embodiment of the present invention.

6 is a simulation result of the test output unit according to an embodiment of the present invention.

7 is an overall simulation result according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: comparative array 230, 250: first and second test output unit

fail_flag: Error detection signal tm_en: Test mode enable signal

mode_select: Mode select signal

The present invention for achieving the above object is a semiconductor memory device having a device for implementing a parallel test mode, the parallel test mode implementation device, the first array output signal and the second array in response to the test mode enable signal A comparison array configured to generate a comparison array output signal by receiving an output signal as a first input signal node and a second input signal node, respectively; The first array output signal is input to the array output signal node in response to the comparison array output signal input to the output enable signal and the error detection signal node, and the same signal as the first array output signal or a high-impedance signal is generated. A first test output unit outputting the first test output signal; And receiving the second array output signal as an array output signal node in response to the test mode enable signal input to the output enable signal and the error detection signal node. The same signal or high-impedance as the second array output signal is received. And a second test output unit which outputs a signal as a second test output signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a test mode block diagram according to an embodiment of the present invention.

Referring to FIG. 2, the test mode block receives the first array output signal array0 and the second array output signal array1 as the first input signal in_a node and the second input signal in_b node, respectively. A comparison array 210 that receives a mode enable signal tm_en and generates a comparison array output signal out_ab, and the comparison array output received as an output enable signal / oe and error_flag node. In response to the signal out_ab, the first array output signal array0 is input to the array output signal node array_dout, and the same test or high-impedance signal as the first array output signal is output to the first test output signal DQ0. The second array output in response to the first test output unit 230 for outputting the signal and the second array output signal array1 received as the output enable signal / oe and the error detection signal node fail_flag. The signal DQ1 is input to the array output signal node array_dout. The second array and the same signal or a high output signal is made an impedance signal to a second test output unit 250 for outputting a second test output signal.

3 is a detailed circuit diagram of the test output unit 230, 250 according to an embodiment of the present invention.

Referring to FIG. 3, test output units 230 and 250 receive the array output signal array_dout in response to the error detection signal fail_flag and the output enable signal / oe, and pull-up signals pu. And an input unit 310 for generating a pull-down signal pd, and an output unit 330 for generating a test output signal DQ in response to the pull-up signal pu and the pull-down signal pd.

The input unit 310 is a NOR gate NOR31 for generating a mode select signal (mode_select) by inputting the error detection signal (fail_flag) and the output enable signal (/ oe), the array output signal (array_dout) and the NAND gate ND31 for inputting a mode selection signal, inverter INV31 for inverting the array output signal, NAND gate ND32 for inputting the output signal of the inverter INV31 and the mode selection signal, and output signal of the NAND gate ND31. The inverter INV32 which inverts to generate the pull-up signal pu and the inverter INV34 which inverts the output signal of the NAND gate ND32 to generate the pull-down signal pd.

The output unit 330 receives an inverter INV33 for inverting the pull-up signal pu and an output signal of the inverter INV33 through a gate and transfers supply power to the test output signal DQ through a source-drain path. A PMOS transistor PM31 and an NMOS transistor NM31 receiving the pull-down signal pd through a gate and transferring ground power to the test output signal DQ through a source-drain path.

4 is a detailed circuit diagram of the comparison array 210 according to an embodiment of the present invention.

Referring to FIG. 4, the comparison array 210 receives a first input signal in_a and the second input signal in_b and compares the comparison unit 410 to generate a comparison output signal com_out. The comparison output unit 430 generates the comparison array output signal out_ab in response to the test mode enable signal tm_en and the comparison output signal com_out.

The comparator 410 includes a first input signal detector configured to include a plurality of transistors that are on-off according to the first input signal in_a to sense a logic level of the first input signal. 411, a second input signal detector 412 including a plurality of transistors turned on and off according to the second input signal in_b to sense a logic level of the second input signal, and a supply of the comparator It consists of a pull-up driving unit 413 for transmitting power. The comparison output unit 430 may include an inverter INV43 for inverting the comparison output signal com_out, an inverter INV44 for inverting the test mode enable signal tm_en, and output signals of the inverter INV43 and the inverter INV44. It is composed of a NOR gate NOR41 which receives the and generates the comparison array output signal out_ab.

In detail, the second input signal detector 412 receives the second input signal through an inverter INV42 for inverting the second input signal in_b and a gate, and supplies the second input signal to the node N41 through a source-drain path. An NMOS transistor NM47 that delivers power, an NMOS transistor NM48 that receives the second input signal through a gate, and delivers ground power to a node N42 through a source-drain path, and an output signal of the inverter INV42 through a gate. -An NMOS transistor NM45 for delivering the supply power to the node N42 through a drain path, and an NMOS transistor NM46 for receiving the output signal of the inverter INV42 through a gate and transferring the ground power through a source-drain path.

The first input signal detection unit 411 may receive an inverter INV41 that inverts the first input signal in_a, and receives the first input signal through a gate to between the node N41 and the node N43 through a source-drain path. An NMOS transistor NM43 that opens a path of the NMOS transistor, an NMOS transistor NM44 that receives the first input signal through a gate, and transfers a signal of the node N42 to the comparison output signal com_out through a source-drain path; An NMOS transistor NM41 that receives the output signal of the inverter INV41 and transfers the signal of the node N41 to the comparison output signal through a source-drain path, and receives the output signal of the inverter INV41 through a gate; It consists of an NMOS transistor NM42 that opens the path between node N42 and node N43.

In addition, the pull-up driving unit 413 receives the comparison output signal com_out through a gate and transfers the PMOS transistor PM41 to the node N43 through a source-drain path, and transmits a signal of the node N43 to a gate. It is composed of a PMOS transistor PM42 that receives the input and delivers the supply power to the comparison output signal through a source-drain path.

An operation according to an embodiment of the present invention having the above configuration will be described with reference to the simulation results of FIGS. 5 to 7.

Before comparing the overall operation, the comparison array 210 and the test output units 230 and 250 will be described first.

First, the test output units 230 and 250 may perform a test mode and a normal by the mode selection signal mode_select determined by the error detection signal fail_flag and the output enable signal / oe. It is divided into normal modes.

If both the error detection signal and the output enable signal are logic " low ", the mode selection signal mode_select becomes " high " to operate in the normal mode to output the array output signal array_dout as the output signal. When only one of the error detection signal and the output enable signal is “high”, the mode selection signal becomes “low” to operate in the test mode to generate a high-impedance signal (DQ) as the test output signal DQ. Hi-z) is output.

Specifically, in the test mode, the mode selection signal is "low" and the pull-up signal pu and the pull-down signal pd are "low", so that both the PMOS transistor PM31 and the NMOS transistor NM31 are turned off. The output signal DQ is brought into a high-impedance state.

In the normal mode, when the mode selection signal is " high " and the array output signal is " high ", the pull-up signal is " high " and the pull-down signal is " low " so that the PMOS transistor PM31 is turned on. -On and the NMOS transistor NM31 is turned off so that the output signal DQ is "high" and outputs the same signal as the array output signal. On the other hand, when the array output signal is applied as "low", the pull-up signal is "low" and the pull-down signal is activated "high" so that the NMOS transistor NM31 is turned on so that the output signal DQ is " Low "to output the same signal as the array output signal.

Next, the operation of the comparison array 210 when the first input signal (in_a) and the second input signal (in_b) is received when the two input signals are the same as shown in Table 2 below the comparison unit ( When the comparison output signal of logic 410 is logic "low" and the two input signals are different, the comparison output signal is logic "high" and a detailed operation description of the comparison unit 410 can be easily understood by those skilled in the art with reference to Table 2 below. I understand it and omit it.

First input signal in_a Second input signal in_b Comparison output signal (com_out) L L L L H H H L H H H L

The comparison output signal is output as the comparison array output signal out_ab when the test mode enable signal tm_en is active "high", and the comparison output when the test mode enable signal is disabled "low". Regardless of the signal, the comparison array output signal is " low ".

With reference to the operation of the comparison array 210 and the test output unit (230, 250) will be described by dividing the operation of the test mode block according to an embodiment of FIG. .

In the normal mode, the comparison array output signal out_ab, which is an output signal of the comparison array 210, is output as a logic "low" regardless of the first array output signal array0 and the second array output signal array1. The error detection signal (fail_flag) node of the first test output unit 230 is input, and the test mode enable signal is “low” as the error detection signal (fail_flag) node of the second test output unit 250. "Level, and the output enable signal / oe is activated" low "and is applied to the first test output unit 230 and the second test output unit 250 to provide the first array output signal. And the second array output signal are output as it is as the first test output signal DQ0 and the second test output signal DQ1.

In the test mode, the test mode enable signal is “high” and the output enable signal is “low”, so that the second test output signal of the second test output unit outputs “high impedance”, and the first The test output unit outputs the first array output signal as the first test output signal when the first array output signal and the second array output signal are the same. On the other hand, when the first array output signal and the second array output signal are different, the first test output signal also outputs a "high-impedance" signal.

When the output enable signal is "high" disabled, a "high-impedance" signal is always output regardless of the test mode enable signal.

The test operating as described above may compare not only two array output signals as described above but also two or more array output signals, and have a plurality of blocks comparing two array output signals as described above. Note that the test operation can be performed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can be tested in a variety of data output forms to improve the fault coverage (fault coverage) during the test.

Claims (14)

In a semiconductor memory device having a device for implementing a parallel test mode, The parallel test mode implementation device, A comparison array configured to receive a first array output signal and a second array output signal as a first input signal node and a second input signal node, respectively, and generate a comparison array output signal in response to the test mode enable signal; The first array output signal is input to the array output signal node in response to the comparison array output signal input to the output enable signal and the error detection signal node, and the same signal as the first array output signal or a high-impedance signal is generated. A first test output unit outputting the first test output signal; And In response to the test mode enable signal input to the output enable signal and the error detection signal node, the second array output signal is input to the array output signal node and is the same as the second array output signal or a high-impedance signal. Second test output unit for outputting a signal as a second test output signal A semiconductor memory device having a. The method of claim 1, The first test output unit and the second test output unit, An input unit configured to receive the array output signal and generate a pull-up signal and a pull-down signal in response to the error detection signal and the output enable signal; And An output unit configured to generate a test output signal in response to the pull-up signal and the pull-down signal A semiconductor memory device comprising a. The method of claim 2, The input unit, A NOR gate configured to generate a mode selection signal by inputting the error detection signal and the output enable signal; A first NAND gate configured to receive the array output signal and the mode selection signal; A first inverter for inverting the array output signal; A second NAND gate configured to receive an output signal of the first inverter and the mode selection signal; A second inverter for inverting the output signal of the first NAND gate to generate the pull-up signal; And A third inverter for inverting the output signal of the second NAND gate to generate the pull-down signal A semiconductor memory device comprising a. The method of claim 3, The output unit, A fourth inverter for inverting the pull-up signal; A PMOS transistor receiving an output signal of the fourth inverter through a gate and transferring a supply power to the test output signal through a source-drain path; And An NMOS transistor receiving the pulldown signal through a gate and transferring ground power to the test output signal through a source-drain path. A semiconductor memory device comprising a. The method of claim 1, The first test output unit outputs the first array output signal to the first test output signal when the first array output signal and the second array output signal are the same in a test mode, and in the normal mode. A semiconductor memory device, characterized by outputting a high-impedance signal. The method of claim 1, And the second test output unit outputs the second array output signal as the second output signal in the normal mode, and outputs a high-impedance signal in other cases. The method of claim 1, The comparison array, A comparator configured to receive the first input signal and the second input signal and compare them to generate a comparison output signal; And A comparison output unit configured to generate the comparison array output signal in response to the test mode enable signal and the comparison output signal; A semiconductor memory device comprising a. The method of claim 7, wherein The comparison unit, A first input signal detector including a plurality of transistors turned on and off according to the first input signal to sense a logic level of the first input signal; A second input signal detector including a plurality of transistors turned on and off according to the second input signal to sense a logic level of the second input signal; And It is provided with a pull-up driving unit for transmitting the power supply of the comparison unit, And comparing the first input signal and the second input signal sensed by the first input signal detector and the second input signal detector, respectively, to generate the comparison output signal. The method of claim 7, wherein The comparison output unit, A first inverter for inverting the comparison output signal; A second inverter for inverting the test mode enable signal; And A NOR gate receiving the output signals of the first inverter and the second inverter to generate the comparison array output signal A semiconductor memory device comprising a. The method of claim 8, The second input signal detector, A third inverter for inverting the second input signal; A first NMOS transistor receiving the second input signal through a gate and transferring the supply power to a first node through a source-drain path; A second NMOS transistor receiving the second input signal through a gate and transferring ground power to a second node through a source-drain path; A third NMOS transistor configured to receive an output signal of the third inverter through a gate and transfer the supply power to the second node through a source-drain path; And A fourth NMOS transistor receiving an output signal of the third inverter through a gate and transferring the ground power through a source-drain path; A semiconductor memory device comprising a. The method of claim 10, The first input signal detection unit, A fourth inverter for inverting the first input signal; A fifth NMOS transistor receiving the first input signal through a gate and opening a path between the first node and a third node through a source-drain path; A sixth NMOS transistor receiving the first input signal through a gate and transferring a signal of the second node to the comparison output signal through a source-drain path; A seventh NMOS transistor configured to receive an output signal of the fourth inverter through a gate and transfer a signal of the first node to the comparison output signal through a source-drain path; And An eighth NMOS transistor configured to receive an output signal of the fourth inverter through a gate and open a path between the second node and the third node through a source-drain path; A semiconductor memory device comprising a. The method of claim 11, The pull-up driving unit, A first PMOS transistor receiving the comparison output signal through a gate and transferring the supply power to the third node through a source-drain path; And A second PMOS transistor receiving a signal of the third node through a gate and transferring the supply power to the comparison output signal through a source-drain path; A semiconductor memory device comprising a. The method of claim 1, And the comparison array compares a plurality of array output signals. The method of claim 1, And a plurality of test blocks for comparing the array output signals.