KR20010060548A - Flash EEPROM cell and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A flash EEPROM(Electrically Erasable Programmable Read-Only Memory) cell and a fabricating method thereof is provided to improve the integration density, the property of data retention and the property of disturbance, and to reduce the time for injecting electrons by using double floating gate. CONSTITUTION: The first tunnel oxide film(12) is formed on a substrate(11), and the first polysilicon layer(13) is deposited and patterned on the first tunnel oxide film(12), so that a portion is defined. An insulating film spacer(14) is formed on the etched sidewall of the first polysilicon layer(13). The first dielectric film(15) is formed on the first polysilicon layer(13), and the second tunnel oxide film(16) is formed on the substrate(11). The second polysilicon layer(17) is deposited and patterned on the first dielectric film(15) and the second tunnel oxide film(16), so that a portion is defined. The second dielectric film(18) and the third polysilicon layer(19) are formed on the whole structure in turns, and the third polysilicon layer(19), the second polysilicon layer(17) and the first polysilicon layer(13) are etched by the self-align method. Therefore, the first floating gate(13), the second floating gate(17) and a control gate(19) are formed. A cell source drain ion injecting process is performed by the self-align method, so that a source and a drain are formed on the substrate(11).

Description

Flash EEPROM cell and method of manufacturing the same {Flash EEPROM cell and method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash ypyrom cell and a method of fabricating the same, and in particular, by using a double floating gate in which portions are overlapped and electrically separated from each other, to improve integration, and to improve data retention characteristic disturbance characteristics. The present invention relates to a flash Y pyrom cell and a method of manufacturing the same, which can improve program efficiency by reducing the time required for electron injection.

Currently, the biggest obstacle to the popularization of flash Y pyrom is the high cost per unit of information. For this purpose, high integration of cells is essential, and each manufacturer is focusing on research for this purpose. However, since the flash Y pyrom structure is relatively complicated compared to DRAM, there are many difficulties in high integration.

Currently, Intel's Strata Flash is the first level of multi-level cells to be used in products or programs, which inject very small amounts of electrons, for example, about 3000 electrons in small increments, at the desired level. Use the programming method up to. This causes a problem that takes a long time when recording a large amount of data.

As high integration of flash Ipyrom cells proceeds, F-N tunneling is generally used for program / erase to reduce the recording time per cell. However, this requires a thin tunnel oxide film, which leads to deterioration of data retention characteristics and disturbance characteristics, which may cause problems in product reliability.

Accordingly, the present invention uses dual floating gates that are partially overlapped and electrically separated to improve density, improve data retention characteristic disturbation characteristics, and reduce the time required for electron injection. It is an object of the present invention to provide a flash Y pyrom cell and a method of manufacturing the same which can increase program efficiency.

The flash ypyrom cell of the present invention for achieving the above object comprises a first floating gate formed to be electrically separated from the semiconductor substrate by a first tunnel oxide film; A second floating gate electrically separated from the semiconductor substrate by a second tunnel oxide layer, electrically separated from the first floating gate by an insulating layer spacer and a first dielectric layer, and formed to overlap a portion of the first floating gate. ; A control gate formed to be electrically separated from the first and second floating gates by a second dielectric film; And a source and a drain formed in a self-aligning manner by both ends of the control gate.

In addition, the method of manufacturing a flash ypyrom cell of the present invention comprises the steps of depositing and patterning a first tunnel oxide film and a first polysilicon layer on a semiconductor substrate; Forming an insulating film spacer on the etched sidewalls of the patterned first polysilicon layer and forming a first dielectric film thereon; Depositing and patterning a second tunnel oxide film and a second polysilicon layer; After the second dielectric film and the third polysilicon layer are formed on the entire structure, the third, second and first polysilicon layers are etched by a self-alignment method, thereby forming a first floating gate, a second floating gate, and Forming a control gate; And forming a source and a drain by performing a cell source / drain ion implantation process in a self-aligning manner.

1A to 1C are cross-sectional views of a device for explaining a flash ypyrom cell and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 2 is a graph showing a change in the threshold voltage of a split-type second floating gate located on the source side according to the potential of the first floating gate located on the drain side in FIG.

<Explanation of symbols for the main parts of the drawings>

11: semiconductor substrate 12: first tunnel oxide film

13: first polysilicon layer (first floating gate) 14: insulating film spacer

15: first dielectric film 16: second tunnel oxide film

17: second polysilicon layer (second floating gate) 18: second dielectric film

19: third polysilicon layer (control gate) 20a: source

20b: drain

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views of a flash Y-pyrom cell according to an embodiment of the present invention and a method for manufacturing the same, and FIG. 2 is a source side of a first floating gate positioned at a drain side in FIG. 1C. A graph showing a threshold voltage change of the split-type second floating gate located.

Referring to FIG. 1A, a first tunnel oxide film 12 is formed on a semiconductor substrate 11, a first polysilicon layer 13 is deposited on the first tunnel oxide film 12, and then patterned to determine a portion thereof. (define) An insulating film spacer 14 is formed on the etched sidewall of the patterned first polysilicon layer 13.

In the above, the first tunnel oxide film 12 is formed to a thin thickness suitable for reducing the recording time per cell by using F-N tunneling (F-N tunneling).

Referring to FIG. 1B, the first dielectric layer 15 is formed on the patterned first polysilicon layer 13, and the second tunnel oxide layer 16 is formed on the semiconductor substrate 11. A second polysilicon layer 17 is deposited on the first dielectric film 15 and the second tunnel oxide film 16, and then patterned to determine a portion thereof.

In the above, the second tunnel oxide film 16 need not be formed as thin as the first tunnel oxide film 16. The reason will be described later.

Referring to FIG. 1C, after forming the second dielectric film 18 on the entire structure, and forming the third polysilicon layer 19 on the second dielectric film 18, the third polysilicon is formed in a self-aligned manner. The layer 19, the second polysilicon layer 17 and the first polysilicon layer 13 are etched, thereby forming a first floating gate 13 made of the first polysilicon layer and a second polysilicon layer. The control gate 19 of the second floating gate 17 and the third polysilicon layer is completed. The cell source / drain ion implantation process is performed in a self-aligning manner so that the source 20a is applied to the semiconductor substrate 11 on the second floating gate 17 side and the semiconductor substrate 11 on the first floating gate 13 side. The drain 20b is formed.

In the above, the channel length of the first floating gate 13 is shorter than that of the first floating gate 13 and the second floating gate 17 formed by the self-aligned etching method. do. The reason will be described later.

The flash Y pyrom cell of the present invention formed by the above process is formed such that the first floating gate 13 is electrically separated from the semiconductor substrate 11 by the first tunnel oxide film 12, and the second floating gate 17 is formed. Is electrically separated from the semiconductor substrate 11 by the second tunnel oxide film 16, and electrically separated from the first floating gate 13 by the insulating film spacer 14 and the first dielectric film 15. A portion of the first floating gate 13 is overlapped to form a split-type, and the control gate 19 is formed by the second dielectric layer 18 to form the first and second floating gates 13 and 17. And a source 20a and a drain 20b are formed on the semiconductor substrate 11 in a self-aligned manner by both ends of the control gate 19, and the source 20a is formed on the second floating gate. Located on the (17) side, the drain 20b is the first floating gate 13 It is located on the side.

In the embodiment of the present invention, as a cell capable of various states, it is practical to obtain an effect of greatly increasing the degree of integration. In addition, the program characteristic of the existing split gate type cell is used to obtain the same program rate per cell. Referring to FIG.

In FIG. 2, when the potential is divided into the low potential "A" region and the high potential "B" region, the second floating result is obtained if the first floating gate 13 on the drain 20b side is in the "A" region. The gate 17 has a high threshold voltage, and the second floating gate 17 has a low threshold voltage if in the " B " region, so three potentials are possible with the original erased state, high threshold voltage and low threshold voltage. Do.

During programming, the potential of the first floating gate 13 may be divided into an "A" region and a "B" region in the first stage, and then the second floating gate 17 may be recorded for the same time in the second stage. At this time, writing of the second floating gate 17 does not require a thin oxide film because it uses channel hot electron injection. That is, since the thin oxide film is not required as the second tunnel oxide film 16, the reliability is improved. Although the first floating gate 13 using Fowler-Nordheim tunneling requires a thin oxide film (first tunnel oxide film), it is possible to ignore the influence of the threshold voltage of the first floating gate 13 at the time of reading, thereby improving reliability. have.

The program, erase, and read operations of the flash Y pyrom cell produced by the embodiment of the present invention will be briefly described as follows.

In programming, after the substrate 11 is grounded, in the first step, 3V / 5V is applied to the drain 20b and -9V is applied to the control gate 19 so that the first floating gate 13 is in the "A" region. In the second step, 5V is applied to the source 20a and 9V to the control gate 19 to complete the program.

At the time of erasing, -5V is applied to the drain 20b and about 9V to the control gate 19 in the first step to erase the first floating gate 13, and then 5V, control to the source 20a in the second step. The gate 19 is erased by adding about -9V.

In reading, after the drain 20a and the substrate 11 are grounded, 2V is applied to the source 20a and about 5V is applied to the control gate 19 to read the result. If the channel length of the first floating gate 13 is made shorter than that of the second floating gate 17, since the potential change of the first floating gate 13 does not significantly affect the readout result, a thin oxide film (first tunnel oxide film) Reliability is not a big problem.

As described above, the present invention is configured to electrically separate the first floating gate and the second floating gate, wherein the second floating gate overlaps a portion of the lower first floating gate and is split-type. The control gate is formed so as to pass over the first floating gate and the second floating gate, and the source / drain junction is formed in a self-aligned manner, so that the integration density can be increased twice as much as that of a conventional cell, and is required for electron injection. This reduces the time required to increase program efficiency and improves reliability.

Claims (8)

A first floating gate formed to be electrically separated from the semiconductor substrate by the first tunnel oxide film; A second floating gate electrically separated from the semiconductor substrate by a second tunnel oxide layer, electrically separated from the first floating gate by an insulating layer spacer and a first dielectric layer, and formed to overlap a portion of the first floating gate. ; A control gate formed to be electrically separated from the first and second floating gates by a second dielectric film; And A flash Y pyrom cell comprising a source and a drain formed in a self-aligned manner by both ends of a control gate. The method of claim 1, And the channel length of the first floating gate is shorter than the channel length of the second floating gate in the first floating gate and the second floating gate. The method of claim 1, The flash Y pyrom cell, characterized in that the first tunnel oxide film is formed thin, the second tunnel oxide film is formed thick. The method of claim 1, And the source is located at the side of the second floating gate and the drain is at the side of the first floating gate. Depositing and patterning a first tunnel oxide film and a first polysilicon layer on a semiconductor substrate; Forming an insulating film spacer on the etched sidewalls of the patterned first polysilicon layer and forming a first dielectric film thereon; Depositing and patterning a second tunnel oxide film and a second polysilicon layer; After the second dielectric film and the third polysilicon layer are formed on the entire structure, the third, second and first polysilicon layers are etched by a self-alignment method, thereby forming a first floating gate, a second floating gate, and Forming a control gate; And A method of manufacturing a flash ypyrom cell comprising the step of forming a source and a drain by performing a cell source / drain ion implantation process in a self-aligning manner. The method of claim 5, And the second floating gate is patterned so that a portion overlaps with the first floating gate and is formed in a split-type. The method of claim 5, And patterning the channel length of the first floating gate to be shorter than the channel length of the second floating gate in the first floating gate and the second floating gate. The method of claim 5, The first tunnel oxide film is formed thin, the second tunnel oxide film is thick flash cell manufacturing method characterized in that it is formed thick.