KR20010059648A - Digital IF Receiver - Google Patents

Abstract

PURPOSE: A digital IF(Intermediate Frequency) receiver is provided to digitalize a base station receiver in an IF system of a CDMA receiver. CONSTITUTION: A sampling part(110) samples an analog signal of an IF band to a digital signal. A digital signal process part(120) multiplies a sine function to a cosine function in response to the sampled digital signal, and thereby outputs digital signals(I,Q) of a base band. A filtering part(130) removes image data of the sampling part(110) from the digital signals(I,Q) applied from the digital signal process part(120). The digital signal process part(120) includes multipliers(121,122) for multiplying the sine function to the cosine function, and a digital sinusoidal oscillator(123) for generating the digital signals(I,Q). The filtering part(130) includes low pass filters(131,132) and an input output formatter(133).

Description

Digital Intermediate Frequency Receiver {Digital IF Receiver}

The present invention relates to a digital intermediate frequency (IF) receiver for Code Digital Multiple Access (CDMA).

The IF system of the conventional CDMA receiver is composed of an analog circuit. As shown in FIG. 1, the IQ mixer 11 and the low pass filter (hereinafter referred to as LPF) 13 are composed of analog circuits. First and analog to digital converters (hereinafter referred to as ADCs) 14a and 14b to convert baseband analog signals to digital analog signals. (4) outputs a 4-bit output signal.

In the above configuration, X_if is an IF band analog signal of a conventional CDMA receiver, the input signal is an analog signal having a bandwidth of 1.2288 MHz having an IF center frequency F0, and the output signal has an output sampling rate of 9.8304 MHz, and I, Q 8-bit digital baseband signals of 4 bits each.

The IQ mixer 11 receives X_if as an input and multiplies a cosine and sine function 12 equal to the IF frequency by X_if, respectively, to give an analog baseband I and Q signal.

The I and Q signals pass through LPFs 13a and 13b, which are analog filters composed of the inductance and capacitance, respectively.

The role of the LPFs 13a and 13b removes the image signal from the IQ mixer 11, and the signal passing through the LPF enters the input of the first ADC 14a.

Here, the ADCs 14a and 14b convert analog I and Q signals into digital signals, respectively, wherein the sampling rate of the first ADC is 9.8304 MHz, which is eight times the chip rate which is the output sampling rate.

The input / output formatter 15 receives an digitized I and Q signal that is implemented in an ASIC-ROM and outputs an 8-bit digital signal having an upper 4 bits of I and a lower 4 bits of Q.

However, when the analog circuit is configured like the conventional circuit, the error of the IF system due to the characteristic error of each analog component has to be taken. The error of the system degrades the characteristics of the received signal and increases the unit cost of the hardware. have. And if the input and output conditions of the IF system change, all circuits must be newly configured, and the hardware size is large because the parts are used to compose each part of the circuit.

In order to solve the above disadvantages, an object of the present invention is to provide a digitized IF system suitable for digitization of a base station receiver in an IF system that is part of a CDMA receiver.

In order to achieve the above object, the present invention, the sampling unit for sampling the analog signal of the intermediate frequency (IF) having a predetermined center frequency as a digital signal to the sampled signal using a sample conversion unit (DSP) Therefore, a digital signal processor for outputting baseband digital I and Q signals by multiplying a sine and a cosine function, and a filtering unit (FPGA) for removing an image signal from an output signal of the digital signal processor and outputting a signal at a constant sampling rate. It is characterized by including.

1 is a block diagram of a conventional analog IF receiving block;

2 is a block diagram of a digital IF receiving block to which the present invention is applied.

* Explanation of symbols for main parts of the drawings

100: digital IF receiver

110: sampling unit

120: signal conversion unit

121, 122: first and second multipliers

123: Digital Sine Wave Oscillator

130: filtering unit

131, 132: 11th and 12th low pass filter

133: 10th input / output formatter

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a digital IF receiving block to which the present invention is applied. The digital signal processor 120 outputs I and Q signals, and the filtering unit 130 removes an image of the sampling unit from the converted signal and outputs the output at a constant output rate.

Referring to the operation according to the above configuration, Xif is an IF band analog signal of a conventional CDMA receiver, the center frequency is F0, the bandwidth is B = 1.2288MHz, and the output signals are digital baseband I and Q signals, respectively. It is a 4-bit digital signal with a sampling rate of 8B = 9.8304 MHz.

Looking at each of the configuration blocks, the sampling unit 110 samples the IF analog signal of F0 for digital signal processing, using bandpass sampling, and the sampling rate is output to simplify the signal processing algorithm. 1/2 times the sampling rate (4B), that is, 4.915 MHz.

After sampling, the frequency distribution of the signal is given by Equation 1.

<Equation 1>

Center frequency = F0-n 4B n is an integer

Next, the DSP 120 multiplies a sampled signal by cosine and sine through first and second multipliers 121 and 122 to obtain a digital sinusoidal oscillator. 123), but there are various ways to obtain the DSO 123, but a fast signal processing is possible by using a table method.

At this time, the center frequency (Fdso) of the DSO 123 is a frequency satisfying the following equation (2).

<Equation 2>

0 <Fdso = F0-N4b <2B n is an integer

In addition, the filtering unit 130 has LPFs 131 and 132 which serve to remove the image signal of the mixer, which is related to the sampling rate of the sampling unit 110.

That is, since the output signal is 4 bits, the data size can be adjusted in consideration of the gate size, and the output data rate of the LPFs 131 and 132 is equal to the output sampling.

The LPFs 131 and 132 are composed of two stages of filters. The first stage 131 serves to remove the image signal of the mixer, and the second stage is an interpolation filter for matching the output sampling rate. 8B = 9.8304 MHz.

The I / Q signals from the stages 131 and 132 of the LPF are output as digital signals by the I / O formatter 133, and the output rate is 8B = 9.8304 MHz.

As mentioned above, this invention has the following effects.

First, since the analog signal processing using the existing analog device is digital signal processing using the digital device, the distortion of the received signal due to the characteristic error of the analog device can be reduced.

Second, because only FPGAs and DSPs are used, the size of the hardware can be reduced.

Third, FPGA usage can be reduced and DSP computation can be reduced.

Fourth, even if the IF frequency F0 changes, the software can be used as is by changing the software.

Claims (3)

A sampling unit for sampling an analog signal of an intermediate frequency IF having a predetermined center frequency as a digital signal; A digital signal processor for outputting baseband digital I and Q signals by multiplying a sine and a cosine function according to the sampled signal using a signal converter (DSP); And And a filtering unit (FPGA) which removes an image signal from an output signal of the digital signal processing unit and outputs a signal at a constant sampling rate. The method of claim 1, wherein the filtering unit A first low pass filter for removing an image signal from an output signal of the digital signal processor; A second low pass filter for adjusting a sampling rate of the output signal; And an input / output format for outputting the output signal of the second low pass filter with a predetermined bit. The method of claim 1, And a sampling rate of the digital signal processor is 1/2 of an FPGA output signal sampling rate.