KR20010059512A - Sdram device - Google Patents

Abstract

PURPOSE: A SDRAM(Synchronous Dynamic Random Access Memory) device is provided, which can omit a precharge term generated between the (N-1)th row and the Nth row by activating lower cells along the row direction of the (N-1)th and upper cells along the row direction of the Nth simultaneously. CONSTITUTION: The SRAM device includes a number of column lines(Column0-ColumnN) to select a number of cells along a column direction in a memory cell array structure and a number of split row lines(Rowt_0-Rowt_N)(Rowb_0-Rowb_N) to select a series of lower cells and upper cells along a row direction. By being synchronized to a falling edge of a clock signal(CLK), a /CS(chip select) and a /RAS(row address strobe) are enabled to a low level and a CAS(Column Address Strobe) signal and a WE(Write Enable) signal are enabled to a high level and thus a DQM(input mask & output enable) signal becomes a high level. Then, the split row signal becomes in an enable state(S_REC) by the high level of the DQM signal. And, if (N-1)th row(RowN-1) is inputted, after activating upper cells corresponding to the (N-1)th row array, the lower cells of the array are activated and at the same time a row of upper cells corresponding to the Nth row array is enabled.

Description

SDRAM device {SDRAM device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous dynamic random access memory (SDRAM), and more particularly, to an SDRAM device capable of high speed operation by shortening a precharge period.

In memory devices used to temporarily or permanently store data and commands in computers, communication systems, image processing systems, etc., DRAM (Dynamic Random Access Memory) has recently been synchronized with the bus clock as much as possible to improve speed. SDRAM is designed to lock the DRAM speed to an integer multiple of the clock, eliminating the time required for system clock synchronization by the DRAM controller and adding time to interleaving control.

The features of this SDRAM include: 1) input / output circuits synchronized with an external clock, 2) burst access (high speed of continuous data access), 3) multi-bank configuration, 4) instruction type access (mode register programming), 5) Pipeline data paths.

In a typical DRAM / RAS is set to "low-level" memory is activated and the time is a clock cycle time corresponding to the time until the input of the low place becomes / CAS command to drop the t _RCD in the SDRAM when he t _RCD It is given as an integer multiple, and the time until valid data is output after the read command is input is called CAS latency (hereinafter referred to as CL), which is also given as an integer multiple of the clock cycle time.

1 is a waveform diagram illustrating an operation process of a conventional SDRAM.

As shown in FIG. 1, when the _RCD = 3 and CL = 3 and the burst length BL is 4 by four consecutive data, the operation of the SRDAM is as follows. When the active command ACT and the low data ROW of the DRAM are input at the rising edge of the C ₁ clock and the memory is set to the active state, the word line is selected by the row. If the read command (READ) is input from the C ₄ clock after 3 clocks, the column data (CAS) is also input, so all addresses of the first data of the burst read are input. Since the clock C is continuously output (B1, B2, B3, B4 ) the data while increasing the column address by one every clock from _7. In DRAM, when the / RAS transitions to the "high level", the precharge operation starts, but in the SDRAM, the precharge command PRE is input at the clock C ₉ to change the current state to the precharge state. Of course, in the case of the automatic precharge command, after the data of the burst length determined according to the read / write command is automatically read, the precharge state is automatically entered, and thus no additional precharge command is required.

FIG. 2 is a diagram illustrating a method of selecting a column after activating a row according to a row address in a cell array of a conventional SDRAM, in which a chip set accesses data of a specific memory cell in a conventional SDRAM. To do this, select row (Row0, Row1,… RowN-1, RowN) to enable the word line in the bank, for example, Row0, and then select the column of the cell (Column0, Column1… ColumnN-1, ColumnNN) again. I read the cell data.

On the other hand, conventionally, after a bank receives an active command, t _RAS can receive a charge command at any time, and a minimum t _RP (RAS precharge time) is required to completely precharge the bank while / RAS is at a high level. When the precharge cycle is completed, the corresponding bank is in an idle state and a new row address can be input.

However, the recent trend in semiconductor memory devices has been required to reduce the precharge period.

The present invention can simultaneously activate lower cells in the N-1th row direction and upper cells in the Nth row direction, thereby eliminating a precharge period occurring between the N-1th row and the Nth row. In providing.

1 is a waveform diagram illustrating an operation process of a conventional SDRAM;

2 is a view for explaining a method of selecting a column after activating a row in a cell array of a conventional SDRAM;

3 is a view for explaining a method for activating a split row in an SDRAM device according to the present invention;

4 is a waveform diagram for activation of a split row in an SDRAM device according to the present invention;

In order to achieve the above object, the present invention provides a memory cell array, a plurality of column lines for selecting a plurality of columns in a series of column directions in a memory cell array, and a memory cell array in a unit structure of a cell array of an SDRAM. And a plurality of split row lines Row0, Row1, ... RowN-1, RowN for separately selecting a series of lower and upper cells in a row direction.

In the cell array of the SDRAM of the present invention, the row of the N-th lower cells and the row of the N-th upper cells are simultaneously enabled.

According to the present invention, in response to the enable of the internal command signal DQM, the N-th row and the N-th row can be activated at the same time. The precharge occurring in between can be omitted, which can greatly shorten the data access time in the memory device.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

3 is a view for explaining a method of activating a split row in the SDRAM device according to the present invention.

The SDRAM device according to the present invention has a plurality of column lines (Column0, Column1 ... ColumnN-1, ColumnN) for selecting a plurality of columns in a series of column directions in a memory cell array structure, and a series of lower cells and a top row in a row direction. A plurality of split row lines (Rowt_0, Rowt_1, ... Rowt_N-1, Rowt_N) (Rowb_0, Rowb_1, ... Rowb_N-1, Rowb_N) for separating and selecting the cells are included.

4 is a waveform diagram for activation of a split row in an SDRAM device according to the present invention.

3 and 4, the SDRAM device of the present invention operates as follows.

That is, / CS (chip select) and / RAS (row address strobe) are enabled at the low level in synchronization with the falling edge of the clock signal CLK, and the column address strobe (CAS) signal and the write enable (WE) are enabled. ) Input signal becomes high level, input mask & output enable (DQM) becomes high level.

Then, the split low signal is enabled (S_REC) due to the high level of the DQM signal. When the N-1th row is input, the top cells corresponding to the N-1th row array are activated internally, and then the bottom cells of the array are activated and the Nth row is activated. It simultaneously enables the rows of the top cells corresponding to the row array.

For example, the SDRAM of the present invention is a word of a low line (Rowt_0) that selects only the cells of the upper part in the first row array divided into the upper and lower cells when the DQM is high level and the first row (Row 0) is input. The line is enabled, the word line Row_0 of the lower portion is enabled, and Rowt_1, which selects only the top cells from the second row Row1, is enabled.

Therefore, the SDRAM device of the present invention can omit the precharge cycle between the first row and the second row when the split row signal is activated (S_REC) by a specific DQM signal, thereby increasing the data access speed continuously.

On the other hand, as shown in Fig. 4, after synchronizing the falling edge of the clock signal CLK, / CS and / RAS become low level and the bank is enabled, the CAS signal and the WE signal go high level. When the DQM is at low level, the split low line is in a disabled state (N_REC), which operates as normal SDRAM. That is, when the N-1 th row is input, the upper and lower cells of the N-1 th row array are simultaneously activated. At this time, the upper cells of the next Nth row line are not enabled. The Nth low signal is activated after the N-1th row is deactivated and passes through the precharge cycle.

As described above, the present invention can variably omit the precharge period between the N-1 th row and the N th row or execute the precharge as before, thereby reducing the data access time of the memory device.

Claims (2)

In an SDRAM device, Memory cell arrays; A plurality of column lines for selecting a plurality of cells in a series of column directions in the memory cell array; And And a plurality of split row lines for separately selecting a series of lower and upper cells in a row in the memory cell array. 2. The SDRAM device of claim 1, wherein a row of N-th bottom cells and a row of N-th top cells are simultaneously enabled in the cell array of the SDRAM.