KR20010059177A - Data output controller - Google Patents

Abstract

PURPOSE: A device of controlling a data output is provided to sense a variation in an internal operation frequency, and differentiate and apply an activation timing of a data output enable signal for a high frequency and a low frequency, thereby securing a stable tOH and achieving a high speed of tAC. CONSTITUTION: In a device of controlling a data output, a device of determining an operation frequency determines a variation in an internal operation frequency depending on a change in a period of a clock signal. A device of controlling a timing has an information of the internal operation frequency and controls an activation timing of an output enable signal for controlling an activation of a data output buffer depending on the signal output from the device of determining an operation frequency.

Description

Data output controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output control device that significantly shortens an access time in order to realize a high speed semiconductor integrated circuit. The present invention relates to a data output control device which significantly shortens the data access time by relatively speeding up the activation timing of the enable signal.

In general, conventional semiconductor memory devices, such as DRAM (SRAM) and Static Random Access Memory (SRAM), match data signals read from memory cells therein with peripheral circuits installed externally. In order to provide a data output buffer, the data output buffer is provided to adjust the voltage level of the data signal read from the memory cell to a voltage level required by an external peripheral circuit.

However, according to the related art, an external clock is controlled under a cas latency (CL) and a read command signal in a state where data output from a pipe register is constantly latched at an input terminal of the data output buffer. Due to the fact that the transfer transistor in the data output buffer is activated by an output enable signal generated with a predetermined time delay from the data signal, the data signal that passes through the data output buffer after passing a predetermined delay must be passed. The data is output to the data input / output pad (DQ pad).

That is, the output enable signal doen latches the data signal received from the internal circuit for a predetermined time after the application of an external clock and then receives a new data signal. Thus, tOH (tOH) is a parameter required for stable data output operation. To ensure the retention time of the data.

However, as memory chips operating at high frequencies have been developed in accordance with the trend of high speed, both parameter characteristics that determine access time (hereinafter referred to as 'tAC') and data retention time (hereinafter referred to as 'tOH') are satisfied. It is difficult to let the situation.

This means that even if the data is latched to the first input terminal of the data output buffer at a very high speed, the data output enable signal may occur after a predetermined time after the application of an external clock signal (determined according to cas latency), which is a reference of the data output, as described above. Since the doen is generated, the time for outputting data through the data output buffer is constant in both low frequency operation and high frequency operation. Therefore, in case of high frequency operation, if the time required in the operation process is not reduced, It becomes difficult to satisfy the accelerated tAC.

As described above, there is a limit in activating the data output enable signal (doen) at high speed, and also the data output to eliminate the constant delay time required for activating the data output enable signal (doen). If the buffer is controlled to output the data signal to the outside without the control of the data output enable signal (doen), it is difficult to secure a constant tOH, causing another operational problem, which impairs the stability of the operation as a whole. This happens.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to detect a change in an internal operating frequency and apply activation timing of a data output enable signal to a high frequency above a predetermined frequency and a low frequency below a certain frequency. In addition, the present invention provides a data output control device that realizes high-speed tAC while securing stable tOH.

In order to achieve the above object, the data output control apparatus according to the present invention comprises an operating frequency discriminating means for discriminating the change in the internal operating frequency by the periodic change of the external input clock signal;

And timing adjustment means for controlling the activation timing of an output enable signal having information of an internal operating frequency and controlling whether or not the data output buffer is activated according to a signal output from the operating frequency determination means.

1 is a signal waveform diagram showing an activation timing of control clock signals used in the present invention.

Figure 2 is a circuit diagram according to an embodiment of the operating frequency determination means used in the present invention

3 is a signal timing diagram showing a high frequency operation in the data output control apparatus according to the present invention;

4 is a signal timing diagram showing low frequency operation in the data output control apparatus according to the present invention;

<Description of Symbols for Major Parts of Drawings>

10: latch portion 20: buffering portion

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a signal waveform diagram illustrating activation timing of various control clock signals used in the present invention. As shown in (a), a row activation command signal is applied at one clock of an external clock signal ext_clk applied with a predetermined period. When (rowatv6) is input as shown in (b), after 2n hours from the row activation command signal rowatv6, the first internal clock signal clk_2n of the logic high level is made like the waveform of (c). Will be generated.

Then, the second internal clock signal clk_4n of the 'logic high' level after 4n hours and the third internal clock signal clk_6n of the 'logic high' level after 6 n hours are generated to generate the waveforms of (d) and (e), respectively. In this case, the second internal clock signal clk_4n is controlled to be disabled at the moment when the third internal clock signal clk_6n is enabled.

In addition, another internal clock signal clk_p shown in (f) is a clock signal generated by sensing a rising edge of an external clock signal generated immediately after the row activation command signal rowatv6 is applied. As a result, the periodic change of the internal operating frequency can be determined by the timing of activation of the clock signal clk_p.

Hereinafter, an internal operating frequency sensing operation according to the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 shows a circuit diagram according to an embodiment of the operating frequency determination means used in the present invention, is connected in series between the node (N1) between the power supply voltage (Vcc) applying terminal and the ground terminal (Vss) The PMOS transistor MP1 to which the internal clock signal clk_2n shown in the waveform of FIG. 1 (c), which is activated after 2n hours after the low activation command signal rowatv6 is applied, is applied to each gate terminal. An NMOS transistor MN1; The internal clock signal illustrated in (d) of FIG. 1 (d) is connected in series between the NMOS transistor MN1 and the ground terminal Vss and is generated by adding a delay of 2n hours to the internal clock signal clk_2n. Two NMOS transistors (clk_2n) and an internal clock signal (clk_p), which is activated at a rising edge of the next clock to which the row activation command signal rowatv6 is applied and determines a cycle change, is applied to each gate stage. MN2, MN3); A latch unit 10 which latches the potential of the connection node N1 of the PMOS transistor MP1 and the NMOS transistor MN1 constantly; And a buffering unit 20 for buffering and outputting a signal constantly latched by the latch unit 10.

The latch unit 10 is connected between an inverter IV1 for inverting the potential of the node N1, a power supply voltage Vcc, and a ground terminal, and an output signal of the inverter IV1 is fed back to the gate terminal. A PMOS transistor MP2 is provided.

In addition, the buffering unit includes two inverters IV2 and IV3 connected in series to the output terminal N2 of the latch unit 10.

With this arrangement, since the internal clock signal clk_2n is at the logic low level before the low activation command signal rowatv6 is input, the potential of the node N1 is maintained at the potential state of logic high. The final output signal 6n_en of the operating frequency discrimination means maintains the state of 'logic low'.

Thereafter, the internal clock signal clk_2n is activated as 'logic high' after 2n time after the row activation command signal rowatv6 is input, and after 4n, another internal clock signal clk_4n is 'logic high'. 'Will be applied.

In this state, the internal clock signal clk_p for detecting the clock period, which has another delay time, is activated before the internal clock signal clk_6n is activated to disable the previously activated internal clock signal clk_4n. When applied in a state, the final output signal 6n_en of the operating frequency discrimination means transitions from 'logic low' to 'logic high' in accordance with the activation timing of the internal clock signal int_p for detecting the clock period.

As described above, the fact that the final output signal 6n_en of the operating frequency discriminating means is 'logic high' means that the period of the operating frequency is shorter than the predetermined delay time 6n, that is, high frequency operation.

On the other hand, when the internal clock signal clk_6n is activated before the clock period detection internal clock signal clk_p to disable the previously activated internal clock signal clk_4n, the final operation frequency determination means The output signal 6n_en still maintains the "logic low" potential state.

This state means that the period of the internal operating frequency is longer than the above-described constant delay time 6n, that is, low frequency operation.

By the above operation, the final output signal 6n_en is output at different potentials according to the operating frequency, whereby a change in the internal operating frequency can be discriminated.

As described above, the output signal 6n_en of the operating frequency discriminating means having information on the internal operating frequency and generated at different potential states for each high frequency and low frequency operation controls whether the data output buffer is activated according to the potential state. The timing adjustment means is provided to control the timing of activation of the output enable signal.

Accordingly, the timing adjusting means is complementarily activated according to the logic state of the output signal 6n_en of the operating frequency discriminating means, and externally for data output control in the 'logic low' state of the output signal 6n_en indicating low frequency operation. Logic high of the first data transfer unit for activating the data output enable signal doen_6nu at the rising edge of the clock signal ext_clk and transferring it to the input terminal of the data output buffer, and the output signal 6n_en indicating high frequency operation. In the 'state, a second data transfer unit for activating the data output enable signal doen_6nd at the falling edge of the clock signal immediately before the external clock signal ext_clk for data output control and transferring it to the input terminal of the data output buffer is provided. .

3 and 4 are signal timing diagrams showing a high frequency operation and a low frequency operation of the data output control apparatus according to the present invention. Hereinafter, the timing control operation of the data output buffer for each internal operating frequency will be described in detail. Let's look at it.

First, referring to the signal timing diagram of FIG. 3, the period of the external clock signal ext_clk is shortened due to the high frequency operation with the cascade latency of 3 and the internal operating frequency of 200 MHz, as shown in (f). The internal clock signal clk_p for periodic detection is activated faster than the disable point of the internal clock signal clk_4n shown in (d).

Accordingly, after the column activation command signal casatv6 is inputted, the data output buffer is activated at the rising edge of the third clock (clock shown by 'B' in the figure) with the cascade latency CL being three. It will be normal operation to generate the output enable control signal doen to control, but in the process of the data output control apparatus according to the present invention a large difference in operation occurs.

The difference is determined by the timing adjusting means when the final output signal 6n_en of the operating frequency discriminating means is output as 'logic high' when it is determined to be a high speed operation through the operating frequency discriminating means. Only the data transfer section is selectively activated, which is constant from the falling edge of the previous clock (the clock shown by 'A' in the figure), immediately before the external clock signal (the clock shown by 'B' in the figure). After the time delay, the output enable control signal doen_6nd is generated at high speed as shown in (h).

Meanwhile, referring to the signal timing diagram of FIG. 4, the period of the external clock signal ext_clk is longer than that of the high frequency operation illustrated in FIG. 3 due to the low frequency operation with the cascade latency of 3 and the internal operating frequency of 100 MHz. , as shown in (f), the internal clock signal clk_p for detecting the clock cycle is activated later than the disable point of the internal clock signal clk_4n shown in (d).

As a result, the operating frequency discriminating means determines the operating frequency of the low frequency and outputs the final output signal 6n_en as 'logic low', and receives the received timing adjustment to adjust the activation timing of the output enable control signal. The means selectively activates only the first data transfer unit, and activates the data output buffer at a time period delayed at the rising edge of the external clock signal (clock shown by 'B' in the figure) as in the usual case. The output enable control signal doen_6nu is generated slowly as shown in (h).

As a result, as can be clearly seen from the signal timing diagrams of FIGS. 3 and 4, the operation of the high frequency operation is performed in which the period of the operating frequency is equal to or less than a predetermined time (this description assumes this time as '6n time'). In this case, since the data output enable control signal doen_6nd is activated at the falling edge of the clock immediately before the output control external clock, the period of the operating frequency can be activated with a much faster timing than the low frequency operation longer than the 6n time. In addition, it is possible to significantly reduce the data access time (tAC) while ensuring a stable data retention time (tOH).

As described above, according to the data output control apparatus according to the present invention, by detecting the period change of the internal operating frequency to generate the enable control signal of the data output buffer with a different timing according to the result, the data retention time While maintaining a stable level, the data access time can be significantly reduced for high speed operation.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (3)

Operating frequency discriminating means for discriminating the change in the internal operating frequency by the change in the period of the external input clock signal; And a timing adjusting means for controlling the activation timing of an output enable signal for controlling whether or not the data output buffer is activated according to a signal output from the operating frequency discriminating means having information of an internal operating frequency. Device. The method of claim 1, The first PMOS transistor and the first operating frequency discriminating means are connected in series between a power supply voltage supply terminal and a ground terminal, and the first clock signal, which is activated 2 n hours after the application of the low activation command signal, is applied to each gate terminal. 1 NMOS transistor, Rising of the second clock signal which is connected in series between the first NMOS transistor and the ground terminal and is generated by adding a delay time of 2n to the first clock signal and the next clock to which the low activation command signal is applied. Second and third NMOS transistors having a third clock signal activated at an edge portion and determining a change in period, applied to each gate end thereof; A latch unit for constantly latching a connection node potential of the first PMOS transistor and the first NMOS transistor; And a buffering unit for buffering and outputting a signal constantly latched by the latching unit. The method of claim 1, The timing adjusting means is complementarily activated according to the logic state of the output signal of the operating frequency discriminating means; A first data transfer unit for activating a data output enable signal at a rising edge of an external clock signal for data output control and transferring the data output enable signal to an input of the data output buffer in a first logic state in which low frequency operation is determined; In a second logic state in which high frequency operation is determined, a second data transfer unit is configured to activate a data output enable signal at a falling edge of a clock signal immediately before the external clock signal for data output control, and transmit the data output enable signal to an input terminal of the data output buffer. And a data output controller.