KR20010058233A - Gigabit Ethernet Architecture Including of Layer 3 Forwarding Engine with 2-Way Path - Google Patents

Abstract

PURPOSE: A structure of a giga-bit Ethernet having a three-layer forwarding engine with a two-way type is provided to guarantee a bandwidth of giga-bit speed, by putting a forwarding engine between a MAC(Media Access Controller) layer protocol and a FIFO register, in order to directly route a packet inputted to a MAC and forward the packet to the FIFO register. CONSTITUTION: A physical coding sub-layer(21) processes a line coding operation. A giga-bit Ethernet MAC part(22) generates and detects MAC protocol data. A three-layer IP(Internet Protocol) forwarding engine part(23) detects and forwards a three-layer IP. A processor(25) processes messages such as ICMP(Internet Control Message Protocol) and an ARP(Address Resolution Protocol). A MAC FIFO control logic part(24) stores a protocol message by arbitrating priority of a high-speed path. A clock and test connection part(27) supplies a system clock. A processor connection part(26) includes a register a counter which manage network information, and makes connection to a processor.

Description

Gigabit Ethernet Architecture Including of Layer 3 Forwarding Engine with 2-Way Path}

The present invention relates to Ethernet-based packet forwarding in network technology. In particular, a three-layer forwarding engine is referred to as a gigabit Ethernet media controller (MAC) to implement fast three-layer forwarding that satisfies gigabit-speed traffic. Dual path method that guarantees gigabit speed bandwidth through distributed processing of message traffic using efficient 3-layer forwarding engine structure of 2-way path by eliminating delay and processing time by installing inside A gigabit Ethernet architecture with a three-layer forwarding engine is provided.

Communication between complex and diverse desktop computing applications, which are rapidly increasing in recent years, mainly depends on LAN (Local Area Network), and it is required to increase signal bandwidth due to the increase of traffic volume with the activation of internet and intranet. In the LAN network, which is connected based on a shared medium, the congestion problem cannot be solved. Therefore, it has developed into a switch type device having an advantage of providing a specific bandwidth.

In addition, switch-type devices have also been developed into a network technology using Fast Ethernet with a bandwidth of 100 Mbps.

However, as networking technology using 100Base-T technology between servers or desktops has become commonplace, higher speed network technology is required at the backbone and server levels, and a Gigabit Ethernet system has been developed that provides 1.25Gbps of bandwidth. .

Increasing traffic between subnets also necessitates performance improvements in bridge and router functionality in Gigabit Ethernet systems.

Thus, many improved inventions of Gigabit Ethernet and router technology have been proposed and the combination of these components improves the performance of routers based on Gigabit Ethernet. However, the combination of fast components can cause latency or processing delay due to MAC and forwarding engine component connection. There is a problem that it is difficult to solve the factor (Latency).

Referring to FIG. 1 attached to the above-mentioned problem, FIG. 1 is a diagram illustrating an example of a conventional Ethernet-based router structure that is generally configured.

In the overall configuration, when the packet stream data 17 received through the MAC 11 of the Ethernet is stored in the receiving buffer 12 and notified to the processor 13 by an interrupt or the like, the processor 13 opens the receiving buffer. The packet frame is stored in the memory 152 of the packet forwarding unit 15.

The processor 13 accesses the memory 152 of the packet forwarding unit 15 and sends a destination address read from the IP header to the lookup processing unit 16 to search the lookup table memory 162 by the lookup controller 161. Get in At this time, the cache memory 14 is placed adjacent to the processor 13 to shorten the lookup search time by one hit.

Thereafter, when the lookup process is completed, the processor 13 passes the resulting next hop and port information to the routing controller 151 to modify the packet data in the packet storage memory 152.

At this time, the modified information includes Next HOP change, TTL (Time to Live) reduction, checksum recalculation, and the like. The routing controller 151 forwards the processed packet to the forwarding buffer 153. To allow the packet to be forwarded.

In this case, the conventional gigabit Ethernet-based router operating as described above has a line speed of 1.25 Gbps of input bit unit data. In the related art, the Ethernet and forwarding engine components having their respective components separated from each other are connected to each other when necessary. The fast processor reads the output packet from the MAC 11, stores the packet in another memory, performs the third layer routing and forwarding process, or reads the packet from the FIFO inside the MAC layer to the system FIFO and uses it as an input of the forwarding engine.

Therefore, the processing of these forwarding packets between the MAC and the forwarding engine may result in a gigabit wire-speed forwarding implementation even when an external fast forwarding engine component is applied due to memory access time, copy time, or delay time due to packet separation and combining. There is difficulty.

An object of the present invention for solving the above problems is that the forwarding engine reads an output packet from FIFO (First In First Out) inside the MAC of Ethernet or a packet stored in the external memory by the external processor from the MAC to the IP (Internet). Protocol) Unlike the existing method of forwarding processing based on header classification and lookup, a forwarding engine is installed between the Gigabit Ethernet MAC layer protocol and the MAC FIFO to directly route Layer 3 packets to the MAC and forward them to the MAC FIFO. It is to provide a gigabit Ethernet structure having a dual-path three-layer forwarding engine to ensure the bandwidth of the gigabit speed through the distributed processing of message traffic.

1 is a view illustrating the structure of a conventional conventional Ethernet and three-layer forwarding engine

2 is a diagram illustrating a gigabit Ethernet structure having a three-layer forwarding engine of a 2-way path type according to the present invention.

3 is a diagram illustrating a structure of a 2-way forwarding engine for ensuring a gigabit forwarding speed according to the present invention.

4 is a flowchart of a receiver data according to the present invention.

5 is a flowchart of a transmitter data according to the present invention.

In order to achieve the above object, a dual path type forwarding engine configuration method according to the present invention is characterized in that, in a Gigabit Ethernet system, receiving MAC data streams received at a predetermined rate of 32 bits and receiving packet classification, lookup control, and packets. A first step of receiving a fast path for forwarding and a low speed path for packet processing and forwarding by a processor by receiving a data stream other than normal forwarding; Transmitting a normal forwarding through a fast path through packet classification and lookup information by an IP header; And a third process of processing an exception protocol, ICMP, ARP, etc. through a slow path by the processor through packet classification and lookup information based on the IP header, to distribute traffic of three-layer IP routing and forwarding messages. .

A feature of the configuration method of Gigabit Ethernet having a dual-path three-layer forwarding engine according to the present invention for achieving the above object is that receives a MAC data stream received at a predetermined rate of 32 bits, packet classification, lookup control, packet forwarding A low-speed path for receiving a data stream other than the normal forwarding and normal forwarding, and for processing and forwarding the packet by a processor; A first step of processing 8-bit or 10-bit line coding (encoding / decoding) by connecting a predetermined bit electrical signal of a specific speed obtained by converting an optical signal of a specific frequency band of a link; A second step of generating and detecting a protocol control medium data by accessing 8-bit data of a specific speed processed through the first step; A third process of accessing 32-bit data having a predetermined rate generated through the second process to perform a three-layer IP search and forwarding process; A fourth process of processing a message such as an exception protocol, an internet control message protocol, an address resolution protocol, or the like from the data processed through the third process; And storing a protocol message by arbitration processing of a predetermined high speed path and a high speed path among predetermined data among data processed through the third process and the fourth process.

A feature of the dual-path three-layer forwarding engine structure according to the present invention for achieving the above object is a fast path for receiving MAC data streams from the MAC controller at 32 bits of 31.25 MHz and performing packet classification, lookup control, and packet forwarding. And a slow path that receives a data stream other than normal forwarding and processes and forwards the packet by a processor; A MAC FIFO for arbitrating, collecting data output from each path and outputting the data to the switch fabric; A packet classifier for searching an IP header in the data stream received from the MAC controller to check packet validity, determine a course, and send a destination IP address to a lookup controller to search a lookup table if it is determined to be a valid packet; The normal forwarding message and the local processing message are classified through real-time lookup. In the case of normal forwarding, packet forwarding is performed according to the lookup result, and the packet forwarder outputs the MAC to the MAC FIFO by attaching a header containing the output port information or packet information. In this case, an error processed message in the packet classifier or a message classified as local processing in a lookup process is sent to a low speed path through a MAC FIFO to be processed by a processor.

An additional feature of the dual-path three-layer forwarding engine structure according to the present invention for achieving the above object is that the packet processing includes the next hop address replacement, packet TTL reduction, checksum byte recalculation, and the like. To do it.

A gigabit Ethernet structure having a dual-path three-layer forwarding engine according to the present invention for achieving the above object is connected to a 125MHz speed 10-bit electrical signal converted from the optical signal of 1.25Gbps of the link line 8B10B Physical coding sublayer means for processing coding (encoding / decoding); A Gigabit Ethernet media controller for generating and detecting protocol data for media control by accessing 8-bit data of 125 MHz speed processed by the physical coding sublayer means; A high-speed three-layer IP forwarding engine means for accessing 32-bit data at 31.25 MHz of the Gigabit Ethernet media controller and performing three-layer IP search and forwarding processing; A low-speed processor processing means connected to said three-layer IP forwarding engine means to handle message processing such as exception protocols, Internet control message protocols, and address resolution protocols; And a MAC FIFO control logic unit for accessing the three-layer IP forwarding engine means and the processor processing means, respectively, and storing protocol messages by arbitration processing of fast path priority.

Additional features of a Gigabit Ethernet architecture having a dual path three layer forwarding engine according to the present invention for achieving the above object include: a clock and test connection supplied to the system; The processor further includes a processor connection unit that includes a register and a counter for network information management and provides a connection function with the processor.

First, the technical concept to be applied in the present invention will be briefly described. The present invention reduces the connection latency or processing latency between the MAC and the forwarding engine and guarantees gigabit bandwidth in the conventional general structure. The purpose is to improve the performance of Ethernet-based routers.

Therefore, the forwarding engine structure has a 2-way path efficient traffic distribution structure, preventing normal packet forwarding processing from delaying the traffic of packets that do not require real-time processing such as exception protocol or ICMP. This is to allow forwarding to take place at gigabit speed.

Therefore, to summarize the technical concepts applied in the present invention, a three-layer forwarding engine is installed between the MAC protocol and the FIFO queue of the MAC to directly access MAC data to classify three-layer (IP) headers and perform lookup search. After that, the forwarding message is forwarded to the FIFO of the MAC, and the exception protocol or ICMP error handling message, which is not the forwarding message, is sent to the message processing by the internal processor.

In addition, the messages processed by the internal processor are stored as MAC FIFOs when there are no forwarding messages, and the output of the final FIFO ensures that the forwarding messages and exception protocol messages are transmitted at a rate that guarantees gigabit bandwidth without additional time delays. Is the second.

Therefore, the two-way path (fast path for forwarding and slow path as a message processing process through the processor) is distinguished so that the fast path of the forwarding message does not interfere with the processing of gigabit speed by an exception protocol or the like. That is the purpose.

Hereinafter, a gigabit Ethernet structure having a dual-path three-layer forwarding engine according to the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a gigabit Ethernet structure having a three-layer forwarding engine of a 2-way path type according to the present invention, and FIG. 3 is a dual path guaranteeing a gigabit forwarding speed according to the present invention. Exemplary 2-way path forwarding engine structure.

In the Gigabit Ethernet structure having a three-layer forwarding engine of a two-way path method according to the present invention shown in FIG. 2, in order to realize a three-layer IP forwarding process of gigabit speed in a gigabit Ethernet, FIG. Unlike the structure of the conventional Ethernet router system shown in Fig. 1, the 8B10B line coding (encoding / decoding) is performed by connecting to a 125MHz 10-bit electrical signal converted from a link's 1.25Gbps optical signal. A Gigabit Ethernet MAC unit 22 for generating and detecting MAC protocol data by connecting to a physical coding sublayer (PCS) unit 21 for processing and 8-bit data at 125 MHz of the physical layer PCS 21. And a three-layer IP forwarding engine 23 of a high-speed path that connects to 32-bit data of 31.25 MHz speed of the Gigabit Ethernet MAC unit 22 and performs three-layer IP search and forwarding. A low-speed processor processor 25 that is connected to the three-layer IP forwarding engine unit 23 and handles messages such as exception protocols, ICMP (Internet Control Message Protocol), and ARP (Address Resolution Protocol); and A MAC FIFO control logic unit 24 is connected to the three-layer IP forwarding engine unit 23 and the processor processing unit 25 to store protocol messages by fast path priority arbitration. And a processor connection section 26 for providing a clock and test connection section 27, a register and a counter for network information management, and a connection function with a processor.

The Gigabit Ethernet structure having a 2-way forwarding 3-layer forwarding engine according to the present invention shown in FIG. 2 is different from a conventional router or an Ethernet system. There is a high-speed three-layer IP forwarding engine 23 between the logic 24 and a low-speed processor processor 25 for exception protocol processing to store packets processed in two blocks in the MAC receive FIFO by arbitration.

In this way, the packet output from the MAC FIFO is already a three-layer IP routed message and can be directly connected to a commercial switch fabric without a separate component connection.

FIG. 3 is an efficient two-way path that guarantees the proposed gigabit forwarding speed to implement a gigabit Ethernet structure having a two-way forwarding three-layer forwarding engine proposed in the present invention. Forwarding engine structure diagram.

The configuration shown in FIG. 3 is a high speed method for receiving the MAC data stream from the MAC controller 31 at 32 bits of 31.25 MHz and performing packet classification 321, lookup control 322, and packet forwarding 324. Fast path 32, which is classified as a slow path 33 that receives data streams other than normal forwarding and processes and forwards packets 332 by the processor 331, and outputs data from each of these paths. It is composed of MAC FIFO 34 and the like to arbitrate gather and output to the switch fabric (35).

The data stream received from the MAC retrieves the IP header in the packet classifier 321 to check the packet validity and determine the path. If the packet is valid, the destination IP address is sent to the lookup controller 322 to look up the lookup table 323.

At this time, normal forwarding message and local processing message are classified through real-time lookup. In case of normal forwarding, packet processing is performed by packet forwarder 324 (Next Hop address replacement, TTL reduction of packet, recalculation of checksum byte) by lookup result. And a header containing the output port information or packet information is attached to the MAC FIFO 34.

The message processed by the packet classifier 321 or the message classified as a local process in the lookup process 322 is sent to the low speed path 33 to be processed by the processor 331 to process the message 332. At this time, the fast path 32 is configured by hardware processing to ensure the gigabit speed.

With reference to FIGS. 4 and 5 attached to the transmission and reception of data in a gigabit Ethernet structure having a dual-path three-layer forwarding engine according to the present invention configured as shown in FIG. 2 and FIG. do.

4 is a flowchart illustrating a receiver data according to the present invention.

The main components for the flow of data are the output receiver connection 49, MAC FIFO 48, MAC FIFO arbiter 47, forwarding engine FIFO 45, MAC receiver 44, PHY receiver 43, and It consists of a processor processing part FIFO 46.

Looking at the flow of each data signal between the above-described components, the bus denoted by reference numeral 401 is a data bus connecting the PHY receiver 43 and the MAC receiver 44 is an 8-bit received from the channel (Channel) It serves to convey. At this time, the PHY receiver 43 transmits the GMII receiver control signal indicated by reference numeral 402 indicating that the current data of the current bus is valid to the MAC receiver 44.

The bus 403 denotes a data bus line for transferring data written to the forwarding engine unit FIFO 45 at the MAC receiver 44, and the signal 404 is the forwarding. The signal for control of the data frame transmitted to the engine unit FIFO 45, and the signal indicated by reference numeral 405 is to the MAC receiving unit 44 that the forwarding engine unit FIFO 45 is ready to receive the data frame. It is a signal.

Further, the bus indicated by reference numeral 406 is a 32-bit data bus for transmission of the forwarding engine unit FIFO 45, and the signal indicated by reference numeral 407 denotes a control signal for a data frame of the forwarding engine unit FIFO 45. And bus arbitration control signals, which are signal lines for data communication between the forwarding engine unit FIFO 45 and the MAC FIFO arbiter 47.

At this time, when the data frame being transmitted to the MAC FIFO 48 is being received by the forwarding engine unit FIFO 45, if a signal for requesting discarding is driven from the MAC controller, the MAC is also forwarded from the forwarding engine unit FIFO 45. The control signal for the same purpose is driven by the FIFO 48 to discard the data frame currently being received by the MAC FIFO 48. The signal line used here is referred to by reference numeral 408. FIG.

Further, a signal indicating that the MAC FIFO 48 is ready to receive data from the forwarding engine unit FIFO 45 is transmitted along a signal line indicated by reference numeral 409.

In addition, the MAC FIFO arbiter 47 is connected with signal lines indicated by reference numerals 410 and 411 for data connection with the processor processing unit FIFO 46, and the processor processing unit FIFO 46 is also the MAC FIFO 48. Signal to the processor processor FIFO 46 is ready to receive the data along the signal line indicated by reference numeral 409.

In addition, between the MAC FIFO arbiter 47 and the MAC FIFO 48, a signal line 412 which performs an arbitration role of data of the forwarding engine unit and data of the processor processing unit, and controls for arbitrating data of the forwarding engine unit and data of the processor processing unit. The signal line 413 is connected.

In this case, the MAC FIFO 48 and the output receiver connection 49 and the signal lines 414, 415, and 416 are connected, and the output connection signals are all synchronized to the 31.125MH clock.

5 shows a transmitter data flow diagram of the present invention, wherein the transmitter data flow consists of an input transmitter connection 51, a packet header separator 52, a MAC FIFO 53, and a physical layer transmitter connection 54. have.

A signal line denoted by reference numeral 501 is a bus (32 bits) for data transmission between the packet header separator 52 and the MAC FIFO 53, 502 is a control signal of input data, and 503 is a signal of the MAC FIFO 53. The control signal informs the input transmitter connection 51 of the current state.

And a physical layer Gigabit Media Independent Interface (GMII) transmission data bus (504), a physical layer Gigabit Media Independent Interface (GMII) control signal (505), and an Ethernet control signal between the MAC FIFO (53) and the physical layer transmitter connection (54). It is connected to a signal 506 that warns of the current link channel condition (collision, carrier detection, etc.).

As described above, when providing a Gigabit Ethernet structure having a dual-path three-layer forwarding engine according to the present invention, the existing separate MAC and forwarding engine device by implementing a gigabit MAC protocol and three-layer forwarding in the MAC The transmission takes place at a rate that eliminates the time delay factor and guarantees gigabit bandwidth.

In addition, the two-way path (fast path for forwarding and slow path for processing messages through the processor) is divided into efficient three-layer forwarding structure in which the fast path of the forwarding message does not interfere with the processing of gigabit speed by using an exception protocol. To have.

Claims (6)

In a gigabit ethernet system, A first path receiving MAC data streams received at a predetermined rate of 32 bits and classifying them into a high-speed path for packet classification, lookup control, and packet forwarding, and a low-speed path for receiving a data stream other than normal forwarding for packet processing and delivery by a processor. Process; A second process of forwarding normal forwarding through a fast path through packet classification and lookup information by an IP header; And Through the packet classification and lookup information by the IP header, the processor distributes the traffic of three-layer IP routing and forwarding messages, including a third process of processing exception protocols, ICMP, ARP, etc. through a slow path. Method of configuring a dual-path forwarding three-layer forwarding engine. A high speed path for receiving a MAC data stream received at a predetermined rate of 32 bits at a predetermined rate, for packet classification, lookup control, and packet forwarding; and a low speed path for packet processing and forwarding by a processor for receiving a data stream other than normal forwarding; A first process of processing 8-bit or 10-bit line coding (encoding / decoding) by connecting a predetermined bit electrical signal of a specific speed obtained by converting an optical signal of a specific frequency band of a link; A second step of generating and detecting a protocol data for controlling the medium by accessing 8-bit data of a specific speed processed through the first step; A third process of accessing 32-bit data having a predetermined rate generated through the second process and performing three-layer IP search and forwarding process; A fourth process of processing a message such as an exception protocol, an internet control message protocol, an address resolution protocol, or the like from the data processed through the third process; And And a fifth process of storing a protocol message by arbitration processing of a predetermined high speed path and a high speed path among predetermined data among data processed through the third process and the fourth process. Gigabit Ethernet configuration method having a dual-path forwarding three-layer forwarding engine. It is classified into high speed path that receives MAC data stream with 32 bits of 31.25MHz speed from MAC controller and receives low speed path for packet classification, lookup control and packet forwarding, and data stream which is not normal forwarding. ; A MAC FIFO for arbitrating, collecting data output from each path and outputting the data to the switch fabric; A packet classifier for searching an IP header in the data stream received from the MAC controller to check packet validity, determine a course, and send a destination IP address to a lookup controller to search a lookup table if it is determined to be a valid packet; The normal forwarding message and the local processing message are classified through real-time lookup. In the case of normal forwarding, packet forwarding is performed according to the lookup result, and the packet forwarder outputs the MAC to the MAC FIFO by attaching a header containing the output port information or packet information. ; The message processed by the packet classifier or the message classified as local processing in the lookup process is sent to the low speed path through the MAC FIFO to process the message by the processor. Forwarding engine structure. The method of claim 3, wherein The packet processing is a two-way forwarding engine structure, characterized in that for performing next hop address replacement, packet TTL reduction, checksum byte recalculation, and the like. Physical coding sublayer means for processing the proposed 8B10B line coding (encoding / decoding) by connecting a 125-bit 10-bit electrical signal converted from a 1.25Gbps optical signal of a link; A Gigabit Ethernet media controller for generating and detecting protocol data for media control by accessing 8-bit data of 125 MHz speed processed by the physical coding sublayer means; A high-speed three-layer IP forwarding engine means for accessing 32-bit data at 31.25 MHz of the Gigabit Ethernet media controller and performing three-layer IP search and forwarding processing; A low-speed processor processing means connected to said three-layer IP forwarding engine means to handle message processing such as exception protocols, Internet control message protocols, and address resolution protocols; And And a MAC FIFO control logic unit for accessing the three-layer IP forwarding engine means and the processor processing means, respectively, to store a protocol message by arbitration processing of a fast path priority. Gigabit Ethernet architecture. The method of claim 5, A clock and test connection supplied to the system; Gigabit Ethernet structure having a dual-path three-layer forwarding engine, characterized in that it further comprises a processor connection unit for providing a connection function with a built-in register and counter for network information management.