KR20010057285A - Synchronous DRAM With programmable self-refresh function - Google Patents

Abstract

PURPOSE: A synchronous DRAM capable of being programmable and self refresh is provided to program a self refresh period with desired one by using an address which is not used during mode register setting. CONSTITUTION: The device includes an address buffer(10), an address register(11), a row pre-decoder(13), a mode register(16), a self refresh logic(17), an internal row address counter(20), a bit line precharge control signal generator(21), a memory cell array(22) and a self refresh logic and timer. The self refresh logic and timer uses the signal from the address register which is not used during mode register setting to generate a programmed refresh request signal having plurality of refresh periods. The bit line precharge signal generator is not operated under control of the self refresh logic and timer during self refresh mode. The self refresh logic and timer further includes a decoder which decodes the signal from the address register and a plurality of frequency signal from a frequency divider.

Description

Synchronous DRAM With programmable self-refresh function

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to synchronous DRAMs (hereinafter referred to as SDRAMs), and more particularly, to SDRAMs having a programmable cell refresh function capable of programming a self-refresh cycle at a desired period without using a fuse.

Generally, in DRAM semiconductors, unit memory elements (hereinafter, referred to as cells) are arranged in two dimensions, and are divided into rows and columns, and given an address, and the addresses are referred to as row addresses and column addresses, respectively. . When using DRAM, read and write operations are performed by designating a desired cell by applying a low address followed by a column address.

The memory cells have a capacitor as a means for storing data, which requires a self refresh operation in order to continuously store the data. The period of self-refresh operation is determined by the data retention time which can guarantee the operation of the device even in the worst case. The smaller the current (ICC6) consumed in the self-refresh mode, the better. This ICC6 current decreases with longer self-refresh cycles.

1A is a circuit diagram of a cell refresh logic and a timer included in a conventional SDRAM. The conventional cell refresh logic and timer include a fuse unit F1 and F2 for programming a cycle of self refresh, a decoding unit DEC for decoding signals from the fuse unit F1 and F2, And a delay unit DR1 for delaying the output signal of the decoding unit DEC for a predetermined time.

The fuse part F1 includes a fuse f1 connected to a power supply voltage terminal, a decoupling capacitor C1 connected in parallel with the fuse f1, and an NMOS transistor N1 connected in parallel with the decoupling capacitor C1. And an inverter I1 connected in parallel with the fuse f1 and an inverter I2 connected with an output terminal of the inverter I1. Here, the output terminal of the inverter I1 is also connected to the NMOS transistor N1.

The fuse part F2 is configured in the same manner as the fuse part F1 as the fuse f2, the decoupling capacitor C2, the NMOS transistor N2, and the inverters I3 and I4.

The decoding unit DEC includes inverters I5 and I6, NAND gates ND1 to ND4, and NOR gates NR1 to NR5.

In addition, the conventional cell refresh logic and the timer sequentially sequence a NOR gate NR6 connected to an output terminal of the delay unit DR1 and the decoding unit DEC, and a cell refresh signal selfref which is an entry signal of the cell refresh mode. Inverters I7 and I8 which are inverted by the same, a delay unit DR2 which delays the output signal of the inverter I8, and an inverter I9 which sequentially inverts the output signal of the inverter I8, ( I10 and an oscillator OSC which generates a clock signal of a predetermined frequency in response to the output signal of the inverter I10.

In addition, the conventional cell refresh logic and the timer receive the output signals from the oscillator (OSC) and the delay unit (DR2) through the input terminal (flus), (oscen), a plurality of periods (1128μs), (116μs), A frequency divider FDEV for applying clock signals having 132 μs and 164 μs to the decoding unit DEC, and a NAND gate ND5 connected to the output terminals of the noble gate NR6 and the inverter I8; And an inverter I11 which inverts the output signal of the NAND gate ND5 to generate the cell refresh request signal srefreq.

In the conventional cell refresh logic and the timer configured as described above, the cycle of the cell refresh is programmed by cutting the fuses (fuse1) and (fuse2) provided in the fuses F1 and F2. That is, when the fuse fuse1 is connected, the decoupling capacitor C1 is charged by the power supply voltage, and the inverter I2 outputs a high level signal to the decoding unit DEC. At this time, the inverter I1 applies a low level signal to the gates of the inverter I2 and the NMOS transistor N1. On the other hand, when the fuse fuse1 is cut, the inverter I2 outputs a low level signal to the decoding unit DEC, and the inverter I1 outputs a high level signal. Therefore, the decoupling capacitor C1 is discharged through the NMOS transistor N1. And the fuse part F2 operates in the same way as the above-mentioned fuse part F1.

When the cell refresh signal selfref is at a high level, the oscillator OSC is operated by a signal applied through the inverters I7 to I10 to generate a clock signal of a predetermined period. The frequency divider FDEV receives a signal delayed for a predetermined time and a clock signal from the oscillator OSC through the delay unit DR2, and has a clock having a plurality of periods (1128 μs), (116 μs), (132 μs), and (164 μs). The signals are applied to the noar gates NR1 to NR4 of the decoding unit DEC, respectively. The output signal of the decoding unit DEC is logically computed by the delay unit DR1, the NOR gate NR6, the NAND gate ND5, and the inverter I11 to generate a cell refresh request signal srefreq. As a result, as shown in FIG. 1B, the cell refresh request signal srefreq having different periods 1128 μs, 116 μs, 132 μs, and 164 μs according to the states of the fuses fuse 1 and fuse 2 is different. Is made. As a result, a low address for cell refresh is generated in the SDRAM to perform the cell refresh mode.

2A is a circuit diagram of a bit line precharge control signal generation circuit included in a conventional SDRAM.

The conventional bit line precharge control signal generation circuit includes an inverter I12 that receives a signal sgd for driving a sense amplifier and a NAND gate that receives a signal bax9A for driving a specific block in a bank. (ND6), the NAND gate ND6 which receives the NAND gate ND6 and the output signal of the inverter I12, and the inverter I13 which sequentially inverts the output signal of the NAND gate ND7, ( I14).

In addition, the conventional bit line precharge control signal generation circuit receives an external voltage Vext and is connected to the output terminals of the inverters I13 and I14 through NMOS transistors N3 and N4 and cross-crosses each other. PMOS transistors P1 and P2 coupled in a cross-coupled manner and PMOS transistors P3 connected in series with each other by the node voltage between the PMOS transistor P2 and the NMOS transistor N4 and connected in series. ) And an NMOS transistor N5. Here, a bit line precharge control signal blp_d is generated at a node between the NMOS transistor N5 and the PMOS transistor P3 receiving the external voltage Vext, and the bit line precharge control signal blp_d is a bit. It is an auxiliary means to reduce the precharge time of the line and drives the NMOS transistors connected at both ends of the bit line.

The operation of the conventional bit line precharge control signal generation circuit configured as described above will be described with reference to the waveform diagram of FIG. 2B.

First, when the cell refresh mode is started, the cell refresh signal selfref is changed from the low level to the high level, and at this time, the low level signals sgd, bax9A, and wlcb are the inverter I12 and the NAND gate ND6. Is supplied. Therefore, the NAND gate ND7 receives the high level signals and outputs a low level signal, and the inverters I13 and I14 generate the high level and low level signals, respectively. At this time, since a low-level voltage is applied to the gate of the PMOS transistor P3, it is turned on, and the NMOS transistor N5 is turned off.

As a result, the bit line precharge control signal blp_d has a high level, and thus precharges the bit line to cell refresh the cells selected by the cell refresh request signal srefreq.

On the other hand, when the signals sgd, bax9A, and wlcb are changed from the low level to the high level, the bit line precharge control signal blp_d of the low level is generated through a process opposite to that described above. Therefore, NMOS transistors connected at both ends of the bit line are turned off.

However, in the conventional SDRAM as described above, since the cell refresh cycle is fixed according to the fuse option, the refresh operation is performed according to the fixed cycle even in a device having good refresh characteristics. In other words, the data retention time of the cell could be different for each device manufactured. Therefore, the fixed period could not be changed because many cycles were made and the period was fixed using the fuse option in the worst condition.

In addition, a circuit that does not need to operate in the cell refresh mode, for example, NMOS transistors driven by the bit line precharge control signal blp_d operates, thereby increasing the consumption of the ICC6 current.

Accordingly, the present invention has been made to solve such a problem, and provides an SDRAM having a programmable cell refresh function that can conveniently program a self-refresh cycle at a desired period by using an address not used when setting a mode register. The purpose is to provide.

It is another object of the present invention to provide an SDRAM having a programmable cell refresh function that can reduce the current consumed in the cell refresh mode by using a cell refresh period longer than a predetermined period.

It is still another object of the present invention to prevent the bit line precharge control signal generation circuit, which is an auxiliary means for reducing the precharge time of the bit line, from operating in the cell refresh mode, thereby reducing the current consumed in the cell refresh mode. It is to provide an SDRAM having a cell refresh function.

It is an additional object of the present invention to provide an SDRAM having a programmable cell refresh function that can change the cycle of cell refresh without using a fuse, thereby reducing the process of cutting the fuse with a laser during chip manufacturing.

1A is a circuit diagram of a self refresh logic and a timer included in a conventional synchronous DRAM.

FIG. 1B is a table showing frequencies of the self refresh request signal according to the state of the fuse of FIG. 1A. FIG.

2A is a circuit diagram of a circuit for generating a bit line control signal included in a conventional synchronous DRAM.

2B is a waveform diagram of signals input and output in the circuit of FIG. 2A;

Figure 3a is a block diagram showing the configuration of a synchronous DRAM to which the present invention is applied.

FIG. 3B is a block diagram illustrating signals input and output in some circuit diagrams of FIG. 3A; FIG.

4A is a detailed circuit diagram of the self refresh logic and timer of FIG. 3A.

FIG. 4B is a table showing frequencies of self refresh request signals according to levels of specific address signals in the circuit of FIG. 4A. FIG.

FIG. 5A is a detailed circuit diagram of the bit line precharge control signal generator of FIG. 3A. FIG.

5B is a waveform diagram of signals input and output in the circuit of FIG. 5A.

FIG. 6A is a partial circuit diagram of the memory cell array, sense amplifier, and input / output gate of FIG. 3A. FIG.

6B is a waveform diagram of signals input and output in the circuit of FIG. 6A.

* Description of the symbols for the main parts of the drawings *

10: Low address buffer 11: Address register

12: Command interpreter 13: Low-free decoder

14: column predecoder 15: column address counter

16: Mode register 17: Self-fresh logic and timer

18: Burst Counter 19: Data Output

20: Internal low address counter 21: Bit line presetter control signal generator

22: memory cell array 170: decoding section

selref: cell refresh signal srefreq: cell refresh request signal

In order to achieve the above object, the present invention includes an address buffer, an address register, a low predecoder, a mode register, a cell refresh logic and a timer, an internal low address counter, a bit line precharge control signal generator, and a memory cell array. In the synchronous DRAM, the cell refresh logic and the timer generate a refresh request signal having a plurality of refresh periods programmed using a signal from the address register that is not used in setting the data of the mode register. The line precharge control signal generator is not driven under the control of the cell refresh logic and the timer when the cell refresh mode is executed.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 3A, the SDRAM to which the present invention is applied includes an address buffer 10 for receiving and storing an address signal ADD and a bank address signal BA from the outside and generating an internal address, and the address buffer 10. And an address register 11 for generating a bank selection signal BANK-SEL, a low address and a column address, and a register signal in accordance with the internal address from (10).

In addition, the SDRAM to which the present invention is applied includes a signal, a low active signal ROW_ACT, and a signal for controlling the operation of the respective circuits by analyzing the bank selection signal BANK-SEL and command data from the address register 11. A command interpreter 12 for generating a column active signal COL_ACT, a low predecoder 13 for decoding the low address from the address register 11 in advance, and a column address from the address register 11 in advance. A column predecoder 14 for decoding and a column addresser 15 for counting column addresses from the address register 11.

In addition, the SDRAM to which the present invention is applied is programmed by a mode register 16 for storing mode data relating to a memory operation according to a signal from the address register 11 and a register signal from the address register 11. A cell refresh logic and timer (17) for generating a cell refresh request signal (srefreq) having a period, a burst counter (18) for counting burst data based on the mode data stored in the mode register (16), and A data output control unit 19 for generating a pipeline control signal PLC for data output under control of the burst counter 18, and a cell refresh request signal from the self-fresh logic and timer 17. Recognizing the refresh cycle according to srefreq, counting the internal low address, and applying the internal low address decoder to the low predecoder 13. And a 20 and a bit line precharge control signal generating section 21 for generating a bit line pre-charging control signal according to the control of the self-fresh logic and timer (17).

In addition, the SDRAM to which the present invention is applied includes a memory cell array 22 consisting of memory cells composed of a plurality of banks, and a word of the memory cell array 22 according to a decoding signal from the low predecoder 130. An X control unit and X decoder 22a for driving a line, a Y decoder 22b for selecting a bit line according to a count signal from the column addresser 15, and data from the memory cell array 22. Input / output through the data bus 25 according to a sense amplifier and input / output gate 23 for sensing, amplifying and controlling the input / output and the pipeline control signal PLC from the data output controller 19. An input / output data buffer 24 for temporarily storing data is included.

Referring to FIG. 3B, a 12-bit internal address signal ai0 to ai11 and its inverted signals abi0 to abi11 are applied to the address register 11 from the address buffer 10, and the mode register 16 is an address register. From 11, register signals mrg0 to mrg11 are applied. At this time, a two-bit register signal mrg10 to mrg11 for programming the period of the cell refresh request signal srefreq is input to the cell refresh logic and the timer 17. The mode register 16 includes signals bl1, bl2, bl4, and bl8 relating to the length of the burst data, a signal BT related to the burst form, and a column address strobe signal CAS. Signals relating to the delay time (cl1 to cl3) and signals (brd_swt) for controlling burst read and write of data stored in one cell of the memory cell array 22 are generated. Here, the mode data stored in the mode register 16 is composed of fields such as burst length, burst type (BT), CAS delay, function, command code, and self refresh period selection. It is programmed by the address signals A0 to A2, A3, A4 to A6, A7, A8 to A9, and A10 to A11, respectively.

As shown in FIG. 4A, the cell refresh logic and the timer 17 decode the register signals mrg0 to mrg11 from the address register 11 and the signal from the frequency divider 179. It is provided.

In addition, the cell fresh logic and the timer 17 are configured in the same manner as the conventional circuit shown in FIG. 1A. The gates 172, the inverters 173, 174, the delay unit 175, and the inverter 176 ), 177, an oscillator 178, a NAND gate 180, and an inverter 181 for generating the cell refresh request signal srefreq.

The decoding unit 170 and the frequency divider 179 are configured in the same manner as the decoding unit DEC and the frequency divider FDEV of FIG. 1A.

In addition, as illustrated in FIG. 5A, the bit line precharge control signal generator 21 receives the inverter 210 which receives the cell refresh signal selfref and a signal sgd for driving a sense amplifier. The NAND gate ND6 receiving the input inverter I12, the signals bax9A and wlcb for driving a specific block in the bank, the NAND gate ND6 and the inverter I12 And a NAND gate ND7 'that receives an output signal, and inverters I13 and I14 which sequentially invert the output signal of the NAND gate ND7'. The bit line precharge control signal blp_d is generated at the connection node between the PMOS transistor P3 and the NMOS transistor N5.

Referring to FIG. 6A, the bit line precharge control signal blp_d generated by the bit line precharge control signal generator 21 may bit the upper and lower portions of the subcell array to drive NMOS transistors connected to both ends of the bit line. The line precharge control signals blp_d up and blp_d down are applied. The bit line pre-jaggie signals blp up and blp down and the sense amplifier driving control signals sa_ctrl up and sa_ctrl down are applied to the sense amplifiers provided above and below the subcell array.

The operation of the SDRAM to which the present invention configured as described above is applied will now be described with reference to FIGS. 3A to 6B.

First, in order to program a refresh cycle of a memory cell, a fuse is conventionally used. However, in the present invention, register signals mrg10 to mrg11 which are not used when setting mode data of the mode register 11 are used. That is, as shown in FIGS. 4A and 4B, when the cell refresh signal selfref is at a high level, the oscillator 178 is operated by a signal applied through the inverters 173 to 174 and 176 to 177. To generate a clock signal of a predetermined period. The frequency divider 179 receives a signal delayed for a predetermined time and a clock signal from the oscillator 178 through the delay unit 175, and has a clock having a plurality of periods (1128 μs), (116 μs), (132 μs), and (164 μs). The signals are applied to the decoding unit 170, respectively. At this time, the register signals mrg10 to mrg11 are also applied to the decoding unit 170, so that the output signals of the decoding unit 170 are delayed unit 171, noar gate 172, NAND gate 180, and the inverter ( In operation 181, a cell refresh request signal srefreq having a period of 32 μs, 16 μs, 64 μs, and 128 μs is generated.

That is, when the register signals mrg10 to mrg11 are high level, the cell refresh request signal srefreq has a period of 32 μs, and when the register signals mrg10 to mrg11 are low level and high level, respectively, the cell refresh request signal ( srefreq has a period of 16 μs, when the register signals mrg10 to mrg11 are high level and low level, respectively, the cell refresh request signal srefreq has a period of 64 μs, and the register signals mrg10 to mrg11 are low level, respectively. In this case, the cell refresh request signal srefreq has a period of 128 μs.

As a result, the present invention uses the register signals mrg10 to mrg11 to program the period of the cell refresh request signal srefreq, so that a period longer than a predetermined cell refresh specification can be used, thereby consuming the current when performing the cell refresh mode. Can be reduced. In addition, in the present invention, since the fuse is not used, the process of cutting the fuse with a laser is reduced.

Meanwhile. Since the precharge time is relatively insignificant in the cell refresh mode, the present invention generates a bit line precharge control signal, which is an auxiliary means for reducing the precharge time of the bit line, in order to reduce the current consumption during the cell refresh mode. The unit 21 is made inoperable when the cell refresh mode is performed.

That is, referring to FIGS. 5A and 5B, a high level cell refresh signal selfref is input to the inverter 210, and at this time, the low level signals sgd, bax9A, and wlcb are the inverter I12. ) And the NAND gate ND6. Therefore, the NAND gate ND7 'outputs a high level signal, and the inverters I13 and I14 generate low and high level signals, respectively. At this time, since a high level voltage is applied to the gate of the PMOS transistor P3, it is turned off, and the NMOS transistor N5 is turned on.

As a result, the bit line precharge control signal blp_d has a low level, and the low-level bit line precharge control signal blp_d has NMOS transistors provided at both ends of the bit line as shown in FIG. 6A. The bit line is not precharged because it is turned off and applied.

On the other hand, even if the signals sgd, bax9A, and wlcb are changed from the low level to the high level, the low level signal is continuously applied from the inverter 210 to the NAND gate ND7 ', and thus the operation described above. The low level bit line precharge control signal blp_d is generated through the same operation. Therefore, the NMOS transistors connected at both ends of the bit line are turned off so that the bit line is not precharged.

As a result, since the low level signal is output from the bit line precharge control signal generator 21 in the cell refresh mode, the current consumption due to the precharge of the corresponding bit line can be reduced.

6A and 6B, the bit line precharge signal blp and the bit line precharge control signal blp_d become low level after the bit line is precharged or when the cell refresh mode is performed. In this case, the low decoding signal px becomes a high voltage Vpp level, where the low decoding signal px drives the word line by the least significant 2 bits of the decoding signal output from the low predecoder 13 of FIG. 3A. It is for. In addition, the remaining decoding signals subxb and the signal xdec01b other than the least significant two-bit decoding signals are at a low level. Here, the signal xdec01b is for controlling the time that is disabled after the corresponding word line is operated and turned off. Subsequently, a high level signal is supplied to the word line wl, and data of the power supply voltage Vdd level is loaded on the bit line bl / blb.

As described above, the present invention can conveniently program the self-refresh cycle to a desired period by using an address not used when setting the mode register.

In addition, since the present invention can use a longer cell refresh period than a cycle determined during chip manufacturing, it is possible to reduce the current consumed in the cell refresh mode, and as a supplementary means for reducing the precharge time of the bit line. It is possible to reduce the current consumed in the cell refresh mode by preventing the line precharge control signal generation circuit from operating in the cell refresh mode.

In addition, the present invention enables to change the cycle of the cell refresh without using the fuse to reduce the process of cutting the fuse with a laser in the chip manufacturing process.

Claims (4)

In a synchronous DRAM comprising an address buffer, an address register, a low predecoder, a mode register, a cell refresh logic and a timer, an internal low address counter, a bit line precharge control signal generator, and a memory cell array. The cell refresh logic and timer generate a refresh request signal having a plurality of refresh periods programmed using a signal from the address register that is not used in setting the data of the mode register, And the bit line precharge control signal generation unit is not driven under the control of the cell refresh logic and the timer when the cell refresh mode is performed. The method of claim 1, wherein the self-fresh logic and timer is And a decode for decoding a signal from the address register and a plurality of frequency signals supplied from a frequency divider. The method of claim 1, wherein the bit line precharge control signal generation unit A first inverter receiving a cell refresh signal; A second inverter receiving a signal for driving the sense amplifier; A NAND gate first NAND gate receiving a signal for driving a specific block in the bank; And And a second NAND gate receiving the first NAND gate and output signals of the first and second inverters. The method of claim 1, wherein the bit line precharge control signal generation unit A synchronous DRAM having a programmable cell refresh function, which outputs a low level signal when the cell refresh mode is performed.