KR20010057283A - Synchronous dram - Google Patents

Abstract

PURPOSE: A synchronous DRAM is provided to receive address input lines separately from each other instead of layering the address input line with rows and columns so as to enable a burst operation in a bank direction. CONSTITUTION: The synchronous DRAM includes a bank address buffer(12), a bank address generator(16), a bank decoder(18), a mode register(17) and a command interpreter/generator(22). The bank address buffer stores a bank address applied from outside. The bank address generator is coupled with the bank address buffer and generates an internal bank address. The bank decoder interprets the bank address from the bank address buffer and the bank address generator. The mode register is coupled with the row address buffer, a column address buffer, and the bank address buffer and stores the mode data related to the operation of the memory device. The command interpreter/generator interprets the data from the command buffer and the mode register and generates a signal to control the operation of above-mentioned circuits.

Description

Synchronous DRAM

The present invention relates to a synchronous DRAM (hereinafter referred to as SDRAM). In particular, the burst operation in the bank direction in addition to the row and column directions can be performed, and the direction of the buster operation can be freely changed. The present invention relates to an SDRAM having improved performance of a memory device.

Generally, in DRAM semiconductors, unit memory elements (hereinafter, referred to as cells) are arranged in two dimensions, and are divided into rows and columns, and given an address, and the addresses are referred to as row addresses and column addresses, respectively. . When using DRAM, read and write operations are performed by designating a desired cell by applying a low address followed by a column address.

In more detail, the low address is first applied to amplify the data of one row, that is, all cells connected to a word line, and stored therein until the column address is input. The process up to this point is generally called a row activation operation or row activation, and cells connected to one word line are called pages. Thereafter, when a column address is input, an operation command, for example, a read or write command, which is specified together with the column address is received, and the operation is performed in the cell selected by the column access.

Therefore, once a row is selected and activated, it takes a short time to read data from that row, that is, cells on the same page. It requires a relatively long time since an activation operation is required.

In order to overcome the shortcomings caused by the difference in operating time, fast page mode is used to read and write a lot of data in a short time by writing a series of data to be written in one row and changing only the column address repeatedly. A DRAM that performs a mode) operation has been developed.

On the other hand, SDRAM further develops the DRAM for fast page mode so that consecutive addresses are used internally without separately inputting them, and all input / output operations of the DRAM are synchronized with an external clock. In the case of the SDRAM, a continuous data of a predetermined number, i.e., burst length, can be read or written at each cycle of the external clock. This operation is called a burst operation. Therefore, if the external clock frequency is made faster and data can be read and written accordingly, the bandwidth of memory performance can be dramatically increased by the burst operation.

In addition to the burst operation of reading and writing successive data in the same page every clock, the DRAM operation is performed by dividing an array of DRAM cells into several large chunks, or banks, and operating each bank separately as a separate DRAM. The method of implementing the speed up is also being used. This approach is commonly referred to as bank interleaving operation. This method has the same effect as one more axis that can be read and written in bursts compared to a single bank SDRAM that performs a burst operation, and when configured with multi-bank DRAMs that divide the number of banks into multiple burst operations in two dimensions This is what happens. Therefore, the performance of the memory can be further increased.

The performance and integration of systems are increasing, and the demands of users are increasing the demand for faster and faster memory. In particular, application fields for image processing often require much higher bandwidths than DRAMs. In addition, as ASIC technology and SOC (System On a Chip) technology evolve, it is required to integrate DRAM with other systems, such as MML or embedded DRAM. Even in the case of DRAM, integrating DRAM and other systems on one substrate can provide advantages such as reducing the number of chips and operating the integrated device at low power. Among these advantages, the biggest advantage is that the limit on the number of pins for input / output between the memory and the logic circuit is reduced, thereby greatly increasing the bandwidth of the memory. As a result, it is possible to meet the system's performance improvement requirements.

However, the DRAM integrated with the logic circuit as described above is similar in structure and operation to the case where the DRAM is formed as a single component, and in many cases, only the number of input / output data lines is increased.

Conventional DRAMs may receive the row address and the column address sequentially, respectively, and in order to reduce the number of pins of the chip, the row address and the column address are sequentially received with one address input pin, and the order of operation is determined according to the operation order. Address multiplexing has been used internally by distinguishing between row addresses and column addresses.

Since the conventional DRAM as described above selects the desired memory cells by using the address multiplexing method, there is a limit in improving the operation speed and a lot of current consumption. In addition, in the conventional SDRAM which performs the multi-bank operation, a bank interleave method of supplying the address of the bank from the outside is used, and thus there is a limit in improving its operation speed.

Accordingly, the present invention has been made to solve such a problem, and instead of multiplexing the address input line into rows and columns, the present invention can simultaneously receive each input separately so that burst operation in the bank direction can be performed, thereby improving the performance of the SDRAM. The purpose is to provide a three-dimensional burst-type synchronous DRAM that can further increase the power consumption significantly.

1 is a block diagram showing the configuration of a synchronous DRAM according to the present invention.

FIG. 2 is a detailed illustration of the mode register of FIG. 1. FIG.

3 is a detailed configuration diagram of the memory cell array of FIG. 1.

4 is a burst direction selection table of a synchronous DRAM according to the present invention;

5A is a graph showing the performance by the address of a conventional synchronous DRAM.

Figure 5b is a graph showing the performance by the address of the synchronous DRAM according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: low address buffer 11: column address buffer

12: Bank address buffer 13: Command buffer

14: low / refresh address generator 15: column address generator

16: Bank address generator 17: Mode register

18: bank decoder 19: memory cell array

19a: Low Decoder and Driver 19b: Bitline Sense Amplifier

20: Data pass circuit 21: Data input / output buffer

22: Command interpretation and generator

In order to achieve the above object, the present invention provides a low address buffer for storing a low address, a column address buffer for storing a column address, a command buffer, a row / refresh address generator, a memory cell array, a low decoder and a driver, and a bit line sense amplifier. An SDRAM having a data path circuit and a data input / output buffer, comprising: a bank address buffer for storing a bank address applied from the outside; A bank address generator connected to the bank address buffer to generate an internal bank address; A bank decoder for analyzing bank addresses from the bank address buffer and a bank address generator; A mode register connected to the low address buffer, the column address buffer, and a bank address buffer, and storing mode data related to a memory operation; And a command interpreter / generator configured to interpret data from the command buffer and the mode register to generate a signal for controlling the operation of each of the circuits.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, the present invention has three characteristics as follows.

First, by simultaneously receiving the address of a row and a column, it is possible not to activate all the cells in the same row in a DRAM cell array, but to activate only a cell corresponding to a burst operation, that is, a predetermined burst length. . This can significantly reduce the load of the row activation circuit, which takes up a large portion of the DRAM read time, thereby reducing the row activation time and reducing the power required to drive large loads. This feature is called partial word line activation.

Second, unlike the conventional method of activating only one row corresponding to the input row address, the present invention simultaneously activates a certain number of rows starting from the row corresponding to the input row address. Once activated, the cell is capable of a high speed burst operation, so that a row burst operation that is not possible in the conventional method can be performed. This method is called multi word line activation.

By activating several rows at the same time, bursting in two directions, row and column, is possible, so that a region capable of high-speed operation is changed to a two-dimensional plane of rows and columns. In addition, in order to perform the row direction burst operation, the number of row direction burst operations must be specified in advance, and a method of storing the operation mode in a mode register that records and records the operation mode in advance can be used.

It is also necessary to automatically generate a row address internally for the row direction burst operation, which includes an internal row address generator for auto refresh and self refresh in the existing SDRAM. There are many cases. Therefore, if the existing internal row address generator has a register that temporarily stores an internal address for burst operation, the same function as the existing one and at the same time serves as an internal row address generator for row burst operation in the present invention. It becomes possible. This is because the cell data reproducing operation and the normal read and write operations are not performed in parallel in the DRAM. Therefore, the amount of additional circuitry is minimal.

Third, by activating multiple banks simultaneously in the burst-operable region, which is a two-dimensional plane with multiple rows activated, bursting in the bank direction in addition to the row and column directions is possible. . Therefore, a free burst operation in three directions, that is, a three-dimensional burst operation, can be implemented. In the conventional SDRAM, although several banks were simultaneously activated, the address of the banks had to be supplied separately from the outside. Thus, the operation of switching the banks is not called a burst operation but is called a bank interleave operation. On the other hand, in the present invention, in order to perform a true burst operation using a plurality of banks, by providing a bank address generator that can generate the address of the bank internally, by automatically increasing the address of the bank internally Enables burst operation in the bank direction.

As shown in FIG. 1, the SDRAM according to the present invention has a low address buffer 10, a column address buffer 11, a bank address buffer (10) for storing a low address, a column address, a bank address, and a command, respectively. 12) and a command buffer (13).

In addition, the SDRAM according to the present invention is connected to the low address buffer 10 to generate an internal low address and a refresh address to generate a low / refresh address generator 14 and a column address generator 15 to be connected to an internal column. A column address generator 15 for generating an address and a bank address generator 16 connected with the bank address buffer 12 to generate an internal bank address are provided. The memory cell array 19 is connected to a row decoder and driver 19a, which interprets the row address from the row / refresh address generator 14 and activates the corresponding word line at an address input from the outside. In addition, the bit line sensor amplifier 19b connected to the memory cell array 19 senses and amplifies data of the selected cell.

In addition, the SDRAM according to the present invention is connected to the low address buffer 10, the column address buffer 11 and the bank address buffer 12, the mode register 17 for storing the mode data relating to the memory operation, and the bank address The bank decoder 18 for analyzing the bank address from the buffer 12 and the bank address generator 16, and the data from the command buffer 13 and the mode register 17 are analyzed to control the operation of the respective circuits. And a command interpretation / generating device 22 for generating a signal for performing the same.

The data read from the memory cell array 19 through the bit line sensor amplifier 19b is output to the outside through the data path circuit and the data input / output buffer 21, and vice versa. It is stored in the cell array 19.

The mode register 17 stores mode data as shown in FIG. Figure 2 shows an example of a three-dimensional burst SDRAM of 64 Mega (256? 64? 256? 16 banks) with 16 banks, 256 rows, 64 columns, and 64 data inputs / outputs.

Mode data stored in the mode register 17 is row burst length (RBL: Row Burst Length), column burst length (CBL: Column Burst Length), bank burst length (BBL: Bank Burst Lenth), read delay time (RL: Read Latency) and Burst Type (BT) fields. Here, the low bust length RBL is a field consisting of three bits (RA0 to RA2) among the low addresses from the low address buffer 10, and the column bust length CBL is among the column addresses from the column address buffer 11. The field is composed of three bits CA0 to CA2, and the bank burst length BBL is a field composed of three bits BA0 to BA2 among the bank addresses from the bank address buffer 12. The read delay time RL is a field composed of the upper 3 bits CA3 to CA5 of the column address, and the burst type BT is a field composed of the upper 1 bit RA3 of the low address.

The read delay time RL is the same as the column access strobe latency (CL) of the existing SDRAM, and is information on how many clocks may be read after a read command is input through the command buffer 13. For example, if the read delay time RL is set to "001", one clock may be read. If the read delay time RL is set to "010," the desired data may be read after two clocks.

In addition, there are two modes of burst type BT, for example, sequential burst and interleaved burst. Here, the remaining unused bits (RES), (reserved) is a field that cannot be arbitrarily determined by the user.

FIG. 3 is a detailed configuration diagram of the memory cell array 19 shown in FIG. 1 and is divided into a plurality of banks. One of the banks is selected, and when one of the banks is enlarged, it is configured as shown in the figure just above the memory cell array 19. And a bank is divided into several small segments, each of which is determined by the extent to which it can be activated among the rows. In FIG. 3, it is assumed that the fourth fragment 191 is activated from the left of the enlarged bank. In this activated fragment 191, multiple rows with contiguous addresses are activated at the same time.

The fact that a certain row is activated means that the potential of the word line WL in the cell 192 as shown in the upper part of FIG. 3 is increased so that the cell transistor NM is turned on and thus the cell 192 and the bit line BL are turned on. ) Means connected. The data of the activated cell 192, that is, the charge charged in the capacitor C, is sensed and amplified by the bit line sense amplifier 19b of FIG. 1 connected to the bit line BL to read data. On the contrary, when data supplied from the outside is written into the cell 192, data writing is performed by the write driver connected to the bit line BL, that is, the low decoder and the driver 19a of FIG.

In the SDRAM according to the present invention configured as described above, a process in which a three-dimensional burst operation is performed will be described in detail with reference to the accompanying drawings.

First, it is assumed that the appropriate mode as shown in FIG. 2 is preset in the mode register 17. In this state in which the memory operation mode is set, the low address, the column address, and the read command are simultaneously applied to the low address buffer 10, the column address buffer 11, and the command buffer 13. The command interpreter / generator 22 interprets the read command input through the command buffer 13 and converts the read command into appropriate appropriate control signals and transmits them to each circuit. In addition, the low address buffer 10 and the column address buffer 11 store the input low address and the column address, respectively, and transfer them to the low / refresh address generator 14 and the column address generator 15, and also the low decoder. And a driver 19a and a column decoder (not shown).

Each address interpreter receiving the control signal and the address to be read by the read command activates an appropriate row according to the actual memory cell arrangement. The bank decoder 18 activates a bank corresponding to the bank address input from the outside, and sends the current bank address to the bank address generator 16. The bank address generator 16 sends the internal bank address back to the bank decoder 18 so as to activate all the banks to which a burst operation should be performed from the current bank address. Using this internal bank address, the bank decoder 18 activates all the banks to which the bank operation is to be performed.

The row / refresh address generator 14 and the row / refresh address generator 14, the column address generator 15, and the column decoder operate in the same manner as the bank address generator 16 and the bank decoder 18 described above, and thus burst. Activates all three-dimensional cells in which the operation should be performed. In this way, once the desired cells are activated, the read and write operations to the cells are all ready.

After all of the cells to be burst are activated, data of the cells selected by the column address are amplified and stored by the bit line sense amplifier 19b, and then the data path circuit 20 and the data input / output buffer 21 are stored. It is transmitted to outside through). Subsequently, data of the next column address generated internally is sequentially output. After the data corresponding to the column burst length predetermined in the mode register 17 is continuously output, the low address is increased by one. In the above-described manner, the data is continuously output to the last column of the corresponding row while increasing the column address again. After repeating this continuous operation and outputting the low-burst length data in one bank, it moves to the first column of the active row of the next bank and performs a burst output operation in that row.

This type of burst operation will be referred to as normal burst operation for convenience. In normal burst operation, the column address increases in synchronization with every clock signal, and the increase rate of the column address is obtained by dividing the frequency of the clock signal by the column burst length. The increase rate of the bank address is obtained by dividing the frequency of the clock signal by the low burst length and the column burst length.

In addition to the normal burst operation as described above, the present invention uses four other input signals to increase the burst speed in the row, column and bank directions. That is, the command buffer 13 receives a row direction indication signal RS, a column direction indication signal COS, a bank direction indication signal BS, and a burst direction indication signal BD as shown in FIG. 4 in addition to various commands. The row direction indication signal RS indicates the burst increase and decrease in the row direction for each clock signal, the column direction indication signal COS indicates the increase and decrease in the burst in the column direction, and the bank direction indication signal BS is the bank. The burst increases and decreases in the direction indicated. In addition, signals such as RS, (COS), (BS), and (BD) for burst operation and 14 burst operation signals in combination thereof are applied to the command interpretation / generation device 22 according to the user's selection. The command interpreter / generator 22 generates a control signal corresponding to the signals RS, COS, BS, BD, and a combination signal, and supplies them to each circuit. As a result, one of the 16 burst operations shown in FIG. 4 is selected and performed.

The most important effect of the present invention is to enable a burst operation which is a high speed read operation in a three-dimensional manner. That is, in the conventional SDRAM, the burst operation was possible in only one direction, but in the present invention, the burst operation can be freely changed and the burst speed in each direction is also adapted to the fastest operating frequency of the SDRAM. do. This advantage is possible only by design changes, regardless of DRAM process or production technology.

Figure 5a is a graph representing the performance by the address of the conventional PC100 SDRAM, Figure 5b is a graph representing the performance by the address of the SDRAM of the three-dimensional burst system according to the present invention. The arrow to the right of the graph represents the burst movement speed in the column direction, and the arrow rising upward represents the burst movement speed in the bank direction. In addition, the arrow going to the rear of the graph means the burst operation in the low direction. The unit of all directions used the frequency unit MHz.

The graphs of FIGS. 5A and 5B are examples of a conventional SDRAM, based on an SDRAM having a burst operation speed of 100 MHz in a column direction. In the case of Fig. 5A, the burst operation speed in the column direction is 100 MHz, but in the row direction, the time to close the active row (indicated by "tRP" in the specification of SDRAM), the time to activate another row (tRCD), and the read command At least six clocks are required for the time until the data is received (CL: CAS Latency). As a result, the speed in the low direction does not exceed 15MHz. In addition, although 100 MHz is indicated in the bank direction, the operating speed is actually slower than this. That is, in order to perform a read operation while skipping a bank in the existing SDRAM, the activation of each bank must be separately instructed, so that the burst operation speed in the actual bank direction becomes slow.

On the other hand, in the case of the 3D burst type SDRAM according to the present invention, as shown in FIG. 5B, the burst operation speed in the row, column, and bank directions is 100 MHz even if the same process and production technology as the conventional SDRAM is used. It is possible to operate uniformly. In addition, since the activation is automatically performed in the bank and the row direction, the actual operation performance is higher.

Another advantage of the present invention is that it gives a degree of freedom to the direction selection of the burst operation. That is, since the position of the cell to be read next can be arbitrarily selected at the time of performing the burst operation, it is possible not only to give the application which uses the burst operation much more freedom, but also to enable a new application.

The present invention also uses a partial row activation scheme, which not only reduces the power consumption of the SDRAM, but also reduces the delay time CL, which is the time required to export the first data after receiving a read command.

Claims (6)

Low address buffer to store low address, column address buffer to store column address, command buffer, low / refresh address generator, memory cell array, low decoder and driver, bit line sense amplifier, data pass circuit and data input / output buffer In the SDRAM having: A bank address buffer for storing a bank address applied from the outside; A bank address generator connected to the bank address buffer to generate an internal bank address; A bank decoder for analyzing bank addresses from the bank address buffer and a bank address generator; A mode register connected to the low address buffer, the column address buffer, and a bank address buffer, and storing mode data related to a memory operation; And And a command interpreter / generator configured to interpret data from the command buffer and the mode register to generate a signal for controlling the operation of the respective circuits. The method of claim 1, wherein the mode data stored in the mode register is A synchronous DRAM comprising fields related to low burst length, column burst length, bank burst length, read delay time and burst type. The method of claim 1, wherein the command buffer is And a row direction indication signal, a column direction indication signal, a bank direction indication signal, a burst direction indication signal, and a combination signal thereof according to a user's selection. The synchronous DRAM according to claim 1, wherein the rows corresponding to the low burst length set in the mode register are simultaneously activated by an internal low address among the rows of the memory cell array. The synchronous DRAM according to claim 1, wherein only cells corresponding to the column burst length set in the mode register among the cells connected to the selected one row of the memory cell array are activated by the internal column address. The synchronous DRAM of claim 1, wherein banks corresponding to a bank burst length set in the mode register are simultaneously activated by the internal bank address among the banks of the memory cell array.