KR20010055156A - Operation mode selecting circuit for use in microcontroller - Google Patents

Abstract

PURPOSE: An operating mode select circuit is provided to be capable of receiving a control signal via a single pin and selecting an operating mode corresponding to the control signal in order to accomplish miniaturization of a microcontroller integrated circuit. CONSTITUTION: An operating mode select circuit includes a buffer(10) for delaying a control signal(RESET) inputted via a reset terminal to produce a clock signal(CLK). The first D-flipflop(20) latches the power supply voltage(VDD) in response to the clock signal(CLK). The second D-flipflop(30) latches an output signal(Q) of the first D-flipflop(20) in response to the clock signal(CLK). The third D-flipflop(40) latches the output signal(Q) of the second D-flipflop(30) in response to the clock signal(CLK). A NAND gate(50) NANDs the output signal(Q) of the second D-flipflop(30) and an inverted output signal(QB) of the third D-flipflop(40). A clear signal generator(60) consists of a delay element(62) and an OR gate(64). The delay element(62) delays the control signal(RESET) for a given time. The OR gate(64) ORs a signal from the delay element(62) and the control signal(RESET).

Description

Operation mode selection circuit of a microcontroller {OPERATION MODE SELECTING CIRCUIT FOR USE IN MICROCONTROLLER}

The present invention relates to a microcontroller, and more particularly to a circuit for selecting an operation mode of the microcontroller in response to a signal controlled from the outside.

The microcontroller's operating modes can be broadly divided into run mode, test mode, and diagnostic mode.

The microcontroller performs a corresponding operation in response to control signals input from an external device, for example, a run mode control signal, a test mode control signal, and a diagnostic mode control signal. This microcontroller has separate pins for receiving the control signals.

Recently, semiconductor technology has been developed in order to achieve high integration and miniaturization. Reducing pin count is one of the most important factors in achieving miniaturization of semiconductor integrated circuits.

Accordingly, an object of the present invention is to provide a circuit which receives a control signal through one pin and selects an operation mode corresponding to the control signal in order to achieve miniaturization of the microcontroller integrated circuit.

1 is a circuit diagram showing the configuration of an operation mode selection circuit according to a preferred embodiment of the present invention;

2 is a timing diagram when the microcontroller enters a run mode;

3 is a timing diagram when the microcontroller enters a test mode; And

4 is a timing diagram when the microcontroller enters the diagnostic mode.

* Description of the symbols for the main parts of the drawings *

10: buffer 20, 30, 40: D-flip-flop

50: end gate 60: clear signal generation unit

62: delay unit 64: ora gate

According to a feature of the present invention for achieving the object of the present invention as described above, the operation mode selection circuit provided in the microcontroller includes: delay means for generating a clock signal obtained by delaying a mode selection signal input from the outside for a predetermined time; ; First latch means for latching a power supply voltage in response to the clock signal; Second latch means for latching an output signal of the first latch means in response to the clock signal; Third latching means for latching an output signal of said second latching means in response to said clock signal; A logic circuit for logic operation of the inverted signal of the signal output from the second latch means and the signal output from the third latch means; And clear signal generating means for generating a signal for clearing the signals latched in the first, second and third latch means in response to the mode selection signal. The signal output from the first latch means is a first mode selection signal, and the signal output from the logic circuit is a second mode selection signal. The signal output from the third latching means is a third mode selection signal.

In a preferred embodiment, the first to third latch means each consist of a D-flip flop.

In a preferred embodiment, the clear signal generating means comprises: a delay circuit for delaying the mode selection signal for a predetermined time and an OR gate for outputting the clear signal by calculating and calculating the mode selection signal and the signal delayed by the second delay means. It includes.

(Action)

By such an apparatus, miniaturization of the microcontroller can be achieved.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4. In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.

1 is a circuit diagram showing the configuration of an operation mode selection circuit according to a preferred embodiment of the present invention.

Referring to FIG. 1, the operation mode selection circuit configured in the microcontroller operates in response to a control signal RESET input through a reset terminal. Specifically, the operation mode selection circuit may include the buffer 10, the first to third D-flip flops 20, 30, and 40, the AND gate 50, and the clear signal generator 60. Include.

The buffer 10 delays a control signal RESET input through the reset terminal for a predetermined time and outputs the clock signal CLK. The clock signal CLK output from the buffer 10 is provided as a clock signal of the D-flip flops 20, 30, and 40.

The first D flip-flop 20 latches a power supply voltage VDD in response to the clock signal CLK. The signal Q output from the first D flip-flop 20 is provided as a run mode selection signal RESET_IN of the microcontroller. The microcontroller performs a RUN mode in response to the reset signal RESET_IN.

The second D flip-flop 30 latches the output signal Q of the first D flip-flop 20 in response to the clock signal CLK. The third D flip-flop 40 latches the output signal Q of the second D flip-flop 30 in response to the clock signal CLK.

The AND gate 50 receives and outputs the output signal Q of the second D flip-flop 30 and the inverted output signal QB of the third D flip-flop 40. The signal output from the AND gate 50 is provided as a test mode selection signal TEST of the microcontroller. The signal Q output from the third D flip-flop 40 is provided as a diagnostic mode selection signal DIAG of the microcontroller.

The clear signal generator 60 includes a delay unit 62 and an OR gate 64. The delay unit 62 delays and outputs a control signal RESET input through the reset terminal for a predetermined time. The OR gate 64 receives and computes a signal output from the delay unit 72 and the control signal RESET. The signal Clear output from the OR gate 64 is a signal for clearing the signals latched in the D-flip flops 20, 30, and 40.

Subsequently, an operation of the operation mode selection circuit shown in FIG. 1 will be described with reference to FIGS. 2 through 4.

2 is a timing diagram when the microcontroller enters the run mode, FIG. 3 is a timing diagram when the microcontroller enters the test mode, and FIG. 4 is a timing diagram when the microcontroller enters the diagnostic mode. .

First, referring to FIG. 2, the control signal RESET input through the reset terminal in order to select a run mode transitions from a low level (logical '0') to a high level (logical '1'). The control signal RESET is delayed by the buffer 10 by a predetermined time and then output as a clock signal CLK. When the clock signal CLK transitions from a low level to a high level, the first D-flip-flop 20 outputs the power supply voltage VDD as an output signal Q. Thus, the run mode selection signal RESET_IN is activated to a high level. At this time, the second and third D-flip flops 30 and 40 maintain the low level.

With continued reference to FIG. 3, the control signal RESET transitions from low level to high level and back to low level and then to high level to select a test mode. In response to the clock signal CLK output from the buffer 10, the first D-flip-flop 20 outputs the power supply voltage VDD as an output signal Q. Therefore, the run mode selection signal RESET_IN is activated from the low level to the high level. At this time, the clear signal generator 60 outputs a high level clear signal Clear so that the data latched to the D-flip flops 20, 30, and 40 are not cleared. Even when the control signal RESET transitions from the high level to the low level, since the signal output from the delay unit 62 is a high level, the signal Clear output from the OR gate 64 maintains a high level. However, the low level section of the control signal RESET should be shorter than the time delayed by the delay unit 62.

As the control signal RESET transitions from the low level to the high level again, the clock signal CLK transitions from the low level to the high level after a predetermined time delay. Accordingly, the first D-flip flop 20 outputs the power supply voltage VDD as an output signal Q, and the second D-flip flop 30 is connected to the first D-flip flop 20. Accept the output signal and output it. At this time, the signal Q output from the third D flip-flop 30 is still at a low level. Accordingly, the output signal of the AND gate 50 that performs an AND operation on the output signal Q of the second D flip-flop 30 and the inverted output signal QB of the third D flip-flop 40 is High level.

That is, the run mode selection signal RESET_IN is maintained at a high level, and the test mode selection signal TEST is activated from a low level to a high level. The diagnostic mode selection signal DIAG remains at a low level.

Finally, referring to FIG. 4, the control signal RESET sequentially transitions from low level-> high level-> low level-> high level-> low level-> high level to select a diagnostic mode. The clock signal CLK is equally delayed by the buffer 10 by a predetermined time delay than the control signal RESET. As described above, the clear signal generator 60 transitions from the low level to the high level only when the control signal RESET first transitions from the low level to the high level.

When the clock signal CLK first transitions from the low level to the high level, the first D-flip-flop 20 outputs the power supply voltage VDD as an output signal Q. Accordingly, the run mode selection signal RESET_IN is activated to a high level. At the time when the clock signal CLK transitions from the low level to the high level for the second time, the first D-flip-flop 20 outputs the power supply voltage VDD as an output signal Q and the second signal. The D-flip flop 30 receives and outputs an output signal of the first D-flip flop 20. At this time, since the signal Q output from the third D flip-flop 30 is still at a low level, the signal output from the AND gate 50 is at a high level. Therefore, the test mode selection signal TEST is activated to a high level. Subsequently, at the time when the clock signal CLK transitions from the low level to the high level for the third time, the first D-flip-flop 20 outputs the power supply voltage VDD as an output signal Q, The second D flip-flop 30 receives and outputs an output signal of the first D flip-flop 20, and the third D flip-flop 40 receives the second D flip-flop ( The output signal of 30) is received and output. Accordingly, the test mode selection signal TEST output from the AND gate 50 transitions from the high level to the low level, and the diagnostic mode selection signal DIAG is activated from the low level to the high level.

The microcontroller operates according to the states of the run mode selection signal RESET_IN, the test mode selection signal TEST, and the diagnostic mode selection signal DIAG after a predetermined time after the control signal RESET is applied from the outside. Enter the mode. This is shown in Table 1.

TABLE 1

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, it is possible to determine the operation mode of the microcontroller by the control signal input through one pin. Therefore, miniaturization of the microcontroller integrated circuit can be achieved.

Claims (3)

Delay means for generating a clock signal obtained by delaying a mode selection signal input from the outside for a predetermined time; First latch means for latching a power supply voltage in response to the clock signal; The signal output from the first latching means is a first mode selection signal; Second latch means for latching an output signal of the first latch means in response to the clock signal; Third latching means for latching an output signal of said second latching means in response to said clock signal; The signal output from the third latching means is a third mode selection signal; A logic circuit for logic operation of an inverted signal of the signal output from the second latch means and the signal output from the third latch means to output a second mode selection signal; And And clear signal generating means for generating a signal for clearing signals latched in said first, second and third latch means in response to said mode selection signal. The method of claim 1, And the first to third latching means are each configured as a D-flip-flop. The method of claim 1, The clear signal generating means, A delay circuit for delaying the mode selection signal by a predetermined time; And an OR gate for performing an OR operation on the mode selection signal and the signal delayed by the second delay means, and outputting the clear signal.