KR20010054730A - A Synchronization Circuit For Parallel Operation Of UPS - Google Patents

A Synchronization Circuit For Parallel Operation Of UPS Download PDF

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KR20010054730A
KR20010054730A KR1019990055677A KR19990055677A KR20010054730A KR 20010054730 A KR20010054730 A KR 20010054730A KR 1019990055677 A KR1019990055677 A KR 1019990055677A KR 19990055677 A KR19990055677 A KR 19990055677A KR 20010054730 A KR20010054730 A KR 20010054730A
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clock
nand gate
gate
input
nand
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KR1019990055677A
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Korean (ko)
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KR100673035B1 (en
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류승표
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김형벽ㅂ
현대중공업 주식회사
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stand-By Power Supply Arrangements (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE: A parallel operation synchronizing circuit of uninterruptible power equipment is provided to be capable of assuring stable system synchronization by assuring the flow of fine circulation current in a load terminal even in power failure or power recovery. CONSTITUTION: Signals(SYM_OK) of the circuit and signals(SYM_OKD) of another system are logically combined in NAND gates(201,202). An output of the NAND gate(201) is input to a NAND gate(204) through a NOT gate(203) to be logically combined with any clock(D60Hz) of another system, and is also input to a NAND gate(205) to be logically combined with itself clock signal(60Hz). Outputs of the NAND gates(204,205) are input to a NAND gate(208) through a NAND gate(206). A presence/absence signal(BM_OK) of commercial power is input to the NAND gate(208) through a NOT gate(207), and the signal(BM_OK) and a commercial power clock(BY_CLK) are input to a NAND gate(209). Outputs of the NAND gates(208,209) are output as a system synchronizing clock(SYNCLK) through a NAND gate(210).

Description

무정전 전원장치의 병렬운전 동기화 회로{A Synchronization Circuit For Parallel Operation Of UPS }A Synchronization Circuit For Parallel Operation Of UPS

본 발명은 교류전원(AC)을 직류전원(DC)으로 변환하여 배터리를 충전하고, 변환된 DC를 AC로 변환하여 공급하는 무정전 전원장치에 있어서, 신뢰성 확보나 전원공급 용량의 증대를 위하여 무정전 전원장치 시스템을 병렬로 운전할 때, 인버터 간의 출력전압이 동기가 이루어질 수 있도록 하기 위한 무정전 전원장치 병렬운전 동기화 회로에 관한 것이다.The present invention provides an uninterruptible power supply that converts AC power into DC power to charge a battery, and converts and converts the converted DC into AC, thereby providing reliability and increasing power supply capacity. An uninterruptible power supply parallel operation synchronization circuit for synchronizing output voltages between inverters when operating device systems in parallel is provided.

무정전 전원장치는 교류전원(AC)을 정류하여 직류전원(DC)으로 변환하고, 이 변환된 직류전원을 이용해서 배터리를 충전시켜 두었다가, 상용교류전원이 존재하지 않을 경우(정전) 배터리의 DC전원을 인버터 방식을 이용해서 AC전원으로 변환하여 시스템에 공급하는 장치이다.The uninterruptible power supply rectifies and converts the AC power to DC power, and the battery is charged using the converted DC power, and the DC power supply of the battery is not available when there is no AC power. Is a device that converts into AC power using an inverter method and supplies it to the system.

이와같은 무정전 전원장치는 시스템의 신뢰성 확보나, 용량의 증대를 위해서병렬운전하는 경우가 있다.Such an uninterruptible power supply may be operated in parallel in order to secure system reliability and increase capacity.

특히, 인버터부의 고장시에도 부하단에 전원을 공급하기 위해서 상용전원과 동기가 이루어지도록 하고 있으며, 병렬 운전시에도 이와 같다.In particular, in order to supply power to the load stage even in the event of a failure of the inverter unit is to be synchronized with the commercial power source, even in parallel operation.

그러나, 종래의 무정전 전원장치의 병렬운전 동기화 회로에 의하면, 정전시에는 상용전원이 존재하지 않으므로 정전시에 병렬운전의 동기화를 수행하기 위해서 부하단의 전류에 따른 주파수 변경만 수행하기 때문에, 정전시나 복전시 많은 주파수 변동으로 인한 순환전류 대량 발생과, 이에 의한 시스템 파괴의 문제점을 가지고 있다.However, according to the conventional parallel operation synchronization circuit of the uninterruptible power supply, since there is no commercial power supply during a power failure, only a frequency change is performed according to the current at the load stage in order to perform parallel operation synchronization during a power failure. There is a problem in generating a large amount of circulating current due to a large frequency variation during power recovery and system destruction by this.

도1은 이러한 종래의 무정전 전원장치 병렬운전에서의 동기화 회로 구성을 보이고 있다.Fig. 1 shows a configuration of a synchronization circuit in such a conventional uninterruptible power supply parallel operation.

상용전원 클럭(BY)과 인버터부 출력(INV)을 EXOR게이트(101)를 통해서 AND게이트(102)의 일측에 입력함과 함께, NOT게이트(103)를 통해서 AND게이트(104)의 일측에 입력하고, AND게이트(102)(103)의 다른 쪽 입력단에는 발진신호(OSC1)(OSC2)가 각각 입력되며, AND게이트(102)(103)의 출력은 각각 OR게이트(105)를 통해서 동기화 클럭(SYNCLK)으로 출력되도록 한 구성이다.The commercial power supply clock BY and the inverter unit output INV are input to one side of the AND gate 102 through the EXOR gate 101, and input to one side of the AND gate 104 through the NOT gate 103. The oscillation signals OSC1 and OSC2 are input to the other input terminal of the AND gates 102 and 103, respectively, and the outputs of the AND gates 102 and 103 are respectively synchronized through the OR gate 105. SYNCLK).

도1의 회로에 의하면, 상용전원이 존재할 경우에는 상용전원 클럭(BY)이 EXOR게이트(101)와 AND게이트(102) 및 OR게이트(105)를 통해서 동기화 클럭(SYNCLK)으로 출력되지만, 정전시에는 상용전원 클럭(BY)이 존재하지 않게 되고, 그러면 EXOR게이트(101)의 출력은 인버터부 출력(INV)에 의해서 AND게이트(102) 또는 NOT게이트(103)를 통해서 AND게이트(104)를 제어하게 되고,따라서 AND게이트(102)(103)는 발진신호(OSC1) 또는 발진신호(OSC2)를 OR게이트(105)를 통해서 동기화 클럭(SYNCLK)으로 출력하게 된다.According to the circuit of FIG. 1, when commercial power is present, the commercial power supply clock BY is output as the synchronization clock SYNCLK through the EXOR gate 101, the AND gate 102, and the OR gate 105. There is no commercial power supply clock BY, and the output of the EXOR gate 101 controls the AND gate 104 through the AND gate 102 or the NOT gate 103 by the inverter output INV. Accordingly, the AND gates 102 and 103 output the oscillation signal OSC1 or the oscillation signal OSC2 to the synchronization clock SYNCLK through the OR gate 105.

즉, 정전시에는 인버터부 자신의 클럭만으로 동작하게 되고, 동기화는 앞에서 설명한 바와같이 부하단의 전류에 의한 주파수 변경만 수행한다.That is, during power failure, only the clock of the inverter unit itself operates, and the synchronization only changes the frequency by the current of the load stage as described above.

이와같이 종래에는 정전시에 병렬운전의 동기화를 수행하기 위하여 부하단의 전류에 따른 주파수 변경만 수행하기 때문에, 정전시나 복전시 많은 주파수 변동으로 인하여 순환전류가 많이 발생되어 시스템 파괴의 원인이 되고 있다.As described above, in order to synchronize the parallel operation at the time of power failure, only the frequency change according to the current of the load stage is performed. Thus, a large number of circulating currents are generated due to a large frequency variation during power failure or recovery, causing system destruction.

본 발명은 무정전 전원장치의 병렬운전에 있어서, 상용전원이 존재하는 경우에는 상용전원을 추종하고, 정전시에는 동일한 임의의 클럭을 모든 시스템에 공급하여 정전이나 복전시에도 부하단에 미세한 순환전류가 흐르도록 함으로써, 종래의 문제점을 해결하고, 안정된 시스템 동기화가 이루어질 수 있도록 한 무정전 전원장치의 병렬운전 동기화 회로를 제공한다.In the parallel operation of an uninterruptible power supply, the present invention follows a commercial power supply when a commercial power source is present, and supplies the same arbitrary clock to all systems during a power failure, so that a minute circulating current is applied to the load stage even during a power failure or a power recovery. The present invention provides a parallel operation synchronization circuit for an uninterruptible power supply that solves the conventional problems and enables stable system synchronization.

도1은 종래의 무정전 전원장치 병렬운전 동기화 회로의 회로도1 is a circuit diagram of a conventional uninterruptible power supply parallel operation synchronization circuit

도2는 본 발명의 무정전 전원장치 병렬운전 동기화 회로의 회로도2 is a circuit diagram of an uninterruptible power supply parallel operation synchronization circuit of the present invention.

도2는 본 발명의 무정전 전원장치의 병렬운전 동기화 회로의 구성을 나타낸 도면이다.2 is a diagram showing the configuration of a parallel operation synchronization circuit of the uninterruptible power supply of the present invention.

정전시에도 동기화가 이루어지도록 하기 위한 신호로서 자기신호(SYM_OK)와 다른 시스템의 신호(SYM_OKD)는 NAND 게이트(201)(202)에서 논리조합되고, NAND게이트(201)의 출력이 NOT게이트(203)를 통해 NAND게이트(204)에 입력되어 다른 시스템의 임의 클럭(D60Hz)과 논리조합되고, 또한 NAND게이트(201)의 출력은 NAND게이트(205)에 입력되어 자기 자신의 클럭신호(60Hz)와 논리조합되고, NAND게이트(204) 및 NAND게이트(205)의 출력은 NAND게이트(206)를 통해서 NAND게이트(208)의 일측에 입력되고, NAND게이트(208)의 타측에는 NOT게이트(207)를 통해서 상용전원의 존재유무 신호(BM_OK)가 입력되며, NAND게이트(209)의 일측에는 상기 상용전원의 존재유무 신호(BM_OK)와 상용전원 클럭(BY_CLK)이 입력되고, NAND게이트(208)(209)의 출력은 NAND게이트(210)를 통해서 시스템 동기화 클럭(SYNCLK)으로 출력되는 논리회로 구성을 이루고 있다.As a signal for synchronization even in the case of a power failure, the magnetic signal SYM_OK and the signal SYM_OKD of another system are logically combined at the NAND gates 201 and 202, and the output of the NAND gate 201 is a NOT gate 203. The NAND gate 204 is input to the NAND gate 204 to be logically combined with an arbitrary clock (D60Hz) of another system, and the output of the NAND gate 201 is input to the NAND gate 205 so that its own clock signal (60 Hz) Logically combined, the outputs of the NAND gate 204 and the NAND gate 205 are input to one side of the NAND gate 208 through the NAND gate 206, the NOT gate 207 to the other side of the NAND gate 208 The presence or absence signal of commercial power (BM_OK) is input through the NAND gate 209, and the presence or absence signal of commercial power (BM_OK) and the commercial power clock (BY_CLK) are input to one side of the NAND gate 209. ) Is output to the system synchronization clock (SYNCLK) through the NAND gate 210. It forms the circuit configuration.

도2에서 살펴보면, NAND게이트(201)(202)는 먼저 동작한 시스템의 임의 클럭을 기준클럭으로 하기 위한 제어수단이며, NOT게이트(203) 및 NAND게이트(204) (205)는 상기 제어수단의 제어를 받아서 다른 시스템의 임의 클럭(D60Hz)이나 자기 시스템의 임의 클럭(60Hz)을 기준클럭으로 출력하기 위한 게이트수단이며, NAND게이트(206)와 NOT게이트(207) 및 NAND게이트(208)(209)는 상용전원의 존재유무(정전 여부)(BM_OK)에 따라서 상기 게이트 수단의 임의 클럭 또는 상용전원 클럭(BY_CLK)을 선택하기 위한 스위칭수단이며, NAND게이트(210)는 상기 스위칭수단에 의해서 선택된 클럭을 동기화 클럭(SYNCLK)으로 출력하기 위한 출력수단을 이루고 있다.Referring to Figure 2, NAND gates 201 and 202 are control means for setting a reference clock to an arbitrary clock of a system which has been operated first, and NOT gate 203 and NAND gate 204 and 205 are the control means. It is a gate means for outputting the arbitrary clock (D60Hz) of another system or the arbitrary clock (60Hz) of its own system under control, and the NAND gate 206, NOT gate 207, and NAND gate 208 (209) ) Is a switching means for selecting the arbitrary clock of the gate means or the commercial power supply clock BY_CLK according to the presence or absence of the commercial power (non-outage) BM_OK, and the NAND gate 210 is a clock selected by the switching means. Output means for outputting the signal to the synchronization clock SYNCLK.

이와같이 구성된 본 발명의 병렬운전 동기화 회로 동작을 설명하면 다음과 같다.Referring to the parallel operation synchronization circuit operation of the present invention configured as described above is as follows.

상용전원이 존재하는 경우에는 상용전원 존재유무 신호(BM_OK)가 하이(High)이고, 상용전원이 존재하지 않는 경우에는 로우(Low)이다.When the commercial power is present, the commercial power existence signal BM_OK is high, and when the commercial power is not present, it is low.

그리고, 자기 자신의 신호(SYM_OK)와 다른 시스템(자기 시스템과 함께 병렬운전이 이루어지는 다른 시스템)의 신호(SYM_OKD)가 NAND게이트(201)(202)에서 논리조합되는데, 두 시스템 중에서 먼저 동작된 신호의 임의 클럭이 기준 클럭이 되도록 한다.In addition, a signal SYM_OKD of its own signal SYM_OK and another system (another system in which parallel operation is performed together with its own system) is logically combined in the NAND gates 201 and 202, which are operated first of the two systems. Let arbitrary clock be the reference clock.

즉, 자기 시스템이 먼저 동작하여 SYM_OK신호가 입력되면 NAND게이트(201)의 출력에 의해서 NAND게이트(205)가 게이트 온 상태로 제어되고, NOT게이트(203)를 통해 논리반전된 신호에 의해서 NAND게이트(204)는 게이트 오프 상태로 제어된다.That is, when the SYM_OK signal is inputted by the magnetic system first, the NAND gate 205 is controlled to the gate-on state by the output of the NAND gate 201, and the NAND gate is controlled by the signal inverted logically through the NOT gate 203. 204 is controlled to a gated off state.

따라서, 이 경우에는 NAND게이트(205)에 입력되는 자기 자신의 임의 클럭(60Hz)이 기준 클럭으로 NAND게이트(205)를 통해 NAND게이트(206)에 입력된다.In this case, therefore, an arbitrary clock (60 Hz) of its own input to the NAND gate 205 is input to the NAND gate 206 through the NAND gate 205 as a reference clock.

그러나, 다른 시스템이 먼저 동작하여 SYM_OKD신호가 입력되면 NAND게이트(202)(201)의 출력에 의해서 NAND게이트(205)가 게이트 오프상태로 제어되고, NOT게이트(203)를 통해서 NAND게이트(204)가 게이트 온 상태로 제어된다.However, when another system operates first and the SYM_OKD signal is input, the NAND gate 205 is controlled to be gated off by the output of the NAND gates 202 and 201, and the NAND gate 204 is provided through the NOT gate 203. Is controlled to the gate-on state.

따라서, 이 경우에는 NAND게이트(204)에 입력되는 다른 시스템의 임의 클럭(D60Hz)이 기준 클럭으로 NAND게이트(204)를 통해 NAND게이트(206)에 입력된다.Therefore, in this case, an arbitrary clock (D60Hz) of another system input to the NAND gate 204 is input to the NAND gate 206 through the NAND gate 204 as a reference clock.

한편, 상용전원이 존재하는 경우에는 BM_OK신호가 하이(High)이므로 NOT게이트(207)를 통해서 논리 반전된 로우(Low)신호가 NAND게이트(208)의 일측에 가해져서 NAND게이트(208)는 게이트 오프 상태가 되므로 자기 시스템이든, 다른 시스템이든 NAND게이트(206)의 출력(임의 클럭)은 차단되고, 상용전원 클럭(BY_CLK)이 NAND게이트(209)를 통해서 NAND게이트(210)에 가해져서 시스템 동기화 클럭(SYNCLK)으로 출력되게 된다.On the other hand, when there is a commercial power source, since the BM_OK signal is high, a low signal logically inverted through the NOT gate 207 is applied to one side of the NAND gate 208 so that the NAND gate 208 is gated. Since the system is turned off, the output (random clock) of the NAND gate 206 is cut off, and the commercial power supply clock BY_CLK is applied to the NAND gate 210 through the NAND gate 209 to synchronize the system. The clock signal SYNCLK is output.

그러나, 정전이 되면 BM_OK신호가 로우(Low)이므로 NAND게이트(209)는 게이트 오프 상태가 되고, NOT게이트(207)를 통해서 논리반전된 하이(High)신호가 NAND게이트(208)에 입력되어 NAND게이트(208)는 게이트 온 상태로 제어된다.However, when the power failure occurs, the BM_OK signal is low, so the NAND gate 209 is gated off, and the high signal logically inverted through the NOT gate 207 is input to the NAND gate 208 so that the NAND gate 208 is NAND. Gate 208 is controlled to a gate on state.

그러므로, 이 경우(정전시)에는 NAND게이트(206)를 통해서 입력되는, 앞에서 설명한 자기 시스템의 임의 클럭(60Hz)이나 다른 시스템의 임의 클럭(D60Hz)이 NAND게이트(208)(210)를 통해 동기화 클럭(SYNCLK)으로 출력된다.Therefore, in this case (at power failure), the arbitrary clock (60 Hz) of the magnetic system described above or the random clock (D60 Hz) of another system, which is input through the NAND gate 206, is synchronized through the NAND gate 208 (210). It is output by the clock SYNCLK.

즉, 만약 정전이 되고 기준 클럭이 D60Hz로 되면 동기화 클럭(SYNCLK)의 출력은 D60Hz가 되고, 다른 시스템의 동기화 클럭(SYNCLK)의 출력은 60Hz가 됨으로써, 두 시스템간에 동기화가 이루어지게 되는 것이다.That is, if a power failure occurs and the reference clock becomes D60 Hz, the output of the synchronization clock SYNCLK becomes D60 Hz, and the output of the synchronization clock SYNCLK of another system becomes 60 Hz, thereby synchronizing between the two systems.

본 발명은 무정전 전원장치의 병렬운전에 있어서, 상용전원이 존재하는 경우에는 상용전원을 추종하고, 정전시에는 동일한 임의의 클럭을 모든 시스템에 공급하여 정전이나 복전시에도 부하단에 미세한 순환전류가 흐르도록 함으로써, 종래의 문제점을 해결하고, 안정된 시스템 동기화가 이루어질 수 있도록 하였다.In the parallel operation of an uninterruptible power supply, the present invention follows a commercial power supply when a commercial power source is present, and supplies the same arbitrary clock to all systems during a power failure, so that a minute circulating current is applied to the load stage even during a power failure or a power recovery. By flowing, the conventional problem is solved and stable system synchronization can be achieved.

Claims (1)

먼저 동작한 시스템의 임의 클럭(D60Hz 또는 60Hz)을 기준클럭으로 하기 위한 제어수단과, 상기 제어수단의 제어를 받아서 다른 시스템의 임의 클럭(D60Hz)이나 자기 시스템의 임의 클럭(60Hz)을 기준클럭으로 출력하기 위한 게이트수단과, 상용전원의 존재유무(정전 여부)(BM_OK)에 따라서 상기 게이트 수단의 임의 클럭 또는 상용전원 클럭(BY_CLK)을 선택하기 위한 스위칭수단과, 상기 스위칭수단에 의해서 선택된 클럭을 동기화 클럭(SYNCLK)으로 출력하기 위한 출력수단으로 이루어진 것을 특징으로 하는 무정전 전원장치의 병렬운전 동기화 회로.Control means for making a reference clock (D60Hz or 60Hz) of the first operating system as a reference clock, and an arbitrary clock (D60Hz) of another system or any clock (60Hz) of another system under the control of the control means as a reference clock. A gate means for outputting, switching means for selecting an arbitrary clock or commercial power supply clock BY_CLK of the gate means in accordance with the presence or absence of a commercial power source (outage) (BM_OK), and a clock selected by the switching means. Parallel operation synchronization circuit of the uninterruptible power supply, characterized in that the output means for outputting the synchronization clock (SYNCLK).
KR1019990055677A 1999-12-08 1999-12-08 A Synchronization Circuit For Parallel Operation Of UPS KR100673035B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030080614A (en) * 2002-04-09 2003-10-17 정정웅 Parallel operation controller of on-line UPS system

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KR102303516B1 (en) 2021-04-30 2021-09-16 이길호 Method and apparatus for synchronizing phase of uninterruptible power supply with parallel structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030080614A (en) * 2002-04-09 2003-10-17 정정웅 Parallel operation controller of on-line UPS system

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