KR20010054166A - Memory device - Google Patents

Abstract

PURPOSE: A memory device is provided to reduce a test time sharply by performing the judgement of PASS/FAIL in a write access. CONSTITUTION: The memory device comprises a memory cell array(21), an address decoder(22), a write path buffer(23), a read path buffer(24), an n-bit register(25), a comparison part(26) and an 1 bit flag register(27). The n bit register stores test data temporarily, and the comparison part compares an output data of the n bit register with data from the memory cell array. The 1 bit flag register outputs a flag signal according to the comparison result of the comparison part. In detail describing the circuit operation, the input and the output of the memory cell array are separated and are connected to an input node of the read path buffer and to an output node of the write path buffer respectively. That is, during a write access, the memory cell array performs a write operation, and data written to the memory cell array is latched to the n bit register. Then, data from the n bit register is compared with data from the memory cell array. If the compared data are not equal, the memory is judged as a defective one, and the 1 bit flag register outputs an error flag bit.

Description

Memory device {MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device, and more particularly, to a memory device capable of determining a positive or negative value of a memory cell only by write access during a memory test such as SRAM.

Hereinafter, a memory device according to the related art will be described with reference to the accompanying drawings.

1 illustrates a structure of a conventional memory device.

As shown in FIG. 1, the memory cell array 11 includes an address decoder 12, a write pass buffer 13, and a read pass buffer 14.

The input address A is decoded by the address decoder 12 to specify the address of the memory.

At this time, in the write mode, the write pass buffer 13 is activated and the input data is written to the address designated through the write pass buffer 13.

In the read mode, the read pass buffer 14 is activated and data stored at the designated address is read through the read pass buffer 14.

At this time, the ride pass buffer 13 and the read pass buffer 14 are not activated at the same time.

In such a conventional memory, the written data and the read data must be compared with each other in order to determine the quantity / negativeness of the memory.

That is, the data written to the memory in the write mode is compared with the data read in the read mode, and is determined to be defective if they are not the same.

However, such a conventional memory device has the following problems.

The test data is written to the memory in a write cycle to determine whether the memory is positive or negative, and then the test data stored in the memory is read in the read cycle to compare the two data. The test takes a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a memory device that can drastically reduce test time.

1 is a structure of a memory device according to the prior art

2 is a structure of a memory device according to the present invention

Explanation of symbols for main parts of the drawings

21: memory cell array 22: address decoder

23: write pass buffer 24: read pass buffer

25: n bit register 26: comparison unit

27: 1 bit flag register

According to an aspect of the present invention, a memory device includes a memory cell array, an address decoder for decoding an input address to designate an address of the memory cell array, and an input terminal of the memory cell array to be active during write access. A write pass buffer, a read pass buffer connected to an output terminal of the memory cell array and active during read access, an n-bit register for temporarily storing data written to the memory cell array during the write access, and the n-bit register And a flag register for generating a flag signal according to the comparison result.

Hereinafter, a memory device according to the present invention will be described with reference to the accompanying drawings.

2 illustrates a structure of a memory device according to the present invention.

As shown in FIG. 2, the memory cell array 21, the address decoder 22, the write pass buffer 23, the read pass buffer 24, the n bit register 25, the comparator 26, and 1 bit It consists of a flag register 27.

The n-bit register 25 temporarily stores the test data, and the comparator 26 compares the output data of the n-bit register 25 with the data output from the memory cell array 21.

The 1-bit flag register 27 outputs a flag signal according to the comparison result of the comparison section 26.

The operation of the memory device of the present invention will be described as follows.

First, when the test data is written to the memory cell array 21 each time by using the 1-bit flag register, the value written out and the value output from the memory cell array 21 are not compared to each other. Outputs an error flag and determines whether it is negative or negative.

For reference, in the related art, after performing the read access and the write access once, the value of the read / read is compared by comparing the read value with the read value.

According to the present invention, the input and output of the memory cell array 21 are separated and connected to the output node of the write pass buffer 23 to the input node of the read pass buffer.

That is, during the write access, the write operation proceeds to the memory cell array 21, and the data written to the memory cell array 21 is latched to the n-bit register 25.

Thereafter, the data output from the n-bit register 25 is compared with the data output from the memory cell array 21 by the comparator 26.

If the data of the comparison do not coincide with each other, the memory is determined to be bad and the 1-bit flag register 27 outputs an error flag bit.

According to the above, it can be seen that the memory quantity / determination can be determined only by the write access without performing the read access.

In other words, the amount / negative determination of the memory is not made after the read access but upon the write access.

As described above, the memory device of the present invention has the effect of significantly reducing the time required for the test because the determination of the quantity / negative is made during the write access.

Claims (2)

A memory cell array, An address decoder for decoding an input address and specifying an address of the memory cell array; A write pass buffer connected to an input of the memory cell array and activated during write access; A read pass buffer connected to an output terminal of the memory cell array and active during read access; An n-bit register for temporarily storing data written to the memory cell array during the write access; A comparator for comparing the output of the n-bit register with the output of the memory cell array; And a flag register for generating a flag signal according to the comparison result. The memory device of claim 1, wherein the flag register outputs an error bit when an output of the n-bit register does not coincide with an output of the memory cell array.