KR20010053687A - Rimm system with phase locked loof - Google Patents

Abstract

PURPOSE: A RIMM(Rambus Inline Memory Module) apparatus embedded with a PLL(Phase Locked Loop) is provided to increase a memory recognition capacity by reinforcing a clock signal attenuation using the PLL. CONSTITUTION: The RIMM apparatus comprises a plurality of Rambus DRAM(RDRAM1-RDRAMN:D1-DN), and a phase locked loop(35) is located between random Rambus DRAMs. The PLL is located between a clock(RCTM/N,LCTM/N) to master from a clock generator and a clock(LCFM/N,RCFM/N) from master to the clock generator. And, a left paddle(36) and a right paddle(37) output data and a clock signal and a control signal to the plurality of Rambus DRAM. And there are data signals(LDQA,LDQB, RDQA,RDQB) and row bus(LROW,RROW) signals and column bus(LCOL,RCOL) signals and clock signals(clock to master, clock from master) and a series of clock input signals(LSCK,RSCK) and a series of commands(LCMD,RCMD) applied from a control register and a logic reference threshold voltage(Vref) and a series of input signals(Sin) inputted from the first Rambus DRAM(D1) to the Nth Rambus DRAM(DN) and an output signal(Sout) from the Nth Rambus DRAM between two paddles.

Description

Rim system with phase-locked loop {RIMM SYSTEM WITH PHASE LOCKED LOOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rim memory, and more particularly to a rim (Rambus Inline Memory Module (RIMM)) device incorporating a phase locked loop (PLL).

Referring to the accompanying drawings, a conventional rim (RIMM) device will be described.

1 is a block diagram of a motherboard having a conventional rim (RIMM) device, Figure 2 is a block diagram of a conventional rim (RIMM).

And (a) of Figure 3 is a waveform diagram showing the signal attenuation through the rim of the configuration as shown in Figure 2, Figure 3 (b) is a chart showing the signal attenuation ratio according to the capacity of the conventional rim (RIMM).

As shown in FIG. 2, a conventional RIM device includes a plurality of Rambus DRAMs RDRAM1 to RDRAMN D1 to DN, and two paddles for outputting data, clock signals, or control signals to a plurality of Rambus DRAMs. (Left Paddle 10, Right Paddle 11), and in these two paddles, data signals LDQA, LDQB and RDQA, RDQB, and Low Bus LROW, RROW signal, column bus (LCOL, RCOL) signal, clock signal (Clock to Master, Clock from Master), a series of clock input signals (LSCK, RSCK), and a series of instructions (LCMD) applied from the control register RCMD, a logic reference threshold voltage Vref, a series of input signals Sin input from the first Rambus DRAM D1 to the Nth Rambus DRAM DN, and the Nth Rambus DRAM DN. There is an output signal Sout output.

As shown in FIG. 1, a motherboard for driving a conventional rim device having the above configuration includes a rim 2 composed of a plurality of Rambus DRAMs (RDRAMs) and each Rambus DRAM (RDRAM) in the rim 2. After setting the position of the unit (rambus DRAM) through the clock generator 3 for inputting the clock signal to the clock signal and the clock signal generated by the clock generator 3 at the time of reading or writing the data, control is performed. A master 1 for reading or reading data to a corresponding unit by sending a command, a signal reflection preventing unit 4 for preventing reflection of a signal classified in the rim 2, and applying a reference voltage Vref It is configured to include.

The signal reflection prevention unit 4 separates the signal input from the master 1 to the rim 2 into three types of data signals, control signals and clock signals on the rim 2, and then reflects the classified signals. It is to prevent the role.

Next, the magnitude of the clock signal Vin first inputted to the rim 2 and the attenuated magnitude Va of the clock signal inputted first are shown in FIG. 3A. While the clock signal is output without being attenuated in the magnitude of the signal, the magnitude of the clock signal decreases by 'Va' as compared with the magnitude of the input clock signal over time.

The ratio of Vin and Va is referred to as attenuation ratio Vin / Va of the clock signal.

As shown in (b) of FIG. 3, the attenuation ratio Va / Vin of the clock signal according to the capacity of the rim RIM is four rims 2 and eight 16 devices (rambus DRAM). When the attenuation ratio of the clock signal according to each capacity is expressed as a percentage (%), respectively, it is 12%, 16%, and 25%, respectively, and as the capacity of the rim increases, the rate of attenuation of the clock signal increases.

The conventional rim device as described above has the following problems.

First, the clock signal input to the Rambus DRAM in the rim is attenuated over time, making it difficult to read / write data accurately.

Second, as the capacity of the rim increases, the ratio of the clock signal attenuation becomes larger, so there is a limit to the number of Rambus DRAMs to read / write in the rim.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In particular, a rim having a phase locked loop capable of increasing memory recognition capacity by reinforcing clock signal attenuation using a phase locked loop (PLL) can be used. (RIMM) The purpose is to provide a device.

1 is a block diagram of a motherboard having a conventional rim (RIMM) device

2 is a block diagram of a conventional rim (RIMM)

Figure 3 (a) is a waveform diagram showing the signal attenuation through the rim of the configuration as shown in FIG.

Figure 3 (b) is a diagram showing the signal attenuation according to the capacity of the conventional rim (RIMM)

Figure 4 is a block diagram of a motherboard having a rim (RIMM) device with a phase synchronization loop according to an embodiment of the present invention

5 is a configuration diagram of a rim (RIMM) device incorporating the present invention phase synchronization loop

6 is a detailed configuration diagram of portion 'A' of FIG.

Explanation of symbols for the main parts of the drawings

31: Master 32: Rim

33: clock generator 34: signal reflection prevention part

35 phase locked loop 36 left paddle

37: right paddle 38a-38d: first to fourth buffers

39: comparison output

In order to achieve the above object, a rim device having a phase-locked loop according to the present invention reinforces attenuation of a plurality of Rambus DRAMs connected in series and clock signals applied to the plurality of Rambus DRAMs over time. And a phase-locked loop configured between the arbitrary rambus DRAMs to deliver a clock signal reinforced to the last end of the rambus DRAMs.

Hereinafter, a rim (RIMM) device incorporating a phase-locked loop of the present invention will be described with reference to the accompanying drawings.

Figure 4 is a block diagram of a motherboard having a rim (RIMM) device with a phase synchronization loop according to an embodiment of the present invention, Figure 5 is a block diagram of a rim (RIMM) device with a phase synchronization loop of the present invention 6 is a detailed configuration diagram of portion 'A' of FIG. 5.

BACKGROUND OF THE INVENTION Semiconductor memory devices are moving toward higher integration and higher speed, and a method of increasing a bus or increasing a frequency for high bandwidth is used. Among them, the Rambus dynamic semiconductor memory device (RAMBUS DRAM) having 89 bandwidths of 500 MByte / second has been used as a product having the highest bandwidth to date.

In the present invention, a rim (RIMM) device having a plurality of rambus DRAMs and having a phase-locked loop to reinforce attenuation of a clock signal will be described.

First, as shown in FIGS. 4 and 5, a rim 32 device having a phase-locked loop according to the present invention includes a plurality of rambus DRAMs RDRAM1 to RDRAMn connected in series and an arbitrary rambus among a plurality of rambus DRAMs connected in series. A phase locked loop (PLL) 35 is provided between the DRAMs to reinforce the clock signals applied to the plurality of Rambus DRAMs with attenuation over time.

And as shown in FIG. 4, the motherboard for driving the rim device includes a rim 32 including a plurality of rambus DRAMs and a phase locked loop 35 interposed therebetween, and each Rambus DRAM in the rim 32. The position of a single unit (rambus DRAM) is set through a clock generator 33 for inputting a clock signal to the RDRAM and a clock signal generated by the clock generator 33 when data is read or written. The master 31 sends a control command to read or write data to a corresponding unit, a signal reflection preventing unit 34 for preventing reflection of a signal classified in the rim 32, and a reference voltage Vref. It is provided with an applying end.

The signal reflection prevention unit 34 separates the signal input from the master 31 to the rim 32 into three types of data signals, control signals, and clock signals on the rim 32, and then reflects the classified signals. It is to prevent the role.

The phase locked loop (PLL) 35 receives the attenuated clock signals used in the plurality of Rambus DRAMs and reinforces its phase to deliver the enhanced clock signals to the end of the Rambus DRAMs.

As shown in FIG. 5, the above-described rim 32 includes a plurality of rambus DRAMs RDRAM1 to RDRAMN: D1 to DN, and a phase locked loop (PLL) 35 between arbitrary Rambus DRAMs. There is).

At this time, the phase locked loop 35 includes a clock applied to the master from the clock generator 33 (RCTM / N, LCTM / N), and a clock applied to the clock generator 33 from the master. from Master) (LCFM / N, RCFM / N) signals.

In addition, there are two paddles (left paddle 36 and right paddle 37) for outputting data, clock signals, and control signals to a plurality of rambus DRAMs. Signals (LDQA, LDQB and RDQA, RDQB), low bus (LROW, RROW) signals, column bus (LCOL, RCOL) signals, clock signals (Clock to Master, Clock from Master), Clock input signals LSCK and RSCK, a series of instructions LCMD and RCMD applied from the control resist, a logic reference threshold voltage Vref, and a first rambus DRAM D1 to an Nth rambus DRAM DN. There is a series of input signals Sin input and an output signal Sout output to the N-th Rambus DRAM DN.

In addition, as shown in FIG. 6, a clock for applying a clock signal (RCTM / N, LCFM / N) generated from a right paddle or a left paddle is illustrated in FIG. 6. Receives a signal from the signal applying terminal CLK and the feedback signal applying terminal FBIN for applying the feedback signal, and receives the phase synchronizing loop 35 for synchronizing the delayed clock signal and the power supply voltage AVcc as an optional signal. The comparison output unit 39 for comparing and outputting the signal output through the phase synchronization loop 35 and the clock signal input through the clock signal applying stage, and the phase synchronization loop 35 of the comparison result of the comparison output unit 39. If the clock signal outputted through the same signal as the clock signal input terminal CLK, the clock output terminal CLKOUT receives the clock signal CLK and outputs the clock signal terminal LCLC / N or RCFM / N of the left or right paddle. ) And the comparison output unit 39 When the clock signal outputted through the phase synchronization loop 35 is different from the clock signal inputted from the clock signal applying terminal CLK (large or small), the feedback is fed back to the feedback signal applying terminal FBIN. It consists of signal output terminal (FBOUT).

At this time, buffers 38a and 38b are provided between the clock signal applying terminal CLK and the phase synchronizing loop 35 and between the feedback signal applying terminal FBIN and the phase synchronizing loop 35, respectively. The buffers 38c and 38d are provided between the 39 and the clock output terminal CLKOUT and between the comparison output unit 39 and the feedback output terminal FBOUT, respectively.

In addition, there are four clock signals input to the phase-locked loop 35, RCTM, RCTN, LCFM, and LCFN. The clock signals outputted through the phase-locked loop 35 also correspond to LCTM corresponding to the clock signal. Since there are four LCTN, RCFM and RCFN, four phase synchronizing loops 35 having the above-described configuration are required between the Rambus DRAMs.

When the master 31 reads or writes data, the clock signal generated by the clock generator 33 is detected to set the position of a single product (the Rambus DRAM to be read and written).

After that, a control command is sent from the master 31 to read or write data to the set unit.

At this time, the clock signal is attenuated by the clock signal output from the first clock generator 33 while passing through a plurality of Rambus DRAMs, making it difficult to accurately read or write data to a desired unit (rambus DRAM). Thus, the clock signal is attenuated. By reinforcing through the phase synchronizing loop 35 shown in FIG. 6, the reinforcement signal is transmitted to the last stage of the unit, and data is read or written to the desired unit.

As described above, a rim (RIMM) device incorporating the phase-lock loop of the present invention has the following effects.

First, a phase-locked loop is provided between arbitrary Rambus DRAMs in the rim to reinforce the attenuation of the clock signal so that the clock signal is reinforced up to the last Rambus DRAM. Can / light

Second, since the attenuation of the clock signal can be reinforced through the phase synchronization loop, data can be read / written correctly even if the number of components in the rim increases, so that the number of components in the rim increases the recognition capacity. Can be extended.

Claims (4)

A plurality of rambus DRAMs connected in series, And a phase-locked loop configured between the random rambus DRAMs so as to reinforce the clock signal applied to the plurality of rambus DRAMs to attenuate with time, to deliver the clock signal reinforced to the last end of the rambus DRAMs. Rim device with built-in phase synchronization loop. The clock generator of claim 1, further comprising: a clock generator for generating clock signals to be applied to the plurality of Rambus DRAMs for driving the rim device; A master for setting a position of the Rambus DRAM through a clock signal generated by the clock generator and outputting a control signal for reading or writing data to the set Rambus DRAM; A signal reflection prevention unit for preventing reflection of a signal output from the rim device; And a reference voltage application unit configured to apply a reference voltage to the plurality of Rambus DRAMs. The method of claim 1, The configuration for outputting the clock signal reinforced by the Rambus DRAM First and second clock signals to be applied from the clock generator to the master; a clock signal input terminal for generating third and fourth clock signals to be applied from the master to the clock generator; A phase synchronizing loop for synchronizing the delayed clock signal by receiving the clock signal output from the clock signal applying stage and the feedback input signal output from the feedback signal applying stage, respectively; A phase synchronizing loop for comparing a clock signal output from the clock signal applying terminal with a clock signal output through the phase synchronizing loop and outputting a clock signal to a clock signal output terminal or a feedback signal output terminal; Built-in rim device. 4. The apparatus of claim 3, further comprising: first and second buffers respectively configured between the clock signal applying end and the phase synchronizing loop and between the feedback signal applying end and the phase synchronizing loop; And a third and fourth buffers configured between the output terminal of the comparison output unit and the clock signal output terminal, and between the output terminal of the comparison output unit and the feedback signal output terminal, respectively.