KR20010052109A - InxGa1-xP Stop-Etch Layer for Selective Recess of Gallium Arsenide-based Epitaxial Field Effect Transistors and Process Therefor - Google Patents

Abstract

The present invention is directed to an In _x Ga _1-x P etchstop layer for improving the uniformity of epitaxial wafer traversal mechanisms using high-low-high MESFET structures. The range of x tolerances varies as a function of the thickness of the etchstop layer. To this end, x is preferably 0.5 so as to maintain lattice match with the GaAs substrate. Also disclosed is a novel method for selective recess etching of GaAs field effect transistors. The present invention provides selective recess etching for a material to the point where a relatively uniform thickness of n material remaining on the chatl layer is realized by the use of a relatively thin layer (10-30 angstroms) of In _x Ga _1-x P material. It suggests running

Description

In epitaxial layer of gallium arsenide epitaxial field effect transistor and method for manufacturing the same {InxGa1-xP Stop-Etch Layer for Selective Recess of Gallium Arsenide-based Epitaxial Field Effect Transistors and Process Therefor}

The present invention relates to a recess etch method having a selective chemical action beneficial for the fabrication of gallium arsenide epitaxial field effect transistors.

A gallium arsenide field effect transistor using a depletion region formed by a metal, semiconductor junction, commonly known as a Schottky junction, is characterized by gallium arsenide and associated ternary, Because of the inherent properties of indium gallium arsenide, an approach has been taken as a high performance transistor technology.

Such mechanisms are well known to those skilled in the art for metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), pseudomorphic high electron mobility transistors (PHEMTs), two-dimensional electron gas field effect transistors (TEGFETs), and modulation doped field effects. Reference is made to various names such as transistors (MODFETs). Details of charge transfer dynamics in these structures can be found on pages 38-55 and 141-154 of the quantum semiconductor structure of Weisbuch et al., 1991, published by Academic Press, which is incorporated herein by reference.

In field effect transistors (FETs), the current between the source and drain contacts is controlled by the potential applied to the gate electrode. The function of this mechanism is relatively basic. In logic circuits, mechanisms often function as switches due to the fact that in a region known as a channel, the gate voltage acts in a similar way to the turn-off current value between the source and drain.

In an analog circuit, the short time change voltage on the gate becomes the time change current between the source and the drain. Since the gate current is theoretically pure displacement current, the micro input power can be easily amplified.

Gallium arsenide metal semiconductor field effect transistors, known as MESFETs, have relatively thin, highly doped semiconductor layers, source and drain currents flowing through channels.

The current is controlled by the gate forming a Schottky barrier on the semiconductor and excludes the semiconductor layer of electrons under the gate in accordance with the applied gate voltage.

The other instruments listed above to include HEMT, pHEMT, and MODFETs are based on the basic principles described above.

The structure of the basic HEMT is based on a heterojunction between two dissimilar materials, namely aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs), which are commonly known to those skilled in the art. The essential structure consists first of a semi-insulating substrate on which a buffer layer of GaAs doped unintentionally doped above. An n-doped layer of gallium arsenide, or pseudo-indium gallium arsenide, forms the channel of the instrument. An n layer of Al _x Ga ₁ - _x As is disposed on top of the channel layer to form a suitable Schottky barrier with gate metallization. The last layer is typically a GaAs contact layer that is highly doped n-type to facilitate the formation of resistive contacts in the lower channel layer. The two resistive contacts disposed in this layer are generally referred to as source and drain contacts. The access resistances associated with the underlying semiconductor material for these contacts and the intrinsic instrument are typically referred to as source and drain resistors Rs and R ', respectively.

In analog applications, there are several factors that are important. For this purpose, gain, noise and total microwave output are the most factors to consider in the design of GaAs-based FETs. The transconductance or "gain" of the FET mechanism is defined as follows.

g _n = dI _ds / dVg

Where I _ds is the current between the drain and the source, and Vg is the gate voltage. G _m can also be evaluated for a Hi-Lo-high MESFET with a relatively thin channel layer, for example by the following description.

g _m = εV _sat w _g / t

At this time. ε is the dielectric constant of GaAs, V _sat is the saturation rate of electrons in GaAs, w _g is the width of the gate electrode, and t is the gate electrode with respect to the channel spacing. See, for example, JLWalkg's High-Power GaAs FET Amglifiers, pages 50-56, issued by Artech House of Boston, United States, which is hereby specifically incorporated by reference. In order to first command the speed of operation of the instrument, it is necessary to reduce structures such as the substantially possible gate length and to find structures and materials with the high average speed of the carrier under the gate. Other observations can be made from the above formula.

The gain is large because the n-material layer is made thin under the gate metal. From the simple conduction of electrostatics, the thinner the n-layer between the channel and the gate metal, the greater the effect of the electric field on the channel conductivity through the depletion of the carrier. Therefore, by making this layer thinner, for a change given to the gate voltage, greater control over the conductivity of the channel is realized, and thus a larger change to I _ds is implemented.

Thus, the transconductance is larger. Thus, the closer the gate metal strip approaches the channel, the lower the voltage needed to reduce the pinch off voltage or drain current to negligible values.

Thus, briefly summarizing, the GaAs FET structure of the device disclosed in the present invention modulates the conductivity of the underlying channel by applying a potential to the gate and thereby reduces the source-to-drain current formed from the positive potential applied to the source from the drain. Function to control Highly doped channels (n +), lightly doped (n−) Schottky layers and highly doped n + contact layers are known as hi-looh-high structures. The material is chosen to improve the speed of the carrier in the channel, allowing the formula to improve the gain of the instrument.

Fabrication of FET devices is common to require a repeatable single wafer recess etch process as a technique for fabricating devices with performance characteristics of saturated drain-to-source current, transconductance and pinch-off voltage within tolerances. . Such recess etch is used to increase the transconductance of the instrument and at the same time improve the breakdown voltage of the transistors on pages 66-72 of the High-Power GaAs FET Amplifiers section above. In particular, the proper etch depth is obtained by etching the wafer, measuring the source-drain current, and repeating this procedure until the writing target voltage is obtained. To this end, the contact layer on which the drain and source metals are disposed is etched to expose the n-layer, which provides a surface on which the gate electrode is subsequently disposed. This iterative procedure requires heavy labor for a technician to produce a drain-source current where each iteration for the etch is determined when a target current is obtained. In addition, this labor-intensive method is often not repeated in a reliable way. In addition, some constant point is reached in the etching method in which the source-drain current reaches an unacceptable value. This condition is referred to as over-etching and results in an instrument that does not meet the performance specifications. Additionally, such repetitive processing crosses the wafer and results in variations in etch depth from the wafer-to-wafer. Two-dimensional variation has a direct impact on performance variation. For example, a 5% cross wafer variation in pinch off voltage is realized. The variation of the parameters according to this method can typically exceed 12%. Parameter variation is defined here as the standard deviation divided by the mean.

The use of selective chemical properties to stop the recess etching process to a depth determined by the location of the etch-stop layer has been shown to increase depth uniformity and reproducibility.

The advantage of such a mechanism is that it can control the gate-to-channel spaced to a predetermined level defined by the uniformity of the process used to form the epitaxial layer. Additionally, sufficient labor input can be reduced from the etch procedure as the recess etch is performed in batch. Prior techniques for providing etchstops have been done with materials such as AlAs, in particular Al _x G _a1-x As.

Such techniques are described in US Pat. No. 5,374,328 to Remba et al., The contents of which are incorporated herein by reference.

Unfortunately, the use of such materials can have a detrimental effect on the instrument through an increase in instrument access resistance. As mentioned above, access resistance is a general term used to describe what is commonly referred to as source and drain resistance in the art. An increase in instrument source resistance, for example, reduces the incidental transconductance of the instrument described by the following relationship found in many topics on semiconductor instrument physics (e.g., published in 1969 as a technique used as reference of the present invention). SMSze by John Whiley and Sons, New York, see page 355 of Physis of Semiconductor Devices.

g _me = g _mi / (1 + g _mi R _s )

Where g _me is the negative transconductance of the instrument measured at the external terminal; g _mi is the internal transconductance when the source can be neglected and R _s is the source resistance of the device. In addition, increasing the instrument access resistance increases the drain-source voltage, which saturates what drain current is often referred to as the knee volatage in the art. Increased knee voltage can limit the power performance of the instrument. This access resistance is often described as consisting of two main elements, one associated with the metal-semiconductor interface and the other associated with the semiconductor material outside the forces of the gate electrode. Insertion of the etch-stop layer into the structure adds an additional resistive component to the instrument access resistance. This component relates to the tunneling barrier imposed by the offset in the minimum allowable energy of the conducting electrode between two dissimilar materials known as conduction band discontinuities. The larger the conduction band discontinuity, the larger the associated resistance. The reported experimental value of conduction band discontinuity for AlAs / GaAs material systems is around 500mV.

Therefore, what is needed is a method of manufacturing an apparatus that has improvements in the apparatus and apparatus manufacturing and does not suffer from the drawbacks of the increased access resistance used as conventional etch-stop materials while being implemented with appropriate etch-stop materials.

The present invention relates to an In _x Ga _1-x P etch-stop layer that increases the uniformity of the epitaxial wafer traverse mechanism using a hi-lo-high MESFET structure. The acceptable range of values of x is broad as a hams of the thickness of the etch-stop layer. To this end, x is preferably about 0.5 to maintain the lattice match with the GaAs substrate. In addition, a new process of selective recess etching of GaAs FETs has been disclosed. The present invention uses the relatively thin (10-30 angstroms) of In _x Ga _1-x P material to perform selective recess etching of the material at a point where a relatively constant thickness of n-material remaining on the channel layer is realized. Intended. By using the material described above for the etch-stop, a sufficient reduction in the access resistance is realized for the mechanism containing other etchstop materials, and an improvement in the uniformity of the wafer and the mechanism characteristics with the wafer is also realized. In addition, this technique is helpful for batch processing which reduces process labor.

On the other hand, in an exemplary embodiment, the etch stop layer has a metal material for the weight electrode deposited on top, but in an alternative embodiment, the In _x Ga _1-x P etch stop portion is removable and the metal portion is the lower n-layer. Can be run directly on. This alternative embodiment has the advantage that a high selectivity is obtained and thereby the improved uniformity in mechanical properties is realized across the wafer and from wafer to wafer. This improved selectivity is caused by the availability of etching chemistries which etch In _x Ga _1-x P at a definite rate but exhibit a relatively negligible etch rate for the underlying GaAs layer or for unclear selectivity. One example of such wet chemistry is the HCl: H ₃ PO ₄ : HCl system. In contrast, the best choice for GaAs date realization for In _x Ga _1-x P was limited to 150 levels. Thus, an optional material for the etch stop layer of the present invention exhibits selectivity for etching the contact layer for drain and source and also provides an In _x Ga _1-x P etch stop layer to effect metallization directly on the n-material. Demonstrate the ability to etch through directly.

Finally, note that the thick layer of etch stop material provides a high vias voltage and a large current swing, providing a double junction between the n-layer GaAs and the etch stop layer, which ultimately results in an increase in the maximum open channel current, Imax. Is that.

It is an object of the present invention to realize a gallium arsenide epitaxial field effect transistor structure having constant electrical performance parameters within the wafer crossing and wafer and wafer tolerance defined by the epitaxial layer growth process.

It is a feature of the present invention to have an etch stop layer that executes a uniform distance between the gate layer and the channel layer of the wafer traversal mechanism without a drop in instrument access resistance.

It is another object of the present invention to provide a method for fabricating GaAs field effect transistors within a wafer-to-wafer tolerance that is uniformly across the wafer and defined by epitaxial layer growth processes and batch processing.

It is another feature of the present invention to provide a method of using an etchstop layer that executes a uniform distance between the gate and the channel layer of a wafer traversal instrument without a drop in instrument access resistance.

Another advantage of the present invention is the use of a batch mode process to implement the formation of a recessed area in the instrument that maintains the level of instrument performance comparable to large labor intensity techniques.

1-6 show the instrument showing various processing steps of the present invention, and FIG. 6 shows features of the final instrument of the present invention. The present invention is in a high-low-high gallium arsenide epitaxial FET structure. The focus of the present invention relates to the scope of the MESFET, and it will be apparent to those skilled in the art that the present invention is directed to an epitaxial instrument in which a Schottky barrier is used to control the current in the channel and the common substrate material of all instruments is GaAs. Has applicability. As discussed above, a sufficient reduction in labor intensity, increase in control time and uniformity across a given waiter are realized by the use of In _x Ga _1-x P used as etch stop material in the apparatus of the present invention. To this end, the low conduction to discontinuity is converted to the low resistance component of the overall access resistance. The experimental value for conduction band discontinuity between In _x Ga _1-x P and GaAs varies from 30 to 220 meV, with typical values falling to the range of 180 to 220 meV. The conventional etchstop uses other materials, such as AlAs, or Al _x G _a1-x As, as described above, and also exhibits excellent selectivity for GaAs, which in turn has increased access resistance as described above. . Thus, increased access resistance has an adverse effect on parameters such as maximum open channel current, voltage and transconductance. In contrast, the use of the In _x Ga _1-x P etch stop of the present invention results in a low conduction band discontinuity at the interface with the n-GaAs Schottky layer and also a low tunneling barrier to current flow, thus providing Low access resistance. This enhances the benefits of the etchstop while maintaining the performance characteristics of the device fabricated without the etchstop, which has the drawback of non-uniformity across the wafer as described above. A typical value of x is 0.5 to maintain the lattice match with the GaAs substrate. However, a value other than 0.5 may also be selected from time to time, J. Crytal Growth, published in 1974, JW Matthew, Vol. 27, pp. 118-125, "Defects in epitaxial multilayers I. Misfit" by AEBlakeslee. dislocations "to minimize the misfit dislocation density described.

The manufacture of the appliance will now be described. 1, a semi-insulated AaAs substrate is indicated by reference numeral 101. This layer has an unintentionally doped GaAs buffer layer 102 disposed thereon and an n-doped GaAs layer 103 which is a channel layer. This layer has a doping level in the order of 3x10 ¹⁷ cm ^-3 .

Arranged on top of the channel layer is a sortie barrier layer 104, which is a n-type lightly doped GaAs layer. This layer has a doping level of 5 cm x 10 ¹⁶ cm ^-3 . Schottky barrier layer 104 has a thickness in the range of 200-1000 Angstroms, preferably 430 Angstroms in size. As mentioned above, the distance between the gate metal and the channel layer 103 is influenced by the thickness of the layer 104, and thus this layer plays an important role in the instrument parameters described herein. An etchstop layer of In _x Ga _1-x P is shown at 105. This layer typically has a size of 10-40 Angstroms thick. Additional advantages for the use of In _x Ga _1-x P layers are described.

The metal disposed on the In _x Ga _1-x P surface exhibits a large barrier height, which is known to the skilled person as Schottky barrier height and that placed on the GaAs surface as compared to the forward conduction of the electrons, and is therefore tentative to the instrument. As a result, a large maximum open channel current flows.

Referring again to FIG. 1, layer 106 is a continuous portion of Schottky layer 104 on the bottom surface. The main purpose of this layer is to spatially separate the gate electrode from the highly doped line layer 107, thereby maintaining a reasonable breakdown voltage for this junction. The contact layer 107 is a highly doped n + layer that facilitates the vague ohmic contact of the drain and source described herein. Schottky layer 104, on the other hand, is lightly doped to facilitate the formation of a good Schottky barrier. As described above, the gate-to-channel is selected to realize a particular pinch-off voltage Vp among many other parameters.

In Figure 2, a resistive contact formula is also discussed. Generally, it is formed by defining lithographically contacted sites and by evaporating a suitable metal alloy, such as AuGeNiAu, followed by a subsequent lift off step of the photoresist layer. Such processing steps are known to those skilled in the art and the final resistive contact is indicated at 201 for the source and 202 for the grain. 3 shows implant isolation performed. In order to properly isolate one instrument on one wafer from another instrument, isolation implantation is performed in the outer region of the instrument side boundary. These are shown as 301. The region outside the active semiconductor region is electrically inactivated by an implant of the same kind as the typical implant material Baron. Proton implantation (H +) may also be used in some cases. This implant profile extends into the semi-insulating GaAs substrate 101 and serves to adequately insulate the instrument. Alternatives to this method are also well known to those skilled in the art, where performing mesa insulation, the required layers of the instrument are arranged in mesa form by etching to remove the active material from all areas outside the instrument boundary.

4, an alternative recess etch of the gate region is shown in this figure. This is indicated by reference numeral 401. The gate area 401 is defined in the opening of the photo printing film. This area is etched to remove portions of the highly doped contact layer 107 and the schottky layer 106 prior to the deposition of the gate electrode material, which is the main focus of the present invention. With the etchstop 105 inserted at the appropriate depth, a chemistry of etching GaAs at a higher etch rate compared to the In _x Ga _1-x P etch rate is used to form the recess. In an exemplary embodiment of the invention, such selective chemistry is H ₂ SO _4: H ₂ O _2: H ₂ O with a volume ratio of 1: 8: 500. For this chemical composition, Applicants decided that the GaAs etch rate was 10 Angstroms per second at room temperature and the etch rate ratio GaAs to In _0.5 Ga _0.5 P was 150. It will be appreciated that this chemistry is exemplary and other chemistries are possible. To this end, the main purpose of etchstop is to allow the etching of layers 106 and 107 to proceed at a much faster rate than the etching of layer 105. By selecting the appropriate chemicals and thereby ensuring an appropriate ratio of the etch rates of the etch stop layer 105 to the etch rates of the layers 106 and 107, a relatively uniform recess etch depth is obtained across the wafer. In addition, the wafer uniformity across the gate to channel dimensions is determined by the uniformity of epitaxial layer 104.

After etching to the etchstop layer is completed, the gate electrode 601 is manufactured through a lamination technique known to those skilled in the art. Using the same lithographic layer for recess definition, the Schottky contacts are stacked and lifted up. A typical gate electrode stack will be composed of-TiPtAu. Following this, the instrument is normally inactivated as a dielectric, such as silicon nitride, and connected together with other circuitry with metalized additional layers. Optionally, the proportion of etchstop layer 105 exposed by the lithographic film used to define the recess may be selectively removed to reveal the underlying layer 105 prior to the gate electrode deposition.

Other thicknesses are possible but their etch stop thickness is preferred, namely 10 angstroms and 20 angstroms. Using a 20 Angstrom In _x Ga _1-x P layer as etchstop, the following wafer average instrument parameters are executed. Imax of 400 mm 3 / mm compares very well for wafers made through conventional techniques. In addition, a pinch off voltage of 1.78 volts is very well compared to conventionally manufactured instruments. The inherent transconductance of an instrument made by the technique of the present invention with a 20 angstrom etchstop layer has a specification of 156 mS / mm compared to an instrument made by the prior art without an etchstop layer. Finally, the sum of the source and drain resistances shows no sufficient difference for an instrument made without etch stop. For clarity, this is in sharp contrast to instruments manufactured with epitaxy using different materials for the etchstop layer in which the access resistance has been discussed above.

It has been found that the use of a thin AlAs layer with a size of 10 Angstroms thick increases the combined source and drain resistance by more than 40% with respect to the control sample that does not contain such a stop layer. The advantages of the process procedure known as contact resistance are also compared to the 2 thicknesses (10 and 25 angstroms) of AlAs and the 2 thicknesses (10 and 20 angstroms) of In _0.5 Ga _0.5 P etchstop, where the samples do not contain any etch stop layer. Do not. AlAs samples showed 0.3 and 0.8 Ohm-mm for 10 and 25 Angstrom cases, respectively, compared to 0.1 Ohm-mm of control samples. The difference in this value results in a reduction in the electron tunneling probability associated with a relatively large conduction band discontinuity at the AlAs / GaAs interface. For the In _0.5 Ga _0.5 P case, no difference was observed between the samples including the control samples. That is, everything shows a contact resistance of 0.15 Ohm-mm magnitude. The latter result suggests that it does not represent every additional vortex resistance element compared to the vortex resistance element of a control sample mechanism that does not utilize the etchstop layer of the present invention of a 20 angstrom thick In _0.5 Ga _0.5 P etchstop layer.

Finally, an alternative embodiment of the invention is shown in FIG. To this end, the In _0.5 Ga _0.5 P layer can be removed by highly selective chemistry. This region 501 has an In _0.5 Ga _0.5 P layer removed by appropriate chemistry. An example of a wet etch chemistry exhibiting a high In _0.5 Ga _0.5 P etch rate to a size of 1 micron / min (no recognizable GaAs etch rate was observed in this case), more specifically Hcℓ: H ₃ PO ₄ : HcL is such a chemical formula. Therefore, the selectivity ratio is substantially infinite. This alternative has certain advantages for high selectivity, which gives more uniformity to the etch depth.

The improvement of the cross-wafer parameter variation by the use of the In _x Ga _1-x P etch stop layer is similar to that obtained with a wafer comprising an AlAs etch stop layer. However, as discussed above, the combined access resistance (R _x + R _d ) of the modified instrument compares well to instruments made without an etchstop layer. This includes AlAs and Al _x Ga _1-x As, in contrast to instruments fabricated with other etchstop layers, where a sufficient increase in access resistance is realized to compromise the intrinsic transconductance of instruments fabricated with materials such as 2. Is that.

Although the present invention has been described in detail above, various modifications may be made by those skilled in the art within the scope of the present invention. To this end, the present invention provides an etchstop layer that enhances the increase in transverse wafer parameter uniformity by a uniform recess depth without deleterious effects on the mechanism access resistance associated with conventional etchstop layers.

The scope of the present invention applies to the extent permitted by other materials and chemistries for etching such materials.

Claims (26)

A channel layer disposed between the source and the drain, a schottky layer disposed on the channel layer, a gate disposed on the schottky layer, and an etchstop layer disposed between the schottky layer and the gate, The etch stop layer is I _nx Ga _1-x P Hi-Lo-high metal semiconductor field effect transistor (FET) The method of claim 1, FET characterized in that the etchstop layer is I _nx G _a1-x P with 0.4 ≦ _x ≦ 0.6 The method of claim 1, The etchstop layer is removed in a lithographically defined area and the gate is disposed in the opening area, the gate being in electrical contact with the schottky layer. The method of claim 1, An FET wherein the Schottky layer has a first thickness, the etchstop layer has a second thickness, and wherein the first and second thicknesses define a gate-to-channel spacing The method of claim 4, wherein The first thickness is in the range of 200-800 angstroms The method of claim 4, wherein The second thickness is within the range of 10-40 angstroms A GaAs n + channel formed between the drain and the source and having an n-doped GaAs Schottky layer disposed thereon, an etchstop layer disposed on the Schottky layer, and a gate disposed on the etchstop layer, The etchstop layer is In _x Ga _1-x P field effect transistor (FET) characterized in that The method of claim 7, wherein The etchstop layer has an opening in itself and the gate is disposed in the opening, the gate being in electrical contact with the schottky layer. The method of claim 1, The schottky layer having a first thickness and the etchstop layer having a second thickness, wherein the first and second thicknesses define a gate-to-channel spacing The method of claim 9, The gate-to-channel spacing is in the range of 100-1000 angstroms The method of claim 7, wherein Etch stop layer is FET characterized in that the In _x Ga _1-x P in the range 0.4≤x≤0.6 The method of claim 9, The first thickness is in the range of 200-800 angstroms The method of claim 9, The second thickness is within the range of 10-40 angstroms Growing an n-channel layer of GaAs in a buffer layer, growing a Schottky or the like in the channel layer, epitaxially growing an etchstop layer in the Schottky layer, and growing the GaAs in the etchstop layer Growing the first and second layers while the second layer is a highly doped contact layer; Selectively etching portions of the first and second layers to form a gate region, wherein the first and second layers have a first etch rate and the etchstop layer is subjected to a selected etch chemistry. Has two etch rates; Wherein said first and second etch rates have a ratio of about 150 magnitudes. The method of claim 14, The method of manufacturing a semiconductor device, characterized in that the etch chemical is H ₂ SO ₄ : H ₂ O ₂ : H ₂ O The method of claim 14, A method of manufacturing a semiconductor device, characterized in that a gate metal layer is laminated on the gate region. The method of claim 14, Wherein the etchstop layer has a thickness of 10-40 Angstroms in size. The method of claim 14, Opening a window to the etch stop layer through a second etching chemistry and depositing a gate metal layer therein, the gate metal being in electrical contact with the schottky layer. The method of claim 7, wherein The second etch chemical is HCl: H ₃ PO ₄ : HCl manufacturing method characterized in that the Growing an epitaxial buffer layer of unintentionally doped GaAs on a GaAs substrate, growing an epitaxial n-channel layer in the buffer layer, growing a Schottky layer in the n-channel layer, n -Growing an etchstop layer in the channel layer, growing first and second layers of GaAs in the etchstop layer, and forming the recesses in the first and second layers Optionally etching the layer as etch chemistry; And the etchstop layer is In _x Ga _1-x P. The method of claim 20, Wherein the etchstop layer is In _x Ga _1-x P in the range 0.4 ≦ _x ≦ 0.6. The method of claim 20, The method of manufacturing a semiconductor device, wherein the etch chemical is H ₂ SO ₄ : H ₂ O ₂ : H ₂ O. The method of claim 20, A method of manufacturing a semiconductor device, characterized in that a gate metal layer is laminated on the gate region. The method of claim 20, Wherein said etchstop layer has a thickness of 10-40 Angstroms in size. The method of claim 9, Opening a window to the etch stop layer through a second etching chemistry and depositing a gate metal layer therein, the gate metal being in electrical contact with the schottky layer. The method of claim 25, Wherein the second etch chemical is HCℓ: H ₃ PO ₄ : HCℓ