KR20010048250A - Data output circuit of semiconductor memory device - Google Patents

Abstract

PURPOSE: A data output circuit of a semiconductor memory device is provided to achieve a stable operation as to the variation of a temperature, a voltage and a process by being controlled by a self-timing. CONSTITUTION: According to the data output circuit, a driver(300) performs a pull-up and a pull-down driving of a data output node(do). An internal output control signal generation part(310) generates an internal output control signal(outoffb) activated by a self-timing to a pull-up signal(pu) or a pull-down signal(pd) in response to the pull-up signal, the pull-down signal and an external output control signal(outoff) setting a data output interval. And, a latch circuit part(320) controls the pull-up and pull-down driving of the driver by receiving the internal output control signal and the pull-up signal and the pull-down signal.

Description

Data output circuit of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor memory device, and more particularly, to a data output buffer that realizes stable operation even with changes in temperature, voltage, and process.

In general, a semiconductor memory device includes a data output circuit for outputting data out of a chip, and a synchronous memory device is configured to continuously output data in a section only when the control signal is activated in response to a control signal. It is.

1 is a data output circuit diagram according to the prior art.

Referring to FIG. 1, a conventional data output circuit sets a driver 110 for pulling up and pulling down an output node do, a pull up signal pu, a pull down signal pd, and a data output section. The latch circuit unit 100 controls the pull-up and pull-down driving of the driver 110 in response to an output control signal (outoff).

Specifically, the latch circuit unit 100 inverts the output control signal outoff to output the inverted output control signal outoffb, the pull-up signal pu, the inverted output control signal outoffb, and the second. A first NAND gate 102 receiving an output signal of the NAND gate 103, a pull-down signal pd, an inverted output control signal outoffb, and an output signal of the first NAND gate 102; Inputs of the NAND gate 103, the first and second inverters 104 and 105 connected in series to the output of the first NAND gate 102, and the output of the second NAND gate 103. The third inverter 106 is configured.

In addition, the driver 110 receives the output signal PUb of the second inverter 105 as a gate, and a pull-up transistor having a source-drain path formed between the first supply power supply voltage vextq and the output node do. Mu and the output signal PD of the third inverter 106 are input to the gate, and a source-drain path is a pull-down transistor Md formed between the second supply power supply voltage veeq and the output node do. The pull-up transistor Mu is implemented as a PMOS transistor, and the pull-down transistor Md is implemented as an N-MOS transistor.

In the data output circuit of FIG. 1, the first, second, and third inverters of the latch unit may be omitted, as necessary, in consideration of logic implementation and other environments. For example, when the pull-up transistor is implemented as an NMOS transistor, the second inverter 105 may be omitted. When the output control signal (outoff) input from the outside is set as a high active signal, the first inverter 101 may also be omitted.

FIG. 2 is a timing diagram of each signal with respect to FIG.

First, if the output control signal outoff is at a high level, the inverted output control signal outoffb is at a low level and these signals are input to the first and second NAND gates 102 and 103 to unconditionally output their outputs. Therefore, the output signal PUb of the second inverter 105 becomes high and the output signal PD of the third inverter becomes low to turn off both the pull-up and pull-down transistors.

Next, when the output control signal outoff falls low to output data, the pull-up transistor Mu or the pull-down transistor Md are turned on by the low pulse of the pull-up signal pu or the pull-down signal pd. High or low data is output from the output node do.

However, time τ exists as shown in FIG. 2 according to changes in temperature, voltage, process, and the like. That is, the time τ between the moment when the inversion output control signal outoffb becomes high until the first active pull-up signal pu or pull-down signal pd comes in is present.

Therefore, since all inputs of the three-input NAND gates 102 and 103 go high, the latch is placed in an unstable state where the initial value of the latch is not determined, and there is a risk that incorrect data is output at this moment if the time?

The present invention has been made to solve the above problems of the prior art, the operation is controlled by self-timing to provide a data output circuit for implementing a stable operation even with changes in temperature, voltage, process, etc. There is this.

1 is a circuit diagram of a data output buffer according to the prior art;

2 is a timing diagram of each signal of FIG. 1;

3 is a circuit diagram of a data output buffer according to a preferred embodiment of the present invention;

4 is a timing diagram of each signal with respect to FIG.

Explanation of symbols on the main parts of the drawings

310: internal output control signal generator

320: latch circuit part

330: driver

A data output circuit of the present invention for achieving the above object comprises: a driver for pull-up and pull-down driving a data output node in a data output circuit of a semiconductor memory device; An internal output control signal generator for generating an internal output control signal that is self-timed and activated to the pull-up signal or the pull-down signal in response to an external output control signal for setting a pull-up signal, a pull-down signal, and a data output period; And a latch circuit unit configured to receive the internal output control signal, the pull-up signal, and the pull-down signal to control pull-up and pull-down driving of the driver.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 shows a data output circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, the data output circuit according to the present embodiment includes a driver 330 for pulling up and pulling down the data output node do, a pull up signal pu, a pull down signal pd, and a data output section. Generating an internal output control signal for generating an internal output control signal outoffb that is self-timed and activated in response to the pull-up signal pu or the pull-down signal pd in response to an external output control signal outoff. And a latch circuit unit 320 that receives the internal output control signal outoffb, the pull-up signal pu, and the pull-down signal pd to control pull-up and pull-down driving of the driver 110. Consists of.

The pull-up signal pu, the pull-down signal pd, and the external output control signal outoff are low active signals, respectively.

In detail, the internal output control signal generator 310 may include a first PMOS transistor Mp1 for transmitting a first supply power supply voltage Vcc to the node a in response to the pull-up signal pu, and the pull-down signal. a second PMOS transistor Mp2 that transfers the first supply power supply voltage Vcc to the node a in response to pd, and the internal output control signal outoffb after latching the signal of the node a. As a latch element to output, it implements and consists of inverter INV1 and INV2 connected in series.

The latch circuit unit 320 may include a first NAND gate 321 that receives the pull-up signal pu, an internal output control signal outoffb, and an output signal of a second NAND gate 322, which will be described later, and the pull-down signal. (pd), the second NAND gate 322 which receives the internal output control signal outoffb and the output signal of the first NAND gate 321, and the output of the first NAND gate 321 as inputs; And inverters 323 and 324 connected in series, and a third inverter 325 which uses the output of the second NAND gate 322 as an input. As mentioned in the prior art, the inverters 323, 324, and 325 may be omitted, as necessary, in consideration of logic implementation and other environments.

The driver 330 receives an output signal PUb of the second inverter 324 as a gate, and a PMOS transistor Mu that pulls up the output node and an output signal of the third inverter 325. An NMOS transistor Md receives the PD as a gate and pulls down the output node do.

Referring to Figure 4 will be described in detail the operation of the data output buffer of the present invention.

First, when the external output control signal outoff for outputting data only at the low level is at the low level, the nMOS transistor Mn of the internal output control signal generator 310 is turned off, and the external output control signal outoff generates the internal output control signal. Without affecting the operation of the unit 310, the pull-up signal (pu) or the pull-down signal (pd) input to the internal output control signal generation unit 310 has a low pulse, the PMOS transistors Mp1, Mp2 Is turned on to raise the internal output control signal outoffb to high. When the internal output control signal outoffb is input to the latch circuit unit 320 in a high state, the latch circuit unit 320 receives the pull-up signal pu and the pull-down signal pd. When the pull-up signal pu has a low pulse, the pull-down transistor Md of the driver 330 is received. ) To turn on the low data, and if the pull-down signal pd has a low pulse, turn on the pull-up transistor Mu to turn on the high data.

When the external output control signal outoff rises from low to high, the internal output control signal outoffb is made low by turning on the enMOS transistor Mn of the internal output control signal generator 310. The internal output control signal outoffb is input to the latch circuit unit 320 to make both its output signals PUb and PD high, and to turn off both the pull-up transistor Mu and the pull-down transistor Md to output the data output buffer. Will no longer be driven.

It should be noted that since the internal output control signal outoffb, which defines the data output interval, is generated by the pull-up signal pu and the pull-down signal pd differently than in the related art, the change in temperature, voltage, process, etc. Self-timed output control signal (internal output control signal) can be generated.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention uses the pull-up signal pu and the pull-down signal pd as a signal for controlling the data output circuit of the semiconductor memory device, thereby eliminating the need for timing margin. Implement a data output circuit to ensure stable operation even with changes in temperature, voltage, and processes.

Claims (7)

In a data output circuit of a semiconductor memory device, A driver 330 for driving the data output node do up and pull down; Self-timed and activated by the pull-up signal pu or the pull-down signal pd in response to an external output control signal outoff for setting a pull-up signal pu, a pull-down signal pd, and a data output period. An internal output control signal generation unit 310 for generating an internal output control signal outoffb; And The latch circuit unit 320 receiving the internal output control signal outoffb, the pull-up signal pu, and the pull-down signal pd to control pull-up and pull-down driving of the driver 110. Data output circuit consisting of. The method of claim 1, The internal output control signal generator 310, Node a; A first transistor Mp1 transferring a first supply power supply voltage to the node a in response to the pull-up signal pu; A second transistor Mp2 transferring the first supply power supply voltage to the node a in response to the pull-down signal pd; A third transistor (Mn) for transmitting a second supply power supply voltage to the node a in response to the external output control signal (outoff); And Latch elements INV1 and INV2 for outputting the internal output control signal outoffb after latching the node a signal. Data output circuit comprising a. The method of claim 2, The latch circuit unit 320, A first NAND gate 321 for receiving the pull-up signal pu, the internal output control signal outoffb, and an output signal of a second NAND gate 322 to be described later; And The second NAND gate 322 which receives the pull-down signal pd, the internal output control signal outoffb, and the output signal of the first NAND gate 321. Data output circuit comprising a. The method of claim 3, The latch circuit unit 320, First and second inverters 323 and 324 connected in series using an output of the first NAND gate 321 as an input; And A third inverter 325 having an output of the second NAND gate 322 as an input; Data output circuit, characterized in that further comprises. The method of claim 4, wherein The driver 330, A PMOS transistor (Mu) receiving the output signal PUb of the second inverter 324 as a gate and driving the output node up; And EnMOS transistor Md which receives the output signal PD of the third inverter 325 as a gate and pulls down the output node do. Data output circuit comprising a. The method of claim 2, And the pull-up signal, the pull-down signal and the external output control signal are low active signals, respectively, the first and second transistors are PMOS transistors, and the third transistor is an MOS transistor. The method of claim 4, wherein And the latch element comprises an even number of inverters connected in series for receiving the signal of the node a and outputting the internal output control signal (outoffb).