KR20010048128A - Dual apparatus of ATM board in base station controller of IMT 2000 system - Google Patents

Abstract

PURPOSE: A duplexing apparatus of an ATM board of a control station of an IMT2000 system is provided to stably maintain a system, continuously and stably maintain a high quality service and be easily adaptable in an ATM board development by implementing duplexing of ATM boards in a control station. CONSTITUTION: Cubits(11,31) receive an ATM cell inputted through a cell bus. Multiplexers(12,32) multiplex the ATM cell received from the cubits(11,13). The first buffers(13,33) are operated according to a buffer control signal of a master/slave EPLD by a CPU and provide a path for storing the ATM cells multiplexed by the multiplexers(12,32). The second buffers(14,34) are operated according to the buffer control signal of the master/slave EPLD and provide a path for storing the ATM cell received from the cubits(11,31). The third buffers(15,35) are operated according to the buffer control signal of the master/slave EPLD and provide a path for storing the ATM cell received by the cubits(11,31) and multiplexed by the multiplexers(12,32). The first SRAMs(16,36) store the ATM cell inputted through the first buffers(13,33) and the third buffers(35,15) of the other ATM board. The second SRAMs(17,37) store the ATM cell inputted through the second buffers(14,34) and the third buffers(35,15) of the other ATM board. CPUs(18,38) output a control signal according to various control information for receiving and storing the ATM cell. The master/slave EPLDs(19,39) controls a corresponding ATM board by a mater or a slave according to a control signal outputted from the CPUs(18,38) and controls operations of the first, second, third, fourth, fifth and sixth buffers. The fourth buffers(20,40) are operated according to the buffer control signal of the master/slave EPLDs(19,39) and provide a path for storing the control information of the CPUs(18,38). The sixth buffers(22,42) are operated according to the buffer control signal of the master/slave EPLDs(19,39) by the CPUs(18,38) and provide a path for storing the control information of the CPUs(18,38). The third SRAMs(23,43) store the control information of the CPUs(18,38) inputted through the fourth buffers(20,40) and the sixth buffers(42,22) of the other ATM board. DRAMs(24,44) store the control information of the CPUs(18,38) inputted through the fifth buffers(21,41) and the sixth buffers(42,22) of the other ATM board.

Description

Dual apparatus of ATM board in base station controller of IMT 2000 system

The present invention is to implement asynchronous transfer mode (hereinafter, referred to as "ATM") boards configured in the control station of the International Mobile Telecommunication (IMT) 2000 system in redundancy to maintain high quality service continuously and stably. A redundancy device of an ATM board in a control station of an IMT2000 system.

In general, the control station of the IMT-2000 system transfers four E1 signals input by connecting various boards developed by adopting the ATM method, that is, the base station and the control station to the E1, through the mux to the AMD Mux / Demux Assembly (AMDA). ATM Frame / Deframe Assembly (AFDA), which transfers data to the cell bus via Cubit, and STM-1 optical interface and ATM switches for signals transmitted from the AFDA through the cell bus. It consists of four ATM boards, AMDA, STIA (Selector & Transcoder Interface Assembly) and STBA (Selector & Transcoder Board Assembly), which perform the function of transmitting to the next block through the data block. From narrowband services such as telephony to broadband services such as video telephony, video conferencing, and high-speed data transmission, it is easy to integrate and apply signals with a wide bandwidth distribution.

Meanwhile, the ATM boards configured in the control station of the IMT2000 system are configured to exchange data with each other through a cell bus. In the related art, the ATM boards are not implemented in redundancy. Most importantly, there was a need to duplicate critical ATM boards in order to maintain high quality service continuously and reliably.

The present invention has been made to solve the above problems, and its object is to implement ATM boards configured in the control station of the IMT2000 system in redundancy so that the high quality service can be maintained continuously and stably. It is to provide a board redundancy device.

1 is a block diagram of a redundancy device of an asynchronous transmission mode board in a control station of an IMT2000 system according to the present invention;

<Description of the symbols for the main parts of the drawings>

10: first ATM board 30: second ATM board

11,31: qubit 12,32: mux

13,33: buffer 1 14,34: buffer 2

15,35: Buffer 3 16,36: SRAM1

17,37: SRAM2 18,38: CPU

19,39: Master / Slave EPLD 20,40: Buffer 4

21,41: Buffer 5 22,42: Buffer 6

23,43: SRAM3 24,44: DRAM

In order to achieve the above object, a duplexing device of an ATM board in a control station of an IMT2000 system of the present invention is configured by duplexing one ATM board into a first ATM board and a second ATM board of the same structure, and then a first ATM board and a second ATM board. Only one ATM board that has master rights while sharing data and information of CPU, SRAM, and DRAM in ATM boards is shared with the first ATM board and the second through the Master / Slave EPLD. By controlling the operation of the buffer in the ATM board, the data and information are maintained as it is even if the master right is changed.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the redundancy device of the ATM board in the control station of the IMT2000 system according to the present invention.

FIG. 1 is a block diagram of a redundancy device of an ATM board in a control station of an IMT2000 system according to the present invention, and includes a first ATM board 10 and a second ATM board 30 in which one ATM board is duplicated. The first ATM board 10 and the second ATM board 30 may include cubits 11 and 31 for receiving ATM cells input through a cell bus, and ATM cells received from the qubits 11 and 13. A mux 12, 32 for multiplexing and a buffer control signal of a master / slave EPLD by a CPU to be described later are provided to provide a path for storing the ATM cells multiplexed in the mux 12, 32. Buffer 1 (13, 33) and a buffer 2 which provides a path for storing ATM cells received in the qubits (11, 31) by operating in accordance with the buffer control signal of the master / slave EPLD by the CPU to be described later. (14,34) and received by the qubits (11,31) by operating in accordance with the buffer control signal of the master / slave EPLD by the CPU to be described later. A buffer 3 (15,35) providing a path for storing the multiplexed ATM cells at 12, 32, and the buffer 1 (13, 33) and the buffer 3 (35, 15) in the counter ATM board SRAM1 (16,36) for storing ATM cells, SRAM2 (17,37) for storing ATM cells input through the buffers 2 (14,34) and buffers 3 (35, 15) in counterpart ATM boards; CPUs 18 and 38 outputting control signals according to various control information for receiving and storing ATM cells, and corresponding ATM boards are operated as masters or slaves according to control signals output from the CPUs 18 and 38. Master / slave EPLD (19,39) for controlling and controlling the operations of the buffers 1, 2, 3 (13, 33), (14, 34), (15, 35) and the buffers 4, 5, and 6 to be described later. Buffer 4 which provides a path for storing control information of the CPUs 18 and 38 by operating according to the buffer control signals of the master / slave EPLDs 19 and 39 by the CPUs 18 and 38. (20,40) and master / slave EPLD by the CPU (18,38) A buffer 5 (21, 41) which operates according to the buffer control signal of (19, 39) to provide a path for storing the control information of the CPU (18, 38), and a master by the CPU (18, 38). Buffers 6 (22, 42) which operate in accordance with the buffer control signals of the slave EPLDs (19, 39) to provide a path for storing the control information of the CPU (18, 38); SRAM3 (23, 43) for storing control information of the CPU (18, 38) input through the buffer 6 (42, 22) in the counterpart ATM board, and the buffer 5 (21, 41) and the counterpart ATM board. It consists of DRAMs 24 and 44 which store control information of the CPUs 18 and 38 input through the buffers 6 and 42.

The operation of the redundancy apparatus of the ATM board in the control station of the IMT2000 system according to the present invention configured as described above is as follows.

First, when the system is powered on, one ATM board of the redundant first ATM board 10 and the second ATM board 30 has a master right and operates as a master. The board acts as a slave, ready for data communication over the cell bus.

If the first ATM board 10 operates as a master and the second ATM board 30 operates as a slave, the first ATM board 10 qubits 11 an ATM cell input through a cell bus. And then multiplexed through the mux 12 and stored in the SRAM 1 16 and the SRAM 2 17 through the buffer 1 13 and the buffer 2 14, respectively.

At this time, the buffer 1 13 and the buffer 2 14 operate according to the buffer control signal of the master / slave EPLD 19 by the CPU 18 and are outputted through the mux 12 and the qubit 11. The ATM cells are stored in the SRAM 1 16 and the SRAM 2 17, respectively, and the buffer 3 15 also operates in accordance with the buffer control signal of the master / slave EPLD 19 by the CPU 18. ) And the ATM cells output through the qubit 11 are stored in the SRAM1 36 and the SRAM2 37 in the second ATM board 30, respectively.

The master / slave EPLD 19 receives a control signal according to various control information for receiving and storing ATM cells output from the CPU 18 and controls the first ATM board 10 as a master. A buffer control signal is output to the buffer 1 13, the buffer 2 14, and the buffer 3 15 to control the operations of the buffers 1, 2, 3 (13, 14, 15).

As described above, since the buffer 3 (15) in the first ATM board 10 is connected to the SRAM 1 (36) and the SRAM 2 (37) in the second ATM board 30 and the SRAM 1 (16) in the first ATM board (10). ATM cells stored in SRAM2 17 are simultaneously stored in SRAM1 36 and SRAM2 37 in the second ATM board 30.

In addition, the master / slave EPLD 19 receives buffer control signals according to various control information for receiving and storing ATM cells output from the CPU 18. And the operation of the buffer 6 (22).

That is, the buffer 4 (20) and the buffer 5 (21) operate according to the buffer control signal of the master / slave EPLD 19 by the CPU 18 to control the control information of the CPU 18 to the SRAM3 (23). And the buffer 6 22 are also stored in the DRAM 24 and operate in accordance with the buffer control signal of the master / slave EPLD 19 by the CPU 18 to transfer the control information of the CPU 18 to the second ATM. It is stored in the SRAM3 43 and the DRAM 44 in the board 30, respectively.

Even in this case, since the buffer 6 22 in the first ATM board 10 is connected to the SRAM 3 43 and the DRAM 44 in the second ATM board 30, the SRAM 3 23 in the first ATM board 10 The control information of the CPU 18 stored in the DRAM 24 is simultaneously stored in the SRAM3 43 and the DRAM 44 in the second ATM board 30.

As described above, in the present invention, the first ATM board exclusively controls the buffer control signals for the buffers 1 to 6 (13, 14, 15, 20, 21, 22) in the first ATM board 10 operating as the master. SRAM 1, 2, 3 (16, 17, 23) and DRAM 24 in (10) as well as SRAM 1, 2, 3 (36, 37, 43) and DRAM in second ATM board 30 acting as a slave The control information of the ATM cell and the CPU 18 is stored in the 44, and thus, a problem occurs in the second ATM board 30 operating as a slave, so that the master right is transferred from the first ATM board 10 to the second. Even when the ATM board 30 is changed, only the authority to control the operation of the buffers 1 to 6 (33, 34, 35, 40, 41, 42) in the second ATM board 30 is controlled by the first ATM board. The data and information stored in the SRAMs 1, 2, 3 (16, 36), (17, 37), (23, 43) and the DRAMs (24, 44) are changed from (10) to the second ATM board (30). As it is, it will continue to be stable.

As described above, the present invention, by implementing the ATM boards configured in the control station of the IMT2000 system in redundancy, not only can the system be stably maintained, but also the high-quality service can be continuously and stably maintained. There is an effect that can be easily applied.

Claims (1)

The ATM board, which consists of redundancy in the control station of the IMT2000 system, includes a qubit for receiving ATM cells input through a cell bus, a mux for multiplexing the ATM cells received in the qubit, and a master / slave EPLD by a CPU to be described later. Buffer 1 which provides a path for storing the ATM cells multiplexed in the MUX by operating according to the buffer control signal of the Mx and the buffer control signal of the master / slave EPLD by the CPU to be described below. A buffer for providing a path for storing ATM cells, and a path for storing ATM cells received in the qubit and multiplexed in mux by operating according to a buffer control signal of a master / slave EPLD by a CPU to be described later. SRAM1 for storing an ATM cell input through the buffer 3, the buffer 1 and the buffer 3 in the counterpart ATM board, and an input through the buffer 2 and the buffer 3 in the counter ATM board. SRAM2 for storing an ATM cell, a CPU for outputting a control signal according to various control information for receiving and storing an ATM cell, and operation control of the corresponding ATM board as a master or a slave according to the control signal output from the CPU And the master / slave EPLD controlling the operation of the buffers 1, 2, 3 and the buffers 4, 5, 6 to be described later, and the buffer control signal of the master / slave EPLD by the CPU. A buffer 4 for providing a path for storing control information, a buffer 5 for providing a path for storing control information of the CPU by operating in accordance with a buffer control signal of a master / slave EPLD by the CPU, and the CPU A buffer 6 which provides a path for storing control information of the CPU by operating according to a buffer control signal of a master / slave EPLD SRAM3, which stores the fish information, and DRAM, which stores the control information of the CPU input through the buffer 5 and the buffer 6 in the counterpart ATM board, the ATM board acting as a master is responsible for the operation of the master / slave EPLD. SRAM1,2,3 in ATM board acting as master by exclusively controlling buffer control signals for buffers 1,2,3,4,5,6, SRAM1,2,3 in ATM board acting as DRAM and slave , At the same time storing data and information in the DRAM, and in this state, when the master right is changed to an ATM board acting as a slave, the buffers 1, 2, 3, 4, 5, and 6 in the ATM board acting as a slave are operated. Only the authority to control the system can be changed, and the data and information stored in the SRAMs 1, 2, and DRAM remain intact, so that the service can be continuously and stably maintained. Dual of mode board Device.