KR20010046738A - A branch prediction method using address trace - Google Patents

Abstract

PURPOSE: A branch prediction method using an address trace is provided to reduce the size of a chip and the production cost by reducing the time for an address decoding, and by accurately predicting a branch with a small quantity of trace cache. CONSTITUTION: An address trace cache(220) is composed of a start address which stores an address in which each routine is started, an end address which represents an address in which each routine is ended, a current access loop counter which counts the number of current access of a relevant routine and an old access loop counter which counts the number of whole access of the routine.

Description

Branch prediction method using address trace {A BRANCH PREDICTION METHOD USING ADDRESS TRACE}

The present invention relates to a branch prediction method, and more particularly, to a branch prediction method using an address trace.

1 is a diagram for illustrating a microgeneration of a fourth generation. The figure refers to FIG. 1 of the article "Trace Processors: Moving to Fourth-Generation Microarchitectures" published by IEEE E. Smith and Sriram Vajapeyam in September 1997, IEEE Computer, pp. 68-74. Referring to the drawings, (a) is a serial processor, a first generation microarchitecture applied to the first digital computer in the 1940s and used until the early 1960s. This serial processor fetches and executes each instruction before the next execution. The second generation microarchitecture using the pipeline shown in FIG. 1B was used as a standard for high performance processes until the end of the 1980s. The third and fourth generation microarchitectures shown in FIGS. 1C and 1D are characterized by using super scalar processors. They began to appear first in commercially available processors in the late 1980s. As shown in FIG. 1, the next generation of high performance processors will use multiple superscalar pipelines with a higher level of control, sending instruction groups into individual superscalar pipelines. A superscalar processor that simultaneously fetches multiple instructions into a cache block and parallelizes the instructions suffers from performance degradation caused by pipeline stalls and invalidation of invalid instructions rather than by prediction errors. do. Therefore, accurate branch prediction is more important for superscalar processors.

As mentioned earlier, the key to high performance superscalar processors is to optimize the use of the pipeline, where the most important design element is how to control the branch. Several techniques can be used to predict whether a branch will occur, the most common of which is bimodal branch prediction. Recently, however, more branch history has been used to show more accurate predictions, one of which is local branch prediction, which takes into account each branch history independently and takes advantage of repetitive patterns. branch prediction). And another method is a global branch prediction method that uses a combined history of all recent branches in prediction. Each of these branch prediction methods has unique advantages. For example, the bifurcation branch prediction method is suitable when each branch is strongly biased in a specific direction, and the local branch prediction method is suitable for branches of simple repetitive patterns. The global branch prediction method has a particularly good characteristic when the direction executed by the sequentially executed branches has a high correlation. The methods of branch prediction as described earlier are introduced by Scott McFarling in June 1993 in the article "Combining Branch Predictors" on pages 1-19 of the WRL Technical Note TN-36. Here, WRL (Western Research Laboratory) is a computer system research organization established by Digital Equipment Corporation in 1982. In addition to the branch prediction method described above, there is a combined branch prediction method combining a local branch prediction method and a global branch prediction method.

The branch predictor using the above method predicts the condition check result of the branch instruction by using the result of the previous branch instruction before the result of the condition check process when the branch instruction is encountered. The central processing unit (CPU) fetches and executes the following instruction according to the predicted condition check result. As a result, by adopting a pipelined scheme, it is possible to eliminate pipeline stalls that degrade performance in recent CPUs that require fast instruction fetches. However, if the result of branch prediction is wrong, the instruction that is already fetched and executed must be stopped and the actual next instruction must be fetched. Incorrect prediction causes the pipeline to stop until it is refilled with appropriate instructions. This is called the mispredicted branch penalty.

Processors with a five-stage pipeline usually have a branching penalty of two cycles, so a four-way superscalar design, for example, loses eight instructions. As the pipeline expands, the branch penalty increases as the loss of more instructions occurs. In general, because programs branch every 4-6 instructions, incorrect branch prediction results in severe performance degradation in high superscalar or deep pipeline designs.

Many efforts have been made to reduce such branch penalties, and recently, a trace processor using a trace cache has been used. Such trace processors are disclosed in the article "Trace Processors: Moving to Fourth-Generation Microarchitectures" published by James E. Smith and Sriram Vajapeyam.

FIG. 2A illustrates a dynamic sequence of basic blocks stored in a general instruction cache 21, and FIG. 2B illustrates a general trace cache 22. Referring to FIG. 2A, the arrows shown in the figure indicate 'taken' branches (when jumping to a branch target address). In the instruction cache 21, because instructions are stored in discrete cache locations, even multiple branch predictions that occur every cycle require four cycles to fetch instructions within the basic blocks 'ABCDE'.

For this reason, some researchers have proposed specific instruction caches for capturing long, dynamic instruction sequences. Such a cache has each line storing a snapshot or trace of a dynamic instruction stream, as shown in FIG. 2B. Therefore, the cache having such a structure is referred to as the trace cache 22. The trace cache 22 is described in the article "Expansion Caches for Superscalar Processors" in J. Johnson, June 1994, in Technical Report CSL-TR-94-630, Computer Science Laboratory, Stanford Univ .; U. S. Pat. Acquired by A. Peleg and U. Weiser in January 1995. No. 5,381,533, "Dynamic flow instruction cache memory organized around trace segments independant of virtual address line"; And in December 1996 by E. Rotenberg, S. Bennett and J. Smith. 29th Int'l Symp. Each of the articles, "Trace cache: A Low Latency Approach to High Bandwidth Instruction Fetching," on pages 24-34 of the microarchitecture.

In addition, the trace cache 22 was prepared in June 1998 by Sanjay Jeram Patel, Marius Evers and Yale N. Patt. 25th Inter'l Symp. "Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing", published on pages 262-271 of Computer Architecture; February 1999 by Sanjay Jeram Patel, Daniel Holmes Friendly and Yale N. Patt, IEEE TRANSACTIONS ON COMPUTER, VOL. 48, "Evaluation of Design Options for the Trace Cache Fetch Mechanism," published on pages 193-204 of NO.2; And in IEEE 1999, by Eric Rotenberg, Steve Bennett, and James E. Smith, IEEE TRANSACTIONS ON COMPUTER, VOL. 48, No. 2, pages 111-120, "A Trace Cache Microarchitecture and Evaluation."

As described above, the same dynamic sequence as the blocks appearing discontinuously in the instruction cache 21 shown in FIG. 2A is represented continuously in the trace cache 22 shown in FIG. 2B. Thus, as in the conventional branch prediction method, the instructions stored in the trace cache 22 may be sequentially executed without performing a repetitive branching to an instructioned address according to a programmed routine. Thus, not only the branch penalty incurred by the conventional branch prediction method can be prevented, but also the advanced parallel processing can be performed by continuously storing the instructions stored in the discontinuous positions of the instruction cache 21 in the trace cache 22. Can be done.

However, since the trace cache 22 stores the instruction itself, a decoding process to an address corresponding to the instruction is necessary. In addition, the trace cache 22 as described above has a disadvantage in that the cache size becomes too large because even repeatedly executed instructions are repeatedly stored in the order of execution. Therefore, in order for the trace cache 22 storing the instructions to be large enough to store all the instructions in the above manner, a problem arises in that the chip size and the production cost increase. Accordingly, there is a need for a branch prediction method that can reduce the address decoding time of the trace cache 22 and can reduce the chip size and production cost by using an appropriate amount of cache capacity.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems. In the branch prediction method using the trace cache, the address decoding time can be reduced, and the accurate branch prediction is performed with a small amount of the trace cache. It is to provide a branch prediction method that can reduce chip size and production cost.

1 is a diagram to illustrate a fourth generation microarchitecture;

2A is a diagram for showing a dynamic sequence of basic blocks stored in a general instruction cache;

2B is a diagram for showing a typical trace cache;

3 is a diagram to show an example of a repeating command pattern;

4 is a view for showing a pattern in which the instructions shown in FIG. 3 are stored in a trace cache according to the prior art;

5 is a diagram showing the configuration of an address trace cache according to the present invention; And

6 is a view for showing a pattern stored in the trace cache according to the present invention the instructions shown in FIG.

* Description of the symbols for the main parts of the drawings *

22: trace cache 220: address trace cache

According to a feature of the present invention for achieving the object of the present invention as described above, the branch prediction method using a trace cache, according to the order of instructions to be executed when a routine consisting of instructions that are not repeated is executed. Storing an address corresponding to an instruction in the trace cache, and when the routine consisting of repeated instructions is executed, an address at which the routine starts, an address at which the routine ends, and a current number of accesses of the routine and the Counting and storing the total number of accesses of the routine.

The trace cache includes loop counters for counting the current number of accesses of the routine and the total number of accesses of the routine when the routine of repeated instructions is executed.

The branch prediction method includes comparing coefficients counted by the loop counters and addressing a start address of a routine to be executed after the routine when the two coefficients are equal to each other. And reconfiguring the loop counter when false branch prediction occurs, wherein the loop counter uses the most recently updated loop count.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6.

The novel trace cache of the present invention stores the address traces corresponding to the instructions in a decoded form, thereby reducing the address decoding time for each instruction. In addition, since a small amount of trace cache is used when storing address traces for routines that are repeatedly performed, chip size and production cost can be reduced.

3 is a diagram illustrating an example of a repeated command pattern.

First, referring to the routine 1 shown in Fig. 3, operations A and B are repeatedly performed 30 times. When the execution of the routine ① is finished, the routine ② is executed. In the routine ②, the operations C, D and E are sequentially performed 20 times. When the execution of the routine ② is finished, the routine ③ in which the operations F and G are repeatedly performed 40 times is performed.

For example, assuming that routines as shown in FIG. 3 are performed, the instructions stored in the trace cache 22 according to the prior art are as in FIG. 4.

Referring to FIG. 4, the conventional trace cache 22 stores instructions in the order in which they are executed, regardless of whether the instructions being executed are executed repeatedly or not repeatedly. Accordingly, the trace cache 22 has a data storage area for storing 60 instructions (2 instructions x 30 repetitions = 60) for the routine ①, and 60 instructions (3 instructions x 20) for the routine ②. A data storage area for storing repetition = 60) and a data storage area for storing 80 instructions (2 instructions x 40 repetitions = 80) for the routine 3 are required. That is, in order to store the routines 1 to 3 shown in Fig. 3, a total of 200 data storage areas are required. In this case, if 32 bits are required to store each instruction, a total data storage area of 6,400 bits (ie, 800 Bytes) is required to store the routines 1 to 3.

5 is a diagram illustrating the configuration of the address trace cache 220 according to the present invention. The address trace cache 220 according to the present invention, as shown in FIG. An end address, a current access loop counter to count the current number of accesses of the routine, and an old access loop counter to indicate the total number of accesses of the routine. It is composed.

For example, when the execution information of the instructions performed in the routine ① shown in FIG. 5 is represented by the address trace cache 220 according to the present invention, the start address and the end address of the routine ① are first written to the trace cache 220. Stored. Subsequently, the current access loop counter stores the current access count of the routine ①, and the old access loop counter stores the total access count (for example, 30 times) of the routine ①. As the access of the routine ① is repeated, the value of the current access loop counter is increased. If the value of the current access loop counter is equal to the value of the old access loop counter, the execution of the routine ① is terminated, and the start of the routine ② is started. The address is stored as an next fetch point (NFP).

As shown in FIGS. 3 and 5, the routines 1 to 3 may be stored in the address trace cache 220 by the method described above. However, in the case of routines that are not repeatedly executed, such as the routines 1 to 3, addresses for each of the instructions constituting the routine are sequentially written. If the wrong branch prediction occurs, the loop counter is reconfigured, and the most recently updated loop count is used.

FIG. 6 is a diagram illustrating a pattern in which the instructions illustrated in FIG. 3 are stored in the address trace cache 220 according to the present invention.

Referring to FIG. 6, for example, when the routine ① shown in FIG. 3 is stored in the address trace cache 220 according to the present invention, the address of the instruction A that is executed first is stored as the start address of the routine ①. , The address of the instruction B executed last is stored as the end address of the routine ①. In the case of the routine ①, since the total number of repetitions is 30, the old access loop counter is stored as 30. Each time the routine ① is repeatedly executed, the current access loop counter value is increased by one. In the same manner, information about the routine ② and the routine ③ is stored in the address cache 220, respectively.

As shown in Fig. 6, the address cache 220 according to the present invention is composed of an address at which each routine starts, an address at which each routine ends, a current access loop counter, and an old access loop counter. Only four data storage areas are required to store information about the routines being created. Therefore, a total of twelve data storage areas are required to store the routines 1 to 3 shown in FIG. 3 with the address trace cache 220 according to the present invention. In this case, if 32 bits are required to store each piece of information, a total of 384 bits (ie, 48 Bytes) are required to store the routines 1 to 3. This reduces the data storage area required by about 16.7 times compared to the conventional trace cache shown in FIG.

This effect is greater for routines that contain more repeating instructions, and for more repeating instructions. As such, since the address trace cache 220 according to the present invention uses a data storage area that is significantly reduced compared to the conventional trace cache, the chip size and the production cost can be reduced. In addition, the address trace cache 220 according to the present invention stores the address trace for each instruction in a decoded form, thereby reducing the address decoding time of the instruction.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, since the address trace itself corresponding to the instruction is stored in a decoded form, the address decoding time for each instruction can be reduced, and the chip cache and the production cost can be reduced because a small amount of trace cache is used. Can be.

Claims (4)

In a branch prediction method that uses a trace cache: When a routine consisting of instructions that are not repeated is executed, storing an address corresponding to each instruction in the trace cache according to the order of instructions to be executed; And, Counting and storing the address at which the routine starts, the address at which the routine ends, and the current number of accesses of the routine and the total number of accesses of the routine when the routine of repeated instructions is executed. A branch prediction method using an address trace. The method of claim 1, The trace cache, When the routine consisting of repeated instructions is executed, And loop counters for counting the current number of accesses of the routine and the total number of accesses of the routine. The method of claim 2, The branch prediction method, Comparing coefficients counted by the loop counters to address the starting address of the routine to be executed after the routine when the two coefficients are equal to each other. The method of claim 2, The branch prediction method, Reconfiguring the loop counter when false branch prediction occurs, And wherein the loop counter uses the most recently updated loop count.