KR20010046347A - Redundancy circuit in semiconductor memory device having compatible repair cell array for multi-bank - Google Patents

Abstract

PURPOSE: A redundancy circuit of a semiconductor memory device where a number of banks share one repair cell array is provided to reduce layout area without a mis-operation. CONSTITUTION: A repair cell array comprises an array of a number of 4 cell units comprising four repair cells. Each 4 unit cell inputs or outputs data to/from the repair cell through direct data buses(DB0,DB1,DB2,DB3) in response to bank address signal(Yi_Bank0,Yi_Bank1,Yi_Bank2,Yi_Bank3) and repair row address signals(RWL0,RWL1,RWL2,RWL3) and column address signals(Yi0,Yi1,Yi2,Yi3) corresponding to each bank. The 4 unit cell comprises four repair cells and an input part controlling a path between the repair cell and the data bus. The repair cell includes a latch storing data and NMOS transistors connecting the latch with the data bus through a source-drain path connected serially each other.

Description

Redundancy circuit in semiconductor memory device having compatible repair cell array for multi-bank

The present invention relates to a semiconductor memory device, and more particularly, to a redundancy circuit in which a plurality of banks share a repair cell array by directly connecting a repair cell and a data bus.

In general, in order to solve a problem in which a chip does not operate normally when a defect occurs in some memory cells in a memory device, a spare memory cell is made in advance and a defective cell is spared after the test. The yield is increased by replacing the memory cells. In this case, the spare cell is called a spare cell or a repair cell, and a circuit intervening in such a replacement operation is called a redundancy circuit.

1 is a view showing the arrangement of a conventional repair cell and its control circuit.

Referring to FIG. 1, a memory is composed of four banks 101, 102, 103, and 104, and each of the banks 101, 102, 103, and 104 has a spare word line in addition to an existing memory cell array. a plurality of cell arrays (111, 112, 113) having a spare wordline, a spare row decoder (SPX) 130 and a spare column decoder (SPY) for controlling the spare wordline. Made of 150.

A conventional memory redundancy operation having the above configuration will be described.

In order to replace a bad memory cell after a test of the memory, when the address corresponding to the bad memory cell is applied, the spare decoder 130 and the spare column decoder 250 are enabled and the corresponding cell arrays 111, 112,. The repair cell of the spare word line existing in 113) is selected.

However, when the spare word lines are arranged in the cell arrays 111, 112, and 113 of the respective banks 101, 102, 103, and 104 as described above, the area occupies the entire memory as the memory capacity increases. This increased relatively.

2 is a view showing the arrangement of another conventional repair cell array and its control circuit.

Referring to FIG. 2, a memory is composed of four banks 201, 202, 203, and 204, and each of the banks 201, 202, 203, and 204 is composed of a plurality of cell arrays 211, 212, and 213. And a spare row decoder (SPX) 230 and a spare column decoder (SPY) 250 for controlling a repair cell that replaces a defective memory cell, each bank 201, The spare cell array 220 includes a plurality of spare word lines controlled by the spare decoder 230 and the spare column decoder 250 of 202, 203, and 204 to replace the defective memory cells of the bank. Is done.

Another conventional memory redundancy operation having the above configuration will be described.

In the conventional repair method of FIG. 1, a plurality of spare lines are disposed in the repair cell array 220 shared by the banks 201, 202, 203, and 204 to reduce the area of the defective memory cell of the bank. When the address is input, the spare decoder 230 and the spare column decoder 250 are enabled to perform a repair operation.

However, when two rows belonging to different banks are replaced by two spares of the same repair cell array, two spares sharing the same bit line open at the same time, thereby causing a malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a redundancy circuit of a semiconductor memory device in which a plurality of banks share one repair cell array to reduce an area without malfunction.

1 is a view showing an example of a conventional repair cell and its control circuit arrangement.

Figure 2 is another illustration of the arrangement of a conventional repair cell array and its control circuit.

3 is a circuit diagram of a repair cell array according to an embodiment of the present invention.

4 is a detailed circuit diagram of a four cell unit according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

310: 4-cell unit 400: input unit

410, 420, 430, 440: repair cell

RWL: Repair Low Address Signal

Yi_Bank: Bank Address Signal

Yi: Column address signal

The present invention for achieving the above object is a repair cell array comprising a plurality of repair cell unit for driving input and output in response to a repair address signal, a bank address signal and a column address signal in a redundancy circuit of a semiconductor memory device; And a data bus, wherein the repair cell unit directly inputs and outputs data to and from the data bus.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a circuit diagram of a repair cell array according to an embodiment of the present invention.

Referring to FIG. 3, the repair cell array is composed of an array of a plurality of four cell units 310 having four repair cells. Each four cell unit 310 has a bank address signal Yi_Bank0 corresponding to each bank. The data bus (DB0, DB1, DB2, DB3) directly in response to the Yi_Bank1, Yi_Bank2, Yi_Bank3) and repair address signals (RWL0, RWL1, RWL2, RWL3) and column address signals (Yi0, Yi1, Yi2, Yi3). The data is input or output through the repair cell.

4 is a detailed circuit diagram of a four cell unit 310 according to an embodiment of the present invention.

Referring to FIG. 4, the four cell unit 310 includes four repair cells 410, 420, 430, and 440, a repair address signal RWL, a bank address signal Yi_Bank, and a column address signal Yi. In response, the repair cell 410, 420, 430, 440 includes an input unit 400 that controls a path between the repair cell and the data bus.

The repair cell 410 receives the latch 411 for storing data and the output signal of the input unit 400 and the repair address signal RWL as inputs, respectively, through a source-drain path connected in series. NMOS transistors NM41 and NM42 connecting the latch 411 and the data bus DB0.

It looks at the operation of the present invention having the configuration as described above.

When the spare lines are different as shown in FIGS. 1 and 2, the bit lines are separated from each other, and the column access method of the repair cell array connects the bit lines and the data bus, rather than selecting a cell in which the row and column address match. The signal was used as a repair cell selection signal that must be matched with the row address and the column address.

In detail, each of the four cell units 310 includes four repair cells 410, 420, 430, and 440. In the repair cell, the repair address signal RWL is activated to latch the repair cells. When the bank address Yi_Bank and the column address Yi are enabled while the NMOS transistor NM42 connected to the 411 is turned on, an output signal of the input unit 400 is activated to turn on the NMOS transistor NM41. The latch 411 which is a data storage means of the repair cell is connected to the data bus DB0.

That is, as described above, the repair cell for storing data and the data bus are connected without passing through the bit line, so that a plurality of banks may share and use one repair cell array. Here, the repair time can be reduced by not passing through the bit line.

Meanwhile, the cross-coupled draw, which is a data storage means of the repair cells 410, 420, 430, and 440, may be implemented as a capacitor.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a plurality of banks share one repair cell array, thereby reducing the area of the repair cell array, thereby reducing the yield and repair time of the memory and reducing the production cost.

Claims (5)

In the redundancy circuit of a semiconductor memory device, A repair cell array including a plurality of repair cell units for driving input and output in response to a repair low address signal, a bank address signal, and a column address signal; With a data bus, A redundancy circuit of a semiconductor memory device in which the repair cell unit directly inputs and outputs data to and from the data bus. The method of claim 1, The repair cell unit, Multiple repair cells; And An input unit for controlling a path between the repair cell and the data bus in response to the repair address signal, the bank address signal, and the column address signal Redundancy circuit of a semiconductor memory device, characterized in that it comprises. The method of claim 2, The repair cell, Storage means for storing data; And A first NMOS transistor and a second NMOS transistor configured to receive the output signal and the repair address signal of the input unit through a gate, respectively, and connect the storage means and the data bus through a source-drain path connected in series; Redundancy circuit of a semiconductor memory device, characterized in that it comprises. The method of claim 3, And said storage means comprises a cross-coupled latch. The method of claim 3, The storage means is a redundancy circuit of a semiconductor memory device, characterized in that consisting of a capacitor.