KR20010046145A - Method and apparatus for controlling bit rate of a MPEG decoder - Google Patents

Abstract

PURPOSE: An apparatus and method for controlling a bit rate of a moving image coder are provided to convert an inputted variable while a bit rate adjusting device used in a moving picture coder is operated and to monitor variables and a result value used while a bit rate adjustment is performed. CONSTITUTION: A bit rate control unit comprises a control signal generating unit(20), a DPRAM(Dual Port RAM)(30) and a digital signal processing unit(40). That is, the bit rate control unit comprises a portion generating a control signal for reading/writing to the DPRAM(30), a memory portion for making two ports read/write independently and a portion for adjusting a substantial bit rate. The control signal generating unit(20) comprises an interrupt generating unit(21) and an address decoder(22). The interrupt generating unit(21) generates an interrupt signal used as an input of the digital signal processing unit(40). The bit rate control unit is operated by being synchronized with an interrupt signal being generated from the interrupt generating unit(21). Data which are downloaded in the DPRAM(30) are read through another port of the DPRAM(30) and output to the digital signal processing unit(40) for performing a calculation for a substantial bit rate adjustment.

Description

Bit rate controller and method for video encoder {Method and apparatus for controlling bit rate of a MPEG decoder}

The present invention relates to an apparatus and method for controlling a bit rate of a video encoder, and in particular, to enable the conversion of input variables during operation of a bit rate adjuster used in a video encoder, and the variables and result values used in the process of performing bit rate adjustment. An apparatus for controlling a bit rate of a video encoder and a method thereof are provided.

In general, the video encoder reduces the correlation existing between the temporally separated images in order to increase the encoding efficiency of the input image, and encodes and transmits only the difference images. In this process, the image is divided into I, P, and B pictures.

In the MPEG-2 coder, the picture type of the input frame is determined according to the GOP structure determined in consideration of encoding efficiency, and the frames are rearranged and encoded according to the type, rather than the frames being inputted in order of encoding.

Picture types used in MPEFG encoding are classified into three types, i-picture (Inyra-Picture), P-picture (Predictive Picture), and B-picture (Bidirectionally Predictive Picture).

An I-picture is a frame encoded by the intra-frame encoding method, and does not need information about other adjacent frames when encoding / decoding. A P-picture is a frame encoded by the predictive encoding method. Predicted / decoded frames from frames.

The B picture is a frame encoded by a bidirectional predictive encoding method and requires both an I or P-type frame located temporally and an I or P-frame located later for encoding / decoding.

In a typical video encoder, the compressed video bitstream is stored in the video output buffer and finally transmitted. If the input transmission speed is longer than the output transmission speed of the video output buffer, the overflow occurs because the video output buffer becomes full. In order to prevent this from happening, the quantization process of video encoding should be performed more strictly to lower the transmission speed of the video output buffer.

Similarly, if the video output buffer is empty, the quantization process should be further relaxed to maintain the average output transfer rate. This series of processes is called bit rate control, which is essential for video coding and is an important factor that greatly affects image quality.

The purpose of the bit rate control of such a video encoder is to prevent overflow or underflow of a video output buffer as described above, and to obtain the best image quality in the process of encoding an Asian image. to be.

The quality of the image compressed and reconstructed through the video encoding process is lower than that of the original image, which is inevitable in the compression process.

In order to minimize the deterioration of the image quality and obtain the best image quality, the degree of deterioration of the quality of the compressed and reconstructed pictures, that is, the PSNR should be equal among the pictures. If the PSNRs of the pictures are not even for each picture and some pictures are high and some pictures are low, the average picture quality felt by a person is reduced to the picture quality of a picture encoded with a low PSNR.

On the other hand, in video encoders such as MPEG, there are three types of pictures according to temporal compression methods, i-pictures without using temporal compression methods, P-pictures using correlations from temporally preceding pictures, and temporal backwards and forwards. There is a B picture that uses correlation from a picture. Since these three picture types have different compression efficiencies, the amount of bits required to obtain the same image quality deterioration is different. Accordingly, the bit amount allocation for each picture is inevitably different, and depending on how the bit amount is allocated, the picture quality degradation may be equal or different according to each picture type.

Hereinafter, a bit rate controller and a method of a general video encoder will be described.

FIG. 1 is a block diagram illustrating a video encoder having a bit rate controller of a quantizer according to the related art. Referring to FIG. 1, a subtractor 10, a DCT unit 11, and a quantizer are shown. (12), a variable length coding unit 13, a bit rate control unit 14, an inverse quantization unit 15, an inverse DCT unit 16, and a motion estimation and compensation unit 17.

The motion estimation and compensation unit 17 extracts a motion vector by performing motion estimation using the previous image for input image data and prediction, and uses the extracted motion vector to extract a macro block (16 × 16) of the input image to be processed. After obtaining the predicted value of) from the reference image of the previous frame, the obtained predicted block is output to the subtractor 10.

The subtractor 10 subtracts the predicted block and the input image block output from the motion estimation and compensation unit 17, and transfers the difference value to a discrete cosine transform (DCT) 11.

The DCT unit 11 DCT-converts the difference value transmitted from the subtractor 10 and then outputs the DCT-converted data transferred from the DCT unit 11 to the quantization unit 12. The result is quantized and output to the variable length coding unit (VLC) 13 and the inverse quantization unit 15, respectively.

The variable length encoder 13 variably encodes the quantized image data and transmits the quantized image data to the receiving end and the bit rate controller 14 as a bit string, and the inverse quantization unit 15 quantizes the image data in the quantization unit 12. Inverse quantized and delivered to the inverse DCT unit 16.

After the inverse DCT unit 16 inverses DCT-converts the dequantized image data, the inverse DCT-converted image data is added to the predicted block obtained by the motion estimation and compensation unit 17, and the resulting image block is It is stored as a reference image of a frame and used for motion estimation and motion compensation of the next image block.

The bit rate control unit 14 checks the buffer state in the variable length encoder 13 to control the output of the quantization unit 12.

The operation of the video encoder according to the prior art having such a configuration will be described briefly.

First, when moving picture data is input, it is input to the DCT 11 to perform spatial frequency analysis using a transform. As a result, a result value called a DCT coefficient is output. The DCT coefficient is input to the quantization unit 12 and divided by a constant which is a function of two-dimensional frequency. The low frequency coefficient is divided into small numbers, and the high frequency coefficient is divided into large numbers. Bits of less significance are either discarded or truncated.

The output of the quantization unit 12 is input to the variable length encoder 13 to perform compression using statistical information to output the finally compressed bit amount to the bit rate control unit 14.

The bit rate controller 14 stores the amount of bits output from the variable length encoder 13 in a video output buffer and outputs them at an appropriate time, and quantizes the quantization unit 12 according to the method of controlling the fullness and bit rate of the video output buffer. To adjust the coefficients.

On the other hand, since moving image data has temporal redundancy, compression can be performed by transmitting only differences between screens. The DCT unit 11 restores the spatially coded data through the quantization unit 12 to the same state as the original input data through the inverse quantization unit 15 and the inverse DCT unit 16. In this case, the recovered data may not be exactly the same as the original data due to the nature of quantization.

The reconstructed data is temporally encoded by the motion estimation and compensation unit 17, and the motion compensated data is transferred to the subtractor 10 to be subtracted from the original image, and the subtracted image data is transferred to the DCT unit 11. The spatial encoding is input again.

Here, a method of adjusting the quantization coefficient of the quantization unit 12 by controlling the bit rate in the bit rate control unit 14 will be described.

First, the conventional bit rate control method is largely composed of two steps. In the first step, the amount of bits to be generated in the picture is pre-allocated before coding for each picture.In the second step, the quantization level is determined by comparing the amount of bits allocated to the picture with the amount of bits currently generated. It is.

In the first bit allocation method, the bit quantity is allocated to adjust the amount of bits generated before the gig picture is encoded. In this case, the element used is the picture complexity of the previously encoded pictures, the GOP in the GOP. The amount of bits remaining and the number of pictures of the remaining I, P, and B pictures in the GOP.

In order to obtain the allocation bit amount of each picture, the picture complexity is first calculated. In this case, the picture complexity is calculated using Equation 1 below.

Here, X _i , X _P and X _b are picture complexity of I picture, P picture and B picture, and S _i , S _p and S _b are bit generation amounts of the last coded picture according to picture type, and Q _i , Q _p and Q _b are average values of quantization coefficients of all macroblocks of the last coded picture according to the picture type.

In other words, each picture complexity can be obtained by multiplying an average value of the bit generation amount and the quantization coefficient of each last encoded picture.

In addition, the calculation of the bit amount allocated according to each picture is shown in Equation 2 below.

_{Here, T i, T p, T} b, is the amount of bits allocated to each picture type, R is the amount of the remaining bits used for encoding from among the bit amount allocated to the stack of units of a certain picture GOP, N _i , N _p , N _b are the number of I pictures, P pictures, and B pictures that are not yet encoded in the GOP.

That is, the amount of bits allocated to each picture is obtained by using the correlation between the picture complexity according to each picture type, the amount of bits remaining in the GOP, and the number of pictures remaining in the GOP.

Such a bit rate control apparatus according to the prior art receives a plurality of variables required for bit rate adjustment, and it is inconvenient to change the input variables during the bit rate adjustment process in the bit rate adjustment device, and it is difficult to monitor the operating variables. There is an impossible problem.

Accordingly, the present invention has been made to solve the above-described problems according to the prior art, an object of the present invention is to enable the conversion of the input variables during the operation of the bit rate adjuster used in the video encoder, the process of performing the bit rate adjustment The present invention provides a bit rate controller of a video encoder to monitor variables and result values used in the.

In addition, another object of the present invention is to provide a bit rate control method corresponding to the operation of the bit rate controller.

A feature of a bit rate controller of a video encoder according to the present invention for achieving the above object is a bit rate controller of a video encoder having a variable length encoder, the interrupt signal according to the sync signal provided by the variable length encoder; An interrupt generator that generates; A DPRAM for storing a plurality of input variables provided by the variable length encoder according to the provided control signal; a) operates in synchronization with the interrupt signal provided from the interrupt generator, and reads the corresponding variables stored in the DPRAM to perform GOP processing operations, operations required for the picture level, and operations required for the macro block level After performing sequentially, the result value is written to the DPRAM, and b) a bit rate adjustment unit reads data from the DPRAM at every GOP start point and updates the bit rate.

In addition, a feature of a method for controlling a bit rate of a video encoder according to the present invention is a method for controlling a bit rate of a video encoder having a variable length encoder, a VBV buffer, and a DPRAM, the micro signal according to a control signal provided from the variable length encoder. Downloading the code; When the microcode is downloaded, initializing each of the input variables, and determining whether a GOP start signal is generated; Judging whether the GOP start signal is generated, informing the start point of the variable length encoder to generate a VBV buffer reset signal for synchronization, and then determining whether the GOP signal is generated again; When the GOP signal is generated again, the operation corresponding to the GOP is performed according to the generated GOP start signal.When the GOP operation is completed, the operation necessary for the picture level and the operation required for the macro block level are sequentially performed whenever the macro block start signal occurs. Writing the result of the calculation to the DPRAM by performing the operation; Reading an operation result value written to the DPRAM and updating an input variable at every GOP start point; When the picture-and-signal is generated, after performing the operation required for the picture-and, it waits until the next interrupt signal is generated, and when the next interrupt signal is generated, the process is repeatedly performed.

1 is a block diagram showing a bit rate adjusting apparatus of a general video encoder;

2 is a view illustrating a signal flow of a bit rate controller in a video encoder according to the present invention;

3 is a block diagram illustrating a detailed block configuration of an apparatus for controlling a bit rate of a video encoder according to the present invention;

4 is an interrupt generation timing diagram generated by the interrupt generator shown in FIG. 3;

5 is a view illustrating a time allocation form for a control signal generated in the address decoder shown in FIG. 3;

6 is a flowchart illustrating an operation of a method of controlling a bit rate of a video encoder according to the present invention;

<Explanation of symbols for main parts of drawing>

13 variable-length encoding unit 14 bit rate control unit

20: control signal generator 21: interrupt generator

22: address decoder 30: DPRAM

40: digital signal processing unit

Hereinafter, a preferred embodiment of an apparatus and method for controlling a bit rate of a video encoder according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a signal flow of a bit rate controller in a video encoder according to the present invention, and FIG. 3 is a diagram showing a detailed block configuration of a bit rate control apparatus of a video encoder according to the present invention.

First, the bit rate controller 14 shown in FIG. 2 is a part of a video encoder, and an input signal and an output signal required for the operation are made through the variable length encoder 13.

The variable length encoder 13 stores data coded into a VBV (Video Buffer Verifier) buffer (not shown) as a part that codes the DCT transformed image coefficients by the DCT unit 11 shown in FIG. 1. . The state of the VBV buffer is input to the bit rate controller 14, and using this value, the bit rate controller 14 determines the quant_scale value. The quant_scale value is data necessary for determining a quantization level when quantizing image data with values from 1 to 31.

As shown in FIG. 2, the sync signal provided from the variable length encoder 13 to the bit rate controller 14 is a signal for synchronizing the synchronization between the variable length encoder 13 and the bit rate controller 14. It consists of four signals: a low GOP start, a picture start, a slice start, and a macroblock start. The mbparm signal provided from the variable length encoder 13 to the bit rate control unit 14 is used to obtain every picture information.

The number of bits coded by the variable length encoder 13 is input by being divided into a picture header and a macro block. The VBV buffer state is always input to the bit rate controller 14, and is used whenever the bit rate controller 14 is needed.

A qscale value, which is a value for determining the quantization level of the quantization unit 12 shown in FIG. 1, which is the final purpose of the bit rate control unit 14, is outputted to the variable length encoder 13 for each macro block, and a null stuffing value and a vbv delay value. Is also output.

The null stuffing value is a value required by the variable length encoder 13 to fill up a value of "0" to prevent the depletion of the buffer when data is small at the picture level, and the vbv delay value is used by the variable length encoder 13. Value to be inserted into the bitstream at the picture level. This value tells the decoder when to decode.

In addition, the tmsparm signal provided from the bit rate control unit 14 to the variable length coding unit 13 is data necessary for monitoring a variable used in the bit rate control unit 14.

Hereinafter, a detailed configuration of the bit rate controller 14 shown in FIG. 2 will be described with reference to FIG. 3.

First, the bit rate controller 14 includes a control signal generator 20, a dual port RAM (DPRAM) 30, and a digital signal processor (DSP) 40. That is, a portion that maintains input variables and generates a control signal for reading / writing to the DPRAM 30, and a portion in which two ports independently read / write and adjust the actual bit rate Separated by.

The control signal generator 20 is composed of an interrupt generator 21 and an address decoder 22. The interrupt generator 21 generates an interrupt signal used as an input of the digital signal processor 40.

The interrupt signal will be described in detail with reference to FIG. 4. 4 is a diagram illustrating an interrupt generation timing generated by the interrupt generator illustrated in FIG. 3.

The bit rate control unit 14 operates in synchronization with an interrupt signal generated by the interrupt generator 21, and this interrupt signal is generated from a synchronization signal sync input from the variable length encoder 13. As a result, the bit rate control unit 14 operates in synchronization with the input sync signal.

The sync [0] signal input from the variable length encoder 13 indicates the start of a macro block, the sync [2] indicates the start of a picture, and the sync [3] signal indicates the start of a gop.

In addition, the pict end signal is a signal indicating the end of an active picture, and the variable length encoder 13 indicates the end of actual picture data coding.

The priority of the interrupt processing in the digital signal processor 14 is int0, int1, int2, and int3, and the operation of the bit rate controller 14 is in the order of GOP, picture, macroblock, and picture end. It works.

In addition, the address decoder 22 shown in FIG. 2 generates a control signal of the DPRAM 30, and this control signal is made independent of the operation of the digital signal processor 40. FIG.

The time allocation for the control signal of the address decoder 22 is shown in detail in FIG. FIG. 5 is a diagram illustrating a time allocation form for a control signal generated in the address decoder shown in FIG. 3.

That is, one picture section is divided into an active section in which actual data is coded and an uncoded inactive section. Since each macro block is repeated at 128 clocks in the active section, it is divided into an active download section for writing data to the DPRAM 30 and an active upload section for reading data from the DPRAM 30. . The r / w, / oe, and / addr signals of the DPRAM 30 are determined according to this section.

The data downloaded / uploaded in this section are picture size, macro block size, VBV buffer status, picture type, and quantization level determination data (qscale).

This structure operates repeatedly for 128 cycles during the active period.

The inactive section starts as a picture end signal and only downloads / uploads once during the first 128 cycles. Like the active section, 128 cycles are allocated to the inactive download section and the rest are allocated to the inactive upload section. Variables uploaded / downloaded in this section are N / M value, frame rate, bit rate, VBV buffer size, picture struct, reset vbv, vbv delay, null stuffing, bit rate control (14) Internal parameters. Here, M denotes a period in which the IP-picture type appears and N denotes a period in which the I-picture type appears.

Each variable shown in FIG. 3 is loaded onto the data bus of the DPRAM 30 in accordance with the time allocation described above. The data downloaded to the DPRAM 30 are read by the digital signal processor 40 which independently reads through another port of the DPRAM 30 and performs calculations to perform actual bit rate adjustment.

Data uploaded from the DPRAM 30 is loaded on the tmsparm and transferred to the variable length encoder 13. This data is data used for monitoring the variables and result values used in the bit rate control unit 14.

Hereinafter, a method of controlling a bit rate of a video encoder according to the present invention will be described step by step with reference to FIG. 6.

FIG. 6 is a flowchart illustrating a method of controlling a bit rate of a video encoder according to the present invention, and illustrates a bit rate adjusting method processed by the digital signal processor 40 shown in FIG. 3.

First, the digital signal processor 40 is initialized by receiving the reset signal from the variable length encoder 13 (S101).

Then, after the initialization is completed, the micro code is downloaded (S102). That is, the micro code download is performed through the serial port of the digital signal processor 40 through the ssiclk, ssid, and ssisync signals in the variable length encoder 13.

Subsequently, after the microcode is downloaded, each variable is initialized (S103).

Subsequently, when initialization of each variable is performed, it is determined whether a GOP start signal is generated (S104), and when a GOP start signal is generated, after generating a VBV reset signal (resetvbv) signal (S106), the GOP again. Waiting for the signal.

Here, the VBV reset signal is a signal for synchronizing by instructing the start point in the variable length encoder 13.

Subsequently, when the next GOP start signal is generated, after receiving the GOP start signal and performing the operation corresponding to the GOP (S107), the necessary operation required for the picture level is performed (S108) and the macro block start signal is generated each time. It is to perform the operation according to the level (S109). At this time, necessary variables are read from the DPRAM 30 independently through the other ports at that time, and the calculation results are also independently written to the DPRAM 30.

Subsequently, it is determined whether a picture end signal is generated, and when a picture end signal is generated, a required operation is performed at the end of the picture, and after the operation is completed, if the next interrupt is generated to wait for the next interrupt, the same process as described above is repeated. It will be performed as (S110).

The correction of each variable during operation is written to the DPRAM 30 via the variable length encoder 13, and the digital signal processor 40 reads and updates data from the DPRAM 30 at every GOP start point.

As described above, the apparatus and method for controlling a bit rate of a video encoder according to the present invention operate independently of the input variable by adjusting the input data variable on the basis of DPRAM and the rear end of adjusting the actual bit rate using these variables. It is easy to convert and has the advantage of monitoring the variables used in the actual bit rate regulator during the operation.

Claims (2)

In the bit rate control apparatus of a video encoder having a variable length encoder, An interrupt generator for generating an interrupt signal according to a sync signal provided from the variable length encoder; A DPRAM for storing a plurality of input variables provided by the variable length encoder according to the provided control signal; a) operates in synchronization with the interrupt signal provided from the interrupt generator, and reads the corresponding variables stored in the DPRAM to perform GOP processing operations, operations required for the picture level, and operations required for the macro block level After performing sequentially, the result value is written to the DPRAM, b) a bit rate controller of the video encoder, characterized in that the bit rate adjustment unit reads data from the DPRAM and updates the bit rate at every GOP starting point. In a bit rate control method of a video encoder having a variable length encoder, a VBV buffer, and a DPRAM, Downloading a micro code according to a control signal provided from the variable length encoder; When the microcode is downloaded, initializing each of the input variables, and determining whether a GOP start signal is generated; Judging whether the GOP start signal is generated, informing the start point of the variable length encoder to generate a VBV buffer reset signal for synchronization, and then determining whether the GOP signal is generated again; When the GOP signal is generated again, the operation corresponding to the GOP is performed according to the generated GOP start signal.When the GOP operation is completed, the operation necessary for the picture level and the operation required for the macro block level are sequentially performed whenever the macro block star signal is generated. Writing the result of the calculation to the DPRAM by performing the operation; Reading an operation result value written to the DPRAM and updating an input variable at every GOP start point; When the picture-and-signal is generated, after performing the operation required for the picture-and, it waits until the next interrupt signal is generated, and repeatedly performs the above process when the next interrupt signal is generated. Bit rate control method.