KR20010045427A - Method for forming capacitor bottom electrode of semiconductor device by using blanket etch and polishing - Google Patents
Method for forming capacitor bottom electrode of semiconductor device by using blanket etch and polishing Download PDFInfo
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- KR20010045427A KR20010045427A KR1019990048716A KR19990048716A KR20010045427A KR 20010045427 A KR20010045427 A KR 20010045427A KR 1019990048716 A KR1019990048716 A KR 1019990048716A KR 19990048716 A KR19990048716 A KR 19990048716A KR 20010045427 A KR20010045427 A KR 20010045427A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 캐패시터의 이너 스택형(inner stack type) 하부전극 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an inner stack type lower electrode of a capacitor.
첨부된 도면 도1a 및 도1b를 참조하여 종래 기술에 따른 캐패시터의 이너 스택형 하부전극 형성 방법을 설명한다.An inner stack type lower electrode forming method of a capacitor according to the prior art will be described with reference to FIGS. 1A and 1B.
도1a는 반도체 기판(10) 상에 형성된 실리콘 질화막(12) 및 층간절연막(11)을 선택적으로 식각하여 반도체 기판(10)을 노출시키는 콘택홀을 형성하고, 상기 콘택홀 내부에 폴리실리콘막(13) 및 확산방지 금속막(14)을 채워 플러그를 형성하고, 전체 구조 상에 하부전극 형성용 산화막(15)을 형성하고, 산화막(15)을 선택적으로 식각하여 상기 플러그와 연결되는 하부전극 영역을 정의한 다음, 전체 구조 상에 하부전극용 전도막(16)을 형성한 것을 보이고 있다. 상기 플러그를 폴리실리콘막만으로 형성하기도 한다.FIG. 1A illustrates a contact hole exposing the semiconductor substrate 10 by selectively etching the silicon nitride layer 12 and the interlayer insulating layer 11 formed on the semiconductor substrate 10, and forming a polysilicon layer inside the contact hole. 13) and the diffusion prevention metal film 14 to form a plug, and to form a lower electrode forming oxide film 15 on the entire structure, and selectively etching the oxide film 15 to the lower electrode region connected to the plug Next, it is shown that the lower electrode conductive film 16 was formed on the entire structure. The plug may be formed of only a polysilicon film.
도1b는 상기 산화막(15) 상의 전도막(16)을 제거하기 위한 전면식각을 실시한 상태를 보이는 단면도이다. 도1b에 도시한 바와 같이 산화막(15) 상에 전도막(16)이 잔류하지 않도록 하기 위하여 50 % 정도 과도식각을 실시하게 되는데, 이에 따라 하부전극 영역 내에 채워진 전도막(16)의 손실 즉, 리세스(recess)가 발생하여 캐패시터 전극의 전하저장용량을 감소시키는 문제점이 있다.FIG. 1B is a cross-sectional view showing a state where the entire surface etching is performed to remove the conductive film 16 on the oxide film 15. As shown in FIG. 1B, in order to prevent the conductive film 16 from remaining on the oxide film 15, excessive etching is performed by about 50%. Thus, the loss of the conductive film 16 filled in the lower electrode region, that is, There is a problem in that a recess occurs to reduce the charge storage capacity of the capacitor electrode.
이와 같은 전면식각으로 인한 전도막(16)의 손실에 의해 캐패시터의 전하저장용량이 감소되는 문제를 해결하기 위해 하부전극 형성용 전도막(16)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함) 공정으로 제거하는 방법을 적용한다. 그러나, 현재까지 상업화된 슬러리를 이용하는 경우는 연마속도가 130 Å/분 정도로 낮기 때문에 대략 3000 Å 두께의 하부전극용 전도막을 제거하는데 23분 이상의 시간이 소요된다. 이와 같은 장시간의 연마에 의해 연마후 잔류하는 전도막(16)의 균일도가 크게 악화되며, 이에 따라 캐패시터 특성이 불균일하게 나타나며 또한 소모재 사용량이 크게 증가되는 단점이 있다.In order to solve the problem that the charge storage capacity of the capacitor is reduced by the loss of the conductive film 16 due to the front surface etching, the lower electrode forming conductive film 16 is referred to as chemical mechanical polishing (CMP). ) The process of removal is applied. However, in the case of using commercially available slurries, it takes more than 23 minutes to remove the conductive film for the lower electrode having a thickness of approximately 3000 kPa because the polishing rate is as low as 130 kPa / min. The uniformity of the conductive film 16 remaining after polishing is greatly deteriorated by such a long polishing, and thus, there is a disadvantage in that the capacitor characteristics are uneven and the consumption of consumable materials is greatly increased.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 이너 스택형 캐패시터 하부전극 형성을 위한 과정에서 하부전극용 전도막의 과도식각에 따른 손실, CMP 공정에 의한 균일도 저하, 공정시간의 증가, 소모재 사용량 증가 등을 방지할 수 있는 반도체 소자의 캐패시터 하부전극 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is a loss due to the excessive etching of the conductive film for the lower electrode in the process for forming the bottom electrode of the inner stack type capacitor, the uniformity decrease by the CMP process, the increase of the process time, the consumption of consumables It is an object of the present invention to provide a method for forming a capacitor lower electrode of a semiconductor device capable of preventing an increase.
도1a 및 도1b는 종래 기술에 따른 캐패시터의 이너 스택형 하부전극 형성 공정 단면도,1A and 1B are cross-sectional views of an inner stacked lower electrode forming process of a capacitor according to the prior art;
도2a 내지 도2c는 본 발명의 제1 실시예에 따른 캐패시터 하부전극 형성 공정 단면도,2A to 2C are cross-sectional views of a capacitor lower electrode forming process according to a first embodiment of the present invention;
도3은 본 발명의 제2 실시예에 따른 캐패시터 하부전극 형성 공정 단면도.3 is a cross-sectional view of a capacitor lower electrode forming process according to a second embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
25: 산화막 26: 금속막25: oxide film 26: metal film
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 희생막을 형성하는 제1 단계; 상기 희생막을 선택적으로 식각하여 상기 희생막 내에 하부전극 영역을 정의하는 제2 단계; 상기 하부전극 영역을 채우기 위해 상기 제2 단계가 완료된 전체 구조 상에 전도막을 형성하는 제3 단계; 상기 전도막을 전면식각하되, 상기 전도막의 일부를 상기 희생막 상에 잔류시키는 제4 단계; 및 상기 희생막 표면이 노출될 때까지 상기 전도막을 연마하는 제5 단계를 포함하는 캐패시터 하부전극 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a sacrificial film on the semiconductor substrate; Selectively etching the sacrificial layer to define a lower electrode region in the sacrificial layer; A third step of forming a conductive film on the entire structure in which the second step is completed to fill the lower electrode region; Etching the conductive layer over the entire surface, and leaving a portion of the conductive layer on the sacrificial layer; And a fifth step of polishing the conductive layer until the surface of the sacrificial layer is exposed.
또한, 상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 형성된 층간절연막을 통하여 상기 반도체 기판과 연결되는 플러그 형성이 완료된 상기 반도체 기판 상부에 희생막을 형성하는 제1 단계; 상기 희생막을 선택적으로 식각하여 상기 플러그를 노출시키는 하부전극 영역을 정의하는 제2 단계; 상기 하부전극 영역을 채우기 위해 상기 제2 단계가 완료된 전체 구조 상에 전도막을 형성하는 제3 단계; 상기 전도막을 전면식각하되, 상기 전도막의 일부를 상기 희생막 상에 잔류시키는 제4 단계; 및 상기 희생막 표면이 노출될 때까지 상기 전도막을 연마하는 제5 단계를 포함하는 캐패시터 하부전극 형성 방법을 제공한다.In addition, the present invention for achieving the above object is a first step of forming a sacrificial layer on top of the semiconductor substrate is completed plug formation is connected to the semiconductor substrate through an interlayer insulating film formed on a semiconductor substrate; Selectively etching the sacrificial layer to define a lower electrode region exposing the plug; A third step of forming a conductive film on the entire structure in which the second step is completed to fill the lower electrode region; Etching the conductive layer over the entire surface, and leaving a portion of the conductive layer on the sacrificial layer; And a fifth step of polishing the conductive layer until the surface of the sacrificial layer is exposed.
본 발명은 이너 스택형 캐패시터 하부 전극 형성 공정에서 하부전극용 전도막 증착 후 전면식각 공정을 실시할 때 하부전극 영역 내에 채워진 전도막이 손실되는 리세스 현상의 발생을 방지할 수 있으며 증착된 하부전극용 전도막을 CMP 공정만으로 제거하는 경우 요구되는 과도한 연마 시간, 이로 인한 균일도 악화 및 소모재 비용 증가 문제를 해결하기 위해, 플러그를 형성한 후 캐패시터 형성용 희생막으로서 산화막을 형성하고, 산화막을 선택적으로 식각하여 플러그와 연결될 하부전극 영역을 정의한 다음, 하부전극용 전도막을 증착하고 전면식각을 실시하여 산화막 상에 하부전극용 전도막을 50 Å 내지 500 Å 정도 잔류시키고, 하부전극용 전도막의 리세스를 최소화할 수 있는 CMP 공정을 이용하여 산화막 상부에 잔류하는 하부전극용 전도막을 제거하는데 특징이 있다. 이러한 본 발명에 따라 캐패시터 하부전극용 전도막의 손실을 감소시킬 수 있고, 균일하면서도 충분한 캐패시터 전하저장용량을 확보할 수 있으며 소자특성을 향상시킬 수 있다.The present invention can prevent the occurrence of a recess phenomenon in which the conductive film filled in the lower electrode region is lost when the entire surface etching process is performed after depositing the conductive film for the lower electrode in the process of forming the inner stack type capacitor lower electrode. In order to solve the problem of excessive polishing time required due to the removal of the conductive film only by the CMP process, resulting in deterioration of uniformity and increase in the cost of consumable materials, after forming a plug, an oxide film is formed as a sacrificial film for capacitor formation, and the oxide film is selectively etched. Define a lower electrode region to be connected to the plug, and then deposit a conductive layer for the lower electrode and perform full etching to leave the lower electrode conductive film on the oxide layer by about 50 kV to 500 kPa and to minimize the recess of the lower electrode conductive film. By using the CMP process can remove the conductive film for the lower electrode remaining on the oxide film To is characterized. According to the present invention, it is possible to reduce the loss of the conductive film for the capacitor lower electrode, to secure a uniform and sufficient capacitor charge storage capacity and to improve the device characteristics.
이하, 첨부된 도면 도2a 내지 도2c를 참조하여 본 발명의 제1 실시예에 따른 캐패시터 하부전극 형성 방법을 설명한다.Hereinafter, a method of forming a capacitor lower electrode according to a first embodiment of the present invention will be described with reference to FIGS. 2A to 2C.
먼저 도2a에 도시한 바와 같이 반도체 기판(20) 상에 형성된 비트라인 등의 하부구조(도시하지 않음)를 덮는 층간절연막(21)을 형성하고, 층간절연막(21) 상에 식각방지막(22)을 형성한다. 상기 식각방지막(22)은 SixNy또는 SiON으로 이루어지며 증착방법으로는 저압 화학기상증착법(low pressure chemical vapor deposition) 또는 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition)을 이용하여 400 ℃ 내지 800 ℃에서 100 Å 내지 1000 Å 두께로 증착한다.First, as shown in FIG. 2A, an interlayer insulating film 21 is formed to cover an underlying structure (not shown) such as a bit line formed on the semiconductor substrate 20, and the etch stop layer 22 is formed on the interlayer insulating film 21. To form. The etch stop layer 22 may be formed of Si x N y or SiON, and the deposition method may be 400 ° C. to 800 ° C. using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. Deposit at 100 kPa to 1000 kPa thickness at < RTI ID = 0.0 >
이어서, 식각방지막(22) 및 층간절연막(21) 등을 선택적으로 식각하여 반도체 기판(20)을 노출시키는 콘택홀을 자기정렬 콘택(self align contact, SAC) 식각 등의 방법으로 형성하고, 400 ℃ 내지 1200 ℃ 온도에서 500 Å 내지 3000 Å 두께의 실리콘막(23)을 형성하여 콘택홀 내부를 채우고 300 Å 내지 2000 Å 두께의 실리콘막(23)을 건식 또는 습식 방법으로 전면식각하여 콘택홀 내부의 실리콘막(23) 일부를 제거하는 리세스 공정을 실시한다. 다음으로, Ti, TiN, TiAlN, TiSiN, TaN, WN, TiSi2등과 같은 확산방지 금속막(24)을 스퍼터링(sputtering) 또는 화학기상증착 방법으로 50 Å 내지 1000 Å 두께 증착하고, 막의 종류에 따라 선택적으로 N2분위기에서 400 ℃ 내지 800 ℃로 열처리한다. 이어서, 50 ㎚ 내지 500 ㎚ 크기의 실리카, 알루미나 또는 세리아 계열의 슬러리의 수소이온농도(pH)를 2 내지 7로 유지하면서 확산방지 금속막(24)을 화학적기계적 연마하여 확산방지 금속막(24)과 실리콘막(23)으로 이루어지는 콘택 플러그를 형성한다.Subsequently, a contact hole for selectively etching the etch stop layer 22 and the interlayer insulating layer 21 to expose the semiconductor substrate 20 is formed by a method such as self align contact (SAC) etching, and the like, at 400 ° C. To form a silicon film 23 having a thickness of 500 mV to 3000 mV at a temperature of 1200 to 1200 ° C. to fill the inside of the contact hole, and to completely etch the silicon film 23 having a thickness of 300 mV to 2000 mV by dry or wet method. A recess step of removing part of the silicon film 23 is performed. Next, the diffusion barrier metal film 24 such as Ti, TiN, TiAlN, TiSiN, TaN, WN, TiSi 2, etc., is deposited by 50 to 1000 mm thick by sputtering or chemical vapor deposition, depending on the type of film. Optionally heat treatment at 400 ° C. to 800 ° C. in an N 2 atmosphere. Subsequently, the diffusion barrier metal layer 24 is chemically mechanically polished while the hydrogen ion concentration (pH) of the silica, alumina, or ceria-based slurry of 50 nm to 500 nm is maintained at 2 to 7. And a contact plug made of a silicon film 23 is formed.
다음으로, 전체 구조 상에 BPSG(borophospho silicate glass), PSG(phospho silicate glass), FSG(fluorinated silica glass), 플라즈마 화학기상증착법을 이용하여 형성한 TEOS(plasma enhanced tetraethyl orthosilicate) 및 SiH4, 고밀도 플라즈마(high density plasma)를 이용하여 형성한 USG(undoped silicate glass), APL(advanced planarization layer) 산화막 중 어느 하나로 이루어지며 희생산화막으로서 역할하는 하부전극 형성용 산화막(25)을 2000 Å 내지 10000 Å 두께로 형성하고, 막의 종류에 따라 선택적으로 300 ℃ 내지 10000 ℃ 온도에서 열처리한 다음, 캐패시터 하부전극용 마스크를 이용한 식각으로 산화막(25)을 선택적으로 제거하여 플러그를 노출시키는 하부전극 영역을 정의한다.Next, plasma enhanced tetraethyl orthosilicate (TEOS) and SiH 4 , high density plasma formed using borophospho silicate glass (BPSG), phospho silicate glass (PSG), fluorinated silica glass (FSG), and plasma chemical vapor deposition (CVD) on the entire structure. The lower electrode forming oxide film 25, which is made of any one of an undoped silicate glass (USG) and an advanced planarization layer (APL) oxide film formed using a high density plasma and serves as a sacrificial oxide film, has a thickness of 2000 to 10000 Å. The lower electrode region is formed, and heat treated at a temperature of 300 ° C. to 10000 ° C. according to the type of the film, and then selectively removes the oxide layer 25 by etching using a capacitor lower electrode mask to expose the lower electrode region.
이어서, 전체 구조 상에 400 Å 내지 5000 Å 두께의 하부전극용 전도막(26)을 형성한다. 상기 전도막(26)은 Pt, Ir 또는 Ru 등으로 형성하고 증착방법으로는 스퍼터링 또는 화학기상증착법을 이용하며, 막의 종류에 따라 선택적으로 400 ℃ 내지 800 ℃ 온도에서 후처리를 실시한다.Subsequently, a conductive film 26 for lower electrodes having a thickness of 400 mV to 5000 mV is formed on the entire structure. The conductive film 26 is formed of Pt, Ir, or Ru, and the like, by sputtering or chemical vapor deposition as a vapor deposition method, and optionally subjected to post-treatment at 400 to 800 ° C. according to the type of film.
다음으로 도2b에 도시한 바와 같이, 산화막(25) 상에 잔류하는 전도막(26)의 두께가 50 Å 내지 500 Å이 될 때까지 건식 또는 습식 방법을 이용한 전면식각 공정을 실시하여 전도막(26)의 일부를 제거한다.Next, as shown in FIG. 2B, the entire surface etching process using a dry or wet method is performed until the thickness of the conductive film 26 remaining on the oxide film 25 becomes 50 kPa to 500 kPa. Remove part of 26).
다음으로 도2c에 도시한 바와 같이, 50 ㎚ 내지 500 ㎚ 크기의 실리카, 알루미나 또는 세리아 계열 슬러리의 수소이온농도(pH)를 2 내지 7 또는 9 내지 11로 유지하면서 CMP 공정을 실시하여 산화막(25) 상의 전도막(26)을 제거해서 산화막(25) 표면을 노출시키고 하부전극 영역에만 전도막(26)이 남도록 한다.Next, as illustrated in FIG. 2C, the oxide film 25 is subjected to a CMP process while maintaining a hydrogen ion concentration (pH) of silica, alumina, or ceria-based slurry of 50 nm to 500 nm in a size of 2 to 7 or 9 to 11. By removing the conductive film 26 on the top layer, the surface of the oxide film 25 is exposed and the conductive film 26 remains only in the lower electrode region.
도3은 본 발명의 제2 실시예에 따라 형성된 캐패시터 하부전극을 보이는 단면도로서, 플러그를 실리콘막(23)만으로 형성한 예를 보이고 있다.3 is a cross-sectional view showing a capacitor lower electrode formed according to the second embodiment of the present invention, showing an example in which the plug is formed of only the silicon film 23.
본 발명의 제2 실시예는 반도체 기판(20) 상에 형성된 식각방지막(22) 및 층간절연막(21) 등을 선택적으로 식각하여 반도체 기판(20)을 노출시키는 콘택홀을 형성하고, 400 ℃ 내지 1200 ℃ 온도에서 500 Å 내지 3000 Å 두께의 실리콘막(23)을 형성하여 콘택홀 내부를 채운 다음, 50 ㎚ 내지 500 ㎚ 크기의 실리카, 알루미나 또는 세리아 계열 슬러리의 수소이온농도(pH)를 5 내지 9로 유지하면서 CMP 공정을 실시하여 식각방지막(22) 상의 실리콘막(23)을 제거하여 실리콘막(23)만으로 이루어지는 플러그를 형성한다. 이러한 플러그 형성 방법을 제외한 단계는 전술한 본 발명의 제1 실시예와 동일하므로 그 상세한 설명은 생략한다.The second embodiment of the present invention forms a contact hole for exposing the semiconductor substrate 20 by selectively etching the etch stop layer 22 and the interlayer insulating layer 21 formed on the semiconductor substrate 20, 400 ℃ to A silicon film 23 having a thickness of 500 Pa to 3000 Pa is formed at a temperature of 1200 ° C. to fill the inside of the contact hole, and then the hydrogen ion concentration (pH) of the silica, alumina or ceria-based slurry of 50 nm to 500 nm is 5 to 5 nm. The CMP process is carried out while keeping it at 9 to remove the silicon film 23 on the etch stop film 22 to form a plug consisting of only the silicon film 23. Since the steps except for the plug forming method are the same as those of the first embodiment of the present invention, a detailed description thereof will be omitted.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 이너 스택형 캐패시터 하부전극 형성 방법에 있어서, 하부전극용 전도막의 일부를 전면식각으로 제거한 다음 CMP 공정을 실시하는 2 단계 공정을 실시함으로써, 종래 CMP 공정에서 요구되는 과도한 연마시간을 감소시킬 수 있어 하부전극막과 캐패시터 균일도를 향상시켜 소자 특성을 크게 향상시킬 수 있다. 또한 CMP 공정만을 적용하였을 때 요구되는 과도한 연마시간으로 인한 소모재 비용 증가를 감소시킬 수 있다.According to the present invention made as described above, in the method of forming an inner stack type capacitor lower electrode, by removing a part of the conductive film for the lower electrode by full etching and then performing a two-step process of performing a CMP process, excessive polishing required in the conventional CMP process is performed. Since the time can be reduced, the device characteristics can be greatly improved by improving the uniformity of the lower electrode film and the capacitor. In addition, it is possible to reduce the increase in the cost of consumables due to the excessive polishing time required when applying only the CMP process.
Claims (6)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100444308B1 (en) * | 2001-12-29 | 2004-08-16 | 주식회사 하이닉스반도체 | Formation Method of Semiconductor Device |
| KR100649807B1 (en) * | 2001-06-29 | 2006-11-24 | 주식회사 하이닉스반도체 | Slurry for Chemical Mechanical Polishing of Ruthenium Titanium nitride and the Process for Polishing Using It |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100649807B1 (en) * | 2001-06-29 | 2006-11-24 | 주식회사 하이닉스반도체 | Slurry for Chemical Mechanical Polishing of Ruthenium Titanium nitride and the Process for Polishing Using It |
| KR100444308B1 (en) * | 2001-12-29 | 2004-08-16 | 주식회사 하이닉스반도체 | Formation Method of Semiconductor Device |
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