KR20010039359A - Stable voltage regulator in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: A voltage regulator of a stable semiconductor integrated circuit is provided to generate various voltages stably in a system using various kinds of power supply voltages. CONSTITUTION: The voltage regulator includes: a reference voltage generating part(310) generating a reference voltage signal(Vref); a comparison part(310) generating a comparison voltage signal(Vcomp) by comparing the reference voltage signal with a feedback voltage signal in response to a clock signal; a clamp(330) generating a clamp voltage signal(Vclamp) by clamping the comparison voltage signal; a charge pump(340) generating a control voltage signal(Vg) in response to the clock signal and the comparison voltage signal; a feedback part(350) generating the feedback voltage signal and feeding it back to the comparison part in response to the control voltage signal; and an output part(360) generating the second supply voltage(VCC) as an output in response to the control voltage signal. The feedback part includes: the first NMOS transistor(NM31) transferring the first supply voltage to the feedback voltage signal via the first resistor(R31) through a source-drain path by receiving the control voltage signal to a gate; and the first and the second resistor(R32) outputting the feedback voltage signal to a common node by being connected in serial between the first supply voltage(VDD) and a ground voltage(VSS).

Description

Stable voltage regulator in semiconductor integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a voltage regulator of a semiconductor integrated circuit for stably generating various voltage signals.

In general, with the development of process technology, as the integration of circuits increases and the size of transistors decreases, the supply voltage decreases. As a result, a chip using two power supplies, such as 5V and 3.3V, is used in one system. To compensate for this, a voltage regulator that lowers the power supply of 5V to 3.3V is used.

1 is a diagram illustrating an example in which a voltage regulator is used in a digital chip. A digital chip having two or more supply power sources receives a first supply power supply VDD and receives a second supply power supply VCC having a relatively low potential. The voltage regulator 110 is generated, the digital core 130 driven by the second supply power supply VCC, and the input / output terminal 150 driven by the first supply power supply VDD.

Figure 2a is a circuit diagram according to an embodiment of the voltage regulator according to the prior art, the voltage regulator 110 is a reference voltage signal (Vref) and the output signal of the voltage regulator 110, the second supply power signal ( An operational transconductance amplifier (“OTA”) 210 for generating a control signal ctrl_a for controlling the potential of the second supply power signal VCC in response to VCC). A PMOS transistor PM21 that receives the control signal ctrl_a and transfers the first supply power VDD to the second supply power VCC through a source-drain path, and the second supply power VCC and ground. In order to compensate for the influence of the output impedance Z21 existing between the power supply VSS, a capacitor C21 is disposed between the second supply power supply VCC and the ground power supply VSS.

FIG. 2B is a circuit diagram according to another embodiment of the voltage regulator according to the prior art, wherein the voltage regulator 110 is a reference voltage signal Vref and an output signal of the voltage regulator 110. An operational transconductance amplifier (OTA) 220 for generating a control signal ctrl_b for controlling the potential of the second supply power signal VCC in response to VCC; and the control signal ctrl_b through a gate. A NMOS transistor NM21 that receives the first supply power VDD to the second supply power VCC through a source-drain path, and is present between the second supply power VCC and the ground power supply VSS. It is composed of output impedance Z22.

FIG. 2C is a circuit diagram according to another embodiment of the voltage regulator according to the prior art, wherein the voltage regulator 110 receives the first supply power signal VDD and generates the second supply power signal VCC. Charge pump 230 for generating a control signal (ctrl_c) for controlling the control signal received by the control signal (ctrl_c) to the gate and transfers the control signal (ctrl_c) to the node N21 through a source-drain path An NMOS transistor NM23 receives the signal of the node N21 through a gate, an NMOS transistor NM24 that transfers the signal of the node N21 to a node N22 through a source-drain path, and a source-drain receives the signal of the node N22 through a gate NMOS transistor NM25 which transfers the signal of the node N22 to the ground power supply VSS through a path, a capacitor C22 positioned between the control signal ctrl_c and the ground power supply VSS, and the control signal (gate). ctrl_ c) an NMOS transistor NM22 that receives the first supply power VDD to the second supply power VCC through a source-drain path, the second supply power VCC, and the ground power VSS. Output impedance Z23 between them.

The operation and problems of the prior art according to the three embodiments having the above configuration will be described together.

2A is an output terminal using the feedback of the operational transconductance amplifier (OTA) 210. The output current amount is controlled by a control signal ctrl_a applied to the gate of the PMOS transistor PM21. As the frequency increases, the loop gain drops sharply, resulting in an increase in output impedance Z21. In order to compensate for this, a large size capacitor C21 is required, but this causes a problem of stability of feedback and has a disadvantage of attaching a large capacitor outside the chip.

Figure 2b has a low output impedance Z22 due to the source follower structure, which eliminates the need for a large size capacitor and high stability. However, since the voltage of the control signal ctrl_b applied to the gate of the NMOS transistor NM21 must be lower than the external power supply voltage, there is a problem in controlling the voltage between 5V and 3.3V.

2C is the most stable because there is no feedback, and the charge pump is used, so the gate voltage of the NMOS transistor NM22 can be raised higher than the external power supply voltage, so that the voltage can be adjusted between 5V and 3.3V, but the output voltage is the logic threshold of the NMOS transistor. As the change in the threshold voltage Vt changes, it implies inaccuracies due to the Vt change in the process.

The present invention is to solve the problems of the prior art as described above, it is an object of the present invention to provide a voltage regulator of a semiconductor integrated circuit that generates a variety of voltages stably in a system using various types of power supply voltage. .

1 shows an example in which a voltage regulator is used in a digital chip.

Figures 2a to 2c is a circuit diagram according to various embodiments of the voltage regulator according to the prior art.

Figure 3 is a block diagram of the voltage regulating device according to an embodiment of the present invention.

4 is a detailed circuit diagram of the clamp according to an embodiment of the present invention.

5 is a conceptual diagram of a charge pump according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

310: reference voltage generation unit 320: comparison unit

330: clamp 340: charge pump

350: feedback unit 360: output unit

In order to achieve the above object, the present invention provides a voltage regulator for generating a second supply power source having a relatively low power level compared to the first supply power source as a first supply power source, the reference voltage generation unit generating a reference voltage signal. ; A comparator for generating a comparison voltage signal by comparing the reference voltage signal and a feedback voltage signal in response to a clock signal; A clap for generating a clamp voltage signal by clamping the comparison voltage signal; A charge pump generating a control voltage signal in response to the clock signal and the comparison voltage signal; A feedback unit generating the feedback voltage signal in response to the control voltage signal and returning the feedback voltage signal to the comparison unit; And an output unit configured to generate the second supply power as an output in response to the control voltage signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Figure 3 is a block diagram of a voltage regulating device according to an embodiment of the present invention.

Referring to FIG. 3, a voltage regulator for generating a second supply power supply VCC having a lower power level than the first supply power supply with the first supply power supply VDD generates a reference voltage signal Vref. A comparison unit 320 for generating a comparison voltage signal Vcomp by comparing the reference voltage generator 310 with the reference voltage signal Vref and the feedback voltage signal Vrep in response to a clock signal clk; A clamp 330 for generating a clamp voltage signal Vclamp that clamps the comparison voltage signal Vcomp, and a control voltage signal in response to the clock signal clk and the comparison voltage signal Vcomp. A charge pump 340 for generating Vg, a feedback unit 350 for generating the feedback voltage signal Vrep in response to the control voltage signal Vg, and returning it to the comparator 320; The output unit 360 generates the second supply power VCC as an output in response to the voltage signal Vg.

The feedback unit 350 receives the control voltage signal Vg through a gate and transfers the first supply power VDD to the feedback voltage signal Vrep through a resistor R31 through a source-drain path. NM31 and the resistor R31 and resistor R32 connected in series between the first supply power supply VDD and the ground power supply VSS transmitted through the NMOS transistor NM31 to output the feedback voltage signal to a common node.

The output unit 360 receives an input of the control voltage signal Vg through a gate and transfers the first supply power VDD to the second supply power VCC through a source-drain path; A capacitor C31 connected between the control voltage signal Vg and the ground power supply VSS, and a resistor R33 connected between the second supply power supply VCC and the ground power supply VSS.

The supply power of all the blocks of the power regulator uses the first supply power VDD.

4 is a detailed circuit diagram of the clamp 330 according to an embodiment of the present invention.

4, the clamp 330 includes a control voltage input unit 410 for generating an output node N41 signal in response to the control voltage signal Vg, and the clamp voltage in response to the comparison voltage signal Vcomp. The clamp voltage signal Vclamp is applied in response to a comparison voltage input unit 450 for supplying or drawing a current to a signal node, and an output signal of the control voltage input unit 410 and the comparison voltage input unit 450. It consists of a clamp output unit 430 to generate.

The control voltage input unit 410 receives the control voltage signal Vg through a gate and transfers the supply voltage VDD to the node N42 through a source-drain path, and transmits the control voltage signal through a gate. NMOS transistor NM7 which receives the input and transfers the supply power to the current source J1 through the node N44, and a node between the node N43 and the node through the source-drain path through the source-drain path. A PMOS transistor PM3 for connecting a node, a PMOS transistor PM4 for receiving a node N43 signal through a gate, and a path between the node N42 and a node N41 through a source-drain path, and a node for receiving the node N41 signal through a gate. A NMOS transistor NM1 connecting a path between the node N41 and the node N43 through a drain path, and the ground power signal to a gate, respectively; It is composed of PMOS transistors PM5 and PM6 which receive the input and transfer the ground power signal to the node N43 through a source-drain path.

The comparison voltage input unit 450 receives the node N45 signal and the comparison voltage signal Vcomp through gates, respectively, and transfers the node N44 signal to the clamp voltage signal through a source-drain path connected in series. NMOS transistors NM3 and NM4 for receiving the node N46 signal and the comparison voltage signal through gates, and transmitting the ground power signal to the clamp voltage signal through a source-drain path connected in series, and the node N45 signal through a gate. PMOS transistor PM10 that receives the input and supplies the current to the current source J3 from the node N44 through the source-drain path, and receives the node N46 signal through the gate to open the path between the current source J3 and the ground power source through the source-drain path. The main consists of NMOS transistor NM5.

The clamp output unit 430 receives a node N47 signal through a gate and opens a path between the node N41 and a current source J2 through a source-drain path, and receives a node N41 signal through a gate and receives a source-drain signal. An NMOS transistor NM2 that transfers the node N41 signal as the clamp voltage signal through a path, and a PMOS transistor PM8 that receives the node N47 signal as a gate and transfers the ground voltage signal to the clamp voltage signal through a source-drain path. Is made of.

5 is a conceptual diagram of a charge pump 340 according to an embodiment of the present invention.

Referring to FIG. 5, the charge pump 340 buffers the clamp voltage signal Vclamp to generate an output node N51 signal, and controls the connection between the output node N51 and the output node N52. The first switch S1, the second switch S2 for controlling the connection between the output node N53 and the ground power supply VSS, and the third switch for controlling the connection between the output node N51 and the output node N53 ( S3), a fourth switch S4 for controlling the connection between the output node N52 and the control voltage signal Vg, a capacitor C51 located between the output node N52 and the output node N53, and the control voltage signal. And a capacitor C52 located between Vg and the ground power supply VSS.

It looks at the operation according to an embodiment of the present invention having the configuration as described above.

When the power is supplied through the first supply VDD, the capacitor C31 has not been charged yet, so it is in a logic " low " state and the control voltage signal Vg which is the gate voltage of the NMOS transistors NM31 and NM32. ) And also a logic " low " so that no current flows through the resistor R31 and the resistor R32. Accordingly, the feedback voltage signal Vrep becomes a logic "low" and is applied to the comparison unit 320.

In the clamp 330, the clamp voltage signal Vclamp is activated and applied to the charge pump 340 in response to the comparison voltage signal Vcomp, which is activated in comparison with the reference voltage signal Vref, to control the control voltage. The signal Vg is activated to accumulate charge in the capacitor C31.

When the voltage is gradually increased in the capacitor C31 and the feedback voltage becomes larger than the reference voltage, the comparator detects this and discharges the voltage of the capacitor C31 through a charge pump. To supply.

If the threshold voltage of the NMOS transistor NM31 is changed due to a temperature change and the internal power supply voltage is increased, the threshold voltage of the NMOS transistor NM2 is also changed, which is detected by a comparator and is charged by the charge pump. This is compensated by adjusting the gate voltage of.

In detail with respect to the clamp 330, since the voltage of the node N42 is (Vg-Vt) minus the threshold voltage Vt of the NMOS transistor NM6, the voltage of the node N43 is divided by the voltage distribution ( divide) to (Vg-Vt) / 2. In addition, the voltage of the node N41 becomes (Vg + Vt) / 2 in which Vt is larger than that of the node N43 by the NMOS transistor NM1.

When the "low" signal is applied to the comparison voltage signal Vcomp, the NMOS transistor NM13 is turned on and the NMOS transistor NM12 is turned on so that the clamp voltage signal Vclamp becomes (Vg + Vt) /. When the signal "high" is applied as the signal, the PMOS transistor PM11 is turned on and the PMOS transistor PM8 is turned on so that the clamp voltage signal becomes (Vg-Vt) / 2. This output voltage is essential to precisely control the output stage if the charge distribution of the charge pump is to always charge or discharge a certain amount of charge in the capacitor C31.

The charge pump 340 is the first switch (S1) and the second switch (S2) at the same time on-off, the third switch (S3) and the fourth switch (S4) at the same time on-off First, the first switch and the second switch is turned on to store the clamp voltage signal in the capacitor C51, and when the third switch and the fourth switch are turned on, the charge stored in the clamp voltage signal and the capacitor C51 Is added to signal twice the clamp voltage signal to the capacitor C52.

The feedback unit 350 senses the output voltage in the feedback unit having the same structure as the output terminal instead of directly sensing the output voltage, thereby blocking an unstable element due to the output load.

On the other hand, the position of the NMOS transistor NM32 should be positioned at the center of the NMOS transistor NM31 during layout in order to allow various changes occurring in the NMOS transistor NM31 to be reflected and corrected in the NMOS transistor NM32.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above is to stably generate various voltages in a system using various types of power supply voltages.

Claims (10)

In the voltage regulating device for generating a second supply power source having a lower power level relative to the first supply power supply as a first supply power supply, A reference voltage generator for generating a reference voltage signal; A comparator for generating a comparison voltage signal by comparing the reference voltage signal and a feedback voltage signal in response to a clock signal; A clap for generating a clamp voltage signal by clamping the comparison voltage signal; A charge pump generating a control voltage signal in response to the clock signal and the comparison voltage signal; A feedback unit generating the feedback voltage signal in response to the control voltage signal and returning the feedback voltage signal to the comparison unit; An output unit generating the second supply power as an output in response to the control voltage signal Voltage control device of a semiconductor integrated circuit having a. The method of claim 1, The feedback unit may include a first NMOS transistor configured to receive the control voltage signal through a gate and transfer the first supply power to the feedback voltage signal through a first resistor R31 through a source-drain path; The first and second resistors connected in series between the first supply power source and the ground power source transferred through the first NMOS transistor to output the feedback voltage signal to a common node; Voltage control device of a semiconductor integrated circuit comprising a. The method of claim 2, The output unit, A second NMOS transistor receiving the control voltage signal through a gate and transferring the first supply power to the second supply power through a source-drain path; A capacitor connected between the control voltage signal and the ground power source; And A third resistor connected between the second supply power source and the ground power source; Voltage control device of a semiconductor integrated circuit comprising a. The method of claim 3, And the second NMOS transistor is positioned at the center of the first NMOS transistor in the layout. The method of claim 1, The power supply of all the blocks of the power regulator is the voltage regulator of the semiconductor integrated circuit, characterized in that using the first supply power. The method of claim 1, The clamp is, A control voltage input unit configured to generate a first output node signal in response to the control voltage signal; A comparison voltage input unit configured to supply or draw current to the clamp voltage signal in response to the comparison voltage signal; A clamp output unit configured to generate the clap voltage signal in response to an output signal of the control voltage input unit and the comparison voltage input unit; Voltage control device of a semiconductor integrated circuit comprising a. The method of claim 6, The control voltage input unit, A first NMOS transistor receiving the control voltage signal through a gate and transferring the supply power to a second output node through a source-drain path; A second NMOS transistor receiving the control voltage signal through a gate and transferring the supply power through a third output node to a first current source J1 through a source-drain path; A first PMOS transistor receiving a fourth output node signal through a gate and connecting a path between the second output node and the fourth output node through a source-drain path; A second PMOS transistor configured to receive the fourth output node signal through a gate and connect a path between the second output node and the first output node through a source-drain path; A third NMOS transistor receiving the first output node signal through a gate and connecting a path between the first output node and the fourth output node through a source-drain path; And A third PMOS transistor and a fourth PMOS transistor configured to receive the ground power signal through a gate, and to transfer the ground power signal to the fourth output node through a source-drain path; Power control apparatus for a semiconductor integrated circuit comprising a. The method of claim 7, wherein The comparison voltage input unit, A fifth PMOS transistor and a sixth PMOS transistor configured to receive a fifth output node signal and the comparison voltage signal through a gate, and to transfer the third output node signal to the clamp voltage signal through a source-drain path connected in series; A fourth NMOS transistor and a fifth NMOS transistor configured to receive a sixth output node signal and the comparison voltage signal through a gate, and to transfer the ground power signal to the clamp voltage signal through a source-drain path connected in series; A seventh PMOS transistor configured to receive the fifth output node signal through a gate and supply current from the third output node to a second current source through a source-drain path; And A sixth NMOS transistor configured to receive the sixth output node signal through a gate and open a path between the second current source and the ground power source through a source-drain path; Power control apparatus for a semiconductor integrated circuit comprising a. The method of claim 8, The clamp output unit, An eighth PMOS transistor configured to receive a seventh output node signal through a gate and open a path between the first output node and a third current source through a source-drain path; And A seventh NMOS transistor configured to receive the first output node signal through a gate and transfer the first output node signal as the clamp voltage signal through a source-drain path; And A ninth PMOS transistor configured to receive the seventh output node signal through a gate and transfer the ground voltage signal to the clamp voltage signal through a source-drain path; Power control apparatus for a semiconductor integrated circuit comprising a. The method of claim 1, The charge pump, A buffer configured to buffer the clamp voltage signal to generate a first output node signal; First switch means for controlling a connection between the first output node and a second output node; Second switch means for controlling a connection between a third output node and the ground power source; Third switch means for controlling a connection between the first output node and the third output node; Fourth switch means for controlling a connection between the second output node and the control voltage signal; A first capacitor located between the second output node and the third output node; And A second capacitor located between the control voltage signal and the ground power source Voltage control device of a semiconductor integrated circuit comprising a.