KR20010037890A - Fuse box for repairing memory device - Google Patents

Abstract

PURPOSE: A repair fuse box is provided to convertibly use a row repair fuse box and a column repair fuse box in a composition fuse box according to repair usage. CONSTITUTION: The repair fuse box(5) includes a main address fuse portion(30), a fuse selection portion(10) and an address switching portion(20). The main address fuse portion selects one of a spare row line and a spare column line in response to an output of the fuse selection portion and replaces a line connecting a failed memory cell with the selected line(column line or row line) when the memory cell is a failure. The main address fuse portion outputs a spare column detection signal(SCD) to select the spare column line and a spare row detection signal(SRD) to select the spare row line. The fuse selection portion determines whether to use the main address fuse portion as a row repair fuse or a column repair fuse. The address switching portion selects one of a predecoded row address(row_add) and a predecoded column address(col_add) and transfers to the main address fuse portion.

Description

Repair fuse box for memory devices {FUSE BOX FOR REPAIRING MEMORY DEVICE}

The present invention relates to a repair fuse box of a memory device, and more particularly, a fuse box is configured by combining a low repair fuse box and a column repair fuse box that operate independently in a redundancy circuit of a memory device, and convert the fuse box according to a use. The present invention relates to a repair fuse box of a memory device capable of increasing repair efficiency.

If any one of a number of fine cells in the memory device is defective, it cannot be used as a DRAM and is treated as a fail product. However, as the density of DRAM increases, there is a high probability that defects will occur only in a small number of cells.

Therefore, in this case, a method of increasing the yield by adopting a redundancy cell installed in the DRAM in advance is replaced. The redundancy circuit increases the area of the chip and increases the test required for defect repair. However, the area of the chip does not increase much in DRAM, so it is adopted from 64K to 256K DRAM in earnest.

The redundancy circuit of the memory device is installed for each sub-array block. In this case, a spare ROW and a COLUMN is installed in each cell array in advance so that a defect occurs, thereby replacing a failed memory cell with a redundancy cell in ROW / COLUMN units. When the wafer processor is terminated, a test is performed on the internal circuitry to select a fail memory cell through the test and replace the corresponding address with the address signal of the redundancy cell. The selection changes to the line.

If a fail occurs in the memory cell after the test process as described above, the redundancy cell is replaced. In the meantime, the redundancy cell also performs a test so that the failing cell is not replaced with the redundancy cell.

Therefore, since the row fuse box and the column fuse box must be arranged as much as possible to improve the yield of the memory device, the entire chip area becomes large.

In addition, if more defects occur than a fuse box disposed only in a specific part of a row or a column, repair is not possible anymore, and the other fuse box is not used and occupies only the layout area, thereby reducing the yield of the chip. have.

The present invention was created to solve the above problems, and an object of the present invention is to convert a low repair fuse box and a column repair fuse box independently disposed in a memory device into one composite fuse box according to a repair purpose. It is to provide a fuse box of a memory device.

1 is a block diagram illustrating a repair fuse box and a cell block of a memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram illustrating the repair fuse box of FIG. 1.

3 is a circuit diagram illustrating in detail the fuse selection unit according to the present invention.

4 is a circuit diagram illustrating in detail an address switching unit according to the present invention.

FIG. 5 is a circuit diagram illustrating an address switching unit in detail according to the present invention.

6 is a circuit diagram showing in detail the main address fuse according to the present invention.

7 is a circuit diagram illustrating in detail the first switch mux of the main address fuse according to the present invention.

FIG. 8 is a circuit diagram illustrating in detail the second switch mux of the main address fuse according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: fuse selection unit 20: address switching unit

30: main address fuse unit 110: selection switch

According to the present invention for realizing the above object, a fuse selector for selecting a spare row line and a spare column line, and a main address fuse unit for selecting one of the low repair fuse and the column repair fuse can be used. And an address switching unit which selects the pre-decoded row address and column address and transfers them to the main address fuse unit.

According to the present invention made as described above, the main address fuse unit may be used as a low repair fuse or a column repair fuse to replace a defective line with a spare line to repair a memory cell. The repair operation is performed by the column repair fuse and performs a repair by selecting a spare row line and a spare column line based on a value that is output by selecting an address, that is, a row address and a column address, from the input address to the address switching unit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

1 is a block diagram illustrating a repair fuse box and a cell block of a memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram illustrating the repair fuse box of FIG. 1 in detail.

As shown here, the repair fuse box 5 is installed according to the memory cell block 40, and each repair fuse box 5 includes a main address fuse unit for selecting a spare row line and a spare column line. 30), the fuse selection unit 10 for selecting the main address fuse unit 30 as one of the low repair fuse and the column repair fuse, and the predecoded row address row_add and the column address col_add. The address switching unit 20 selects and transfers the main address fuse unit 30 to the main address fuse unit 30.

Therefore, in order to replace the defective line with a spare line to repair the memory cell, the fuse selection unit 10 selects whether to use the main address fuse unit 30 as a low repair fuse or a column repair fuse. The main address fuse is configured to be operated as a low repair fuse or a column repair fuse and to select an address for repairing among input addresses, that is, a row address row_add and a column address col_add at the address switching unit 20 and output the main address fuse. The block 30 performs a repair by selecting the cell block 40 based on the spare column detection signal SCD for selecting the spare column line and the spare row detection signal SRD for selecting the spare row line.

3 is a circuit diagram illustrating in detail the fuse selection unit according to the present invention.

As shown here, the selection switch 110 is connected to the power supply voltage VCC and selects the low switching signal and the column switching signal, and receives the power up signal (pwrupb; power up signal) to output the output value of the selection switch 110. The input unit 120 for initializing the input unit, the sensing unit 140 for sensing the output value of the selection switch 110, and the pull-down transistor 130 for pulling down the output value of the selection switch 110 by receiving the values of the sensing unit 140. ) And an output unit 150 for outputting the row switching signal ROW_SWITCHb and the column switching signal ROW_SWITCH based on the output value of the sensing unit 140.

Therefore, in order to select whether to use the main address fuse unit 30 as a low repair fuse or a column repair fuse, pwrupb (power up signal) is input and low switching is performed when the selection switch 110 is not cut while holding an initial value. When the signal ROW_SWITCHb is used as the low repair fuse at a low potential and the selection switch 110 is cut off, the low switching signal ROW_SWITCHb is used as the column repair fuse at high potential.

4 is a circuit diagram illustrating in detail an address switching unit according to the present invention.

As shown here, the address switching unit 20 may include the pre-decoded addresses' gax 'and' input under the control of the row switching signal ROW_SWITCHb and the column switching signal ROW_SWITCH output from the fuse selection unit 10. When gay 'is switched in the address mux unit 210, the row address (row_add) is output as the redundancy address (red_add) when used as a row repair fuse, and when the column repair fuse is used as the column repair fuse, the column address (col_add) as the redundancy address ( red_add).

5 is a circuit configuration diagram showing in detail the address mux portion of the address switching portion according to the present invention.

As shown here, the first transfer transistor 212 is turned on by the low switching signal ROW_SWITCHb to transfer the row address row_add, and is turned on by the column switching signal ROW_SWITCH to transfer the column address col_add. Is composed of a second transfer transistor 214.

That is, when the low switching signal ROW_SWITCHb is used as the low repair fuse at low potential, the first transfer transistor 212 is turned on to transfer the row address row_add to output the row address row_add to the redundancy address red_add. .

On the other hand, when the column switching signal ROW_SWITCH is used as the column repair fuse at a low potential, the second transfer transistor 214 is turned on to transfer the column address col_add to output the column address col_add to the redundancy address red_add. .

6 is a circuit diagram showing in detail the main address fuse according to the present invention.

As shown here, the column initializer (col_init) initializes for use as a column repair fuse box, the row initializer (row_init), initialized for use as a low repair fuse box, and the column initializer (col_init) and low initializer. A first switch mux 310 for selectively outputting a row_init output signal by a row switching signal ROW_SWITCHb and a column switching signal ROW_SWITCH, and an output red_init of the first switch mux 310. One side is connected to the fuse stage 330 to designate a defective address, and the other end of the fuse stage 330 is connected to detect the cutting state of the fuse stage 330 according to the output signal of the address switching unit 20 A sensing signal input unit 340 for forming a current path to ground, a pull-up unit 350 for maintaining the first switch mux unit 310 output signal red_init strongly at a high potential at a high potential, and a pull-up unit 350. Low output signal of Consists of a signal (ROW_SWITCHb) and a column switch signal (ROW_SWITCH) spare column sense signal (SCD) only, or the spare row detection signal the second multiplexer switch unit 320 for selectively delivered to the (SRD) only by.

Therefore, when the main address fuse unit 30 operates as a low repair fuse box, since the xdp signal is initially high in the low initialization unit row_init, the n1 node is maintained at high potential through the first switch mux unit 310 and then ras. When the xdp signal becomes active at low potential, the power supply of the n1 node is stopped, and the row address (row_add) enters through the redundancy address (red_add), so that the gmos of the detection signal input unit 340 of the fuse stage 330 is active. Turn on to make current path.

If the input row address (row_add) is an address indicating a defective cell, the corresponding fuse is cut and the n1 node is kept at a high potential to maintain a spare row detection signal (SRD) through the second switch mux unit 320. detect) is selected and output at high potential.

The repair word line substituted through the block selector 60 in the corresponding cell array shown in FIG. 1 is selected by the output spare row detection signal SRD.

On the other hand, when the main address fuse unit 30 operates as a column repair fuse box, since the xdpb_red signal is initially low in the column initialization unit col_init, the node c1 maintains a high potential and then bsel98 (block select address) enters. The current path is made by turning on the gmos of the corresponding detection signal input unit 340.

If the block is faulty, cut the fuse to keep the c1 node at high potential and combine it with the sg (sensing generator) signal to make the c2 node low potential and detect the atdscp (column address detect sum) signal to initialize the column. The high potential is supplied to the n1 node through the first switch mux unit 310 controlled by the high value of the col_init and controlled by the column switching signal ROW_SWITCH and the low switching signal ROW_SWITCHb, and through the redundancy address red_add. The column address col_add is input to turn on the gmos of the detection signal input unit 340 of the fuse stage 330 to create a current path.

If the input column address col_add is an address indicating a defective cell, the corresponding fuse is cut and the n1 node is kept at a high potential to maintain a spare column detection signal (SCD; spare) through the second switch mux unit 320. column detect) is selected and output at high potential.

The output spare column detection signal SCD enters the SYI decoder 50 block shown in FIG. 1 and a repair column is selected.

In the above repair operation, the normal word line YI is disabled by the SRD / SCD signal.

7 is a circuit diagram illustrating in detail the first switch mux of the main address fuse according to the present invention.

As shown here, the third transfer transistor 312 is turned on by the low switching signal ROW_SWITCHb and transfers the row_init output signal, and is turned on by the column switching signal ROW_SWITCH to initialize the column initialization unit (3). col_init) and a fourth transfer transistor 314 that transmits an output signal.

Therefore, when the low switching signal ROW_SWITCHb has a low potential, the low initialization unit transmits a row_init output signal to initialize the main address fuse unit 30 as a low repair fuse box, and the column switching signal ROW_SWITCH is low. When the potential is supplied, the column initialization unit (col_init) output signal is transmitted to initialize the main address fuse unit 30 as a column repair fuse box.

FIG. 8 is a circuit diagram illustrating in detail the second switch mux of the main address fuse according to the present invention.

As shown here, the fifth switching transistor 322 and the column switching signal ROW_SWITCH are turned on by the low switching signal ROW_SWITCHb to transfer the redundancy node signal red_node to the spare row detection signal SRD. The sixth transfer transistor 324 is turned on to transmit the redundancy node signal red_node to the spare column detection signal SCD.

Therefore, when the low switching signal ROW_SWITCHb is low, the redundancy node signal red_node is transferred to the spare word line through the block selector 60 by the spare row detection signal SRD, and the column switching signal ( When ROW_SWITCH is at low potential, the redundant node signal red_node is transmitted to select the spare column line through the SYI decoder 50 by the spare column detection signal SCD.

As described above, the present invention enables a low repair fuse box and a column repair fuse box independently disposed in a memory device to be converted into one composite fuse box according to a repair purpose, thereby increasing the yield of repair and the number of repair fuse boxes. There is an effect that can reduce the area of the chip by reducing.

Claims (7)

A main address fuse for selecting a spare row line and a spare column line; A fuse selector configured to select the main address fuse to be one of a low repair fuse and a column repair fuse; An address switching unit which selects a pre-decoded row address and a column address and transfers them to the main address fuse unit. Repair fuse box of the memory device, characterized in that consisting of. The method of claim 1, wherein the fuse selector A selector switch connected to the supply voltage to select a low signal and a column signal; An input unit configured to receive a power signal and initialize an output value of the selection switch; A sensing unit sensing an output value of the selection switch; A pull-down transistor configured to pull down an output value of a selection switch by receiving a value of the sensing unit; An output unit for outputting a low signal and a column signal by an output value of the sensing unit Repair fuse box of the memory device, characterized in that consisting of. The method of claim 1, wherein the address switching unit A plurality of address muxes for switching the pre-decoded addresses input under the control of the low switching signal and the column switching signal output from the fuse selection unit. Repair fuse box of the memory device, characterized in that consisting of. The method of claim 3, wherein the address mux portion A first transfer transistor turned on by the low switching signal to transfer a row address; A second transfer transistor turned on by the column switching signal to transfer a column address Repair fuse box of the memory device, characterized in that consisting of. The method of claim 1, wherein the main address fuse unit A column initializer (col_init) to initialize for use as a column repair fuse box, A row initializer (row_init) to initialize for use as a low repair fuse box, A first switch mux for selectively outputting the column initialization unit and the low initialization unit output signal by a low switching signal and a column switching signal; A fuse unit having one side connected to an output terminal of the first switch mux unit to designate a defective address; A detection signal input part connected to the other side of the fuse part to sense a cutting state of the fuse part according to an output signal of an address switching part to form a current path to ground; A pull-up part for maintaining the first switch mux part output signal strongly at a high potential when the output signal is high; A second switch mux selectively outputting the output signal of the pull-up part to a spare column sensing signal terminal or a spare row sensing signal terminal based on the low switching signal and the column switching signal; Repair fuse box of the memory device, characterized in that consisting of. The method of claim 5, wherein the first switch mux portion A third transfer transistor turned on by the low switching signal to transfer the low initialization unit output signal; A fourth transfer transistor that is turned on by the column switching signal and transfers the column initializer output signal Repair fuse box of the memory device, characterized in that consisting of. The method of claim 1, wherein the second switch mux portion A fifth transfer transistor which is turned on by the low switching signal and transfers the redundancy node signal to the spare row detection signal terminal; A sixth transfer transistor turned on by the column switching signal to transfer the redundancy node signal to the spare column detection signal terminal; Repair fuse box of the memory device, characterized in that consisting of.