KR20010030168A - Process For Fabricating Low Dielectric Constant(low-k) Layers In Integrated Circuits - Google Patents

Abstract

PURPOSE: A method for fabricating a multi-layer dielectric is provided to reduce line-to-line capacitance. CONSTITUTION: The method includes a step where a dielectric layer of multilayered structure is formed on a substrate, and the dielectric layer of multilayered structure is composed of a structure layer and a dielectric layer of low dielectric constant. The method is substantially identical that discussed in connection with the structure in which the full via is fabricated first. A trench is fabricated through the selectivity between layers(203,204). After the etching of the trench layer(204) to form the trench(207), a via photoresist(301) is disposed and a full via(205) is etched.

Description

Process For Fabricating Low Dielectric Constant (low-k) Layers In Integrated Circuits

The present invention relates to an integrated circuit structure and a method for manufacturing an integrated circuit having reduced line-to-line capacitance thereof.

Integration and miniaturization of integrated circuits results in reducing the spacing between integrated circuit portions. This reduction results in a line-to-line capacitance (C _LL ) or horizontal level conductor that will be a component of excellent plastic capacitance in the integrated circuit. Materials with low dielectric constants are used like gap layer dielectrics (ILDs) in integrated circuits to reduce line-to-line capacitance.

The problem of increasing C _LL can work on a dual damascene conductor structure incorporating trenches and vias. Thus, materials with low dielectric constants (low-kay) are used for the double damascus structure. One technique uses a low-k dielectric monolayer for the trench and via layers. While line-to-line capacitance is reduced with the use of a single low-k dielectric layer, the fabrication of a double damascus structure with a single low-k layer can be difficult. The processing step requires a trench etch to be controlled very preferably. The trench etch should have good internal wafer and wafer to wafer uniformity, and the etch ratio should be independent of the trench width. In addition, the lower portion of the trench is generally planar. The foregoing makes it difficult to obtain using various conventional etching tools.

Another technique for incorporating low-k materials of dual damascus structure employs an etch-interruption layer between the trench and via layers (also, the same material uses trench and via layers). While the etch-stop layer selects a high etch between the trench dielectric layer and the via dielectric layer, the etch stop process becomes relatively difficult. The etch-stop layer adds another step to the processing of the deposition, and in many cases the deposition tools required for the stop etch are not the same tools used for the deposition of the trench dielectric and the via dielectric. The above increases the time and cost of the manufacturing method. After all, it is difficult to control the three-layer film stack because the measurement of the optical film thickness is made difficult like a complicated structure.

In addition to the drawbacks described above, many of the low-k dielectric materials available have the disadvantage of being soft compared to silicon oxide, which is difficult to process.

Thus, there is a need for fabrication techniques to fabricate low-k layers of integrated circuits.

The present invention is directed to a method of manufacturing a multilayer dielectric that reduces line to line capacitance (C _LL ). The method includes a first dielectric layer formed to provide a support for a second dielectric layer formed over the first dielectric layer. The second dielectric layer is low-k which can be formed between conductive elements such as a metal runner. Selective etching between two dielectric layers creates a manufacturing interconnect between the horizontals of multi-horizontal integrated circuits.

1 is a cross-sectional view of a preferred embodiment according to the present invention.

2 (a) to 2 (e) are cross-sectional views of a preferred embodiment according to the present invention showing the sequence of the manufacturing method.

3 shows a preferred embodiment of the present invention.

4 shows a preferred embodiment of the present invention.

* Description of Symbols for Major Parts of Drawings

100 substrate 101 first dielectric layer

102: second dielectric layer 103: conductive element

203: via layer 204: trench layer

206: photoresist layer 301: via photoresist

In summary, the present invention relates to a method for manufacturing a multilayer dielectric using an integrated circuit with reduced plastic capacitance in an integrated circuit. In FIG. 1, a first dielectric layer 101 is formed over a substrate 100, and a second dielectric layer 102 is formed over the first dielectric layer 101. The first dielectric layer 101 provides structural support for the second dielectric layer to have good thermal conductivity. The second dielectric layer is a material having a low dielectric constant (low-k). The low-k layer 102 is formed between the conductive elements 103 to create a reduction in the plastic capacitance between the conductive elements.

In the preferred embodiment shown in Figure 1, the present invention reduces the C _LL between conductive elements 103, which can be a metal runner. The first dielectric layer 101 may be referred to as a structural layer, and the second dielectric layer 102 may be referred to as a low-k dielectric layer. In the preferred embodiment shown in FIGS. 2 (a) -2 (e), 3 and 4, a dual damascus structure with reduced line-to-line capacitance is known. In embodiments describing the dual damascus structure, the first dielectric layer may be referred to as the via dielectric because it is a via formed layer, and the second dielectric layer may be referred to as a trench dielectric because it is a trenched layer. As a result, the preferred fabrication technique for forming the structure shown in FIG. 1 is substantially the same as using via dielectric and trench dielectric for the preferred embodiment described below.

In FIG. 2A, the substrate 201 has a conductive element 202 deposited over the substrate by standard techniques. The substrate can be a dielectric metal or a semiconductor such as silicon, GaAs or SiGe as well as other metals used to fabricate integrated circuits. Via layer 203 is formed over substrate 201 by conventional deposition techniques and has a good thickness between 600 nm and 900 nm. By way of example, the via layer is formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD). Via dielectric material is selected for the mechanical, thermal and plasma etching of the material. Finally, the via layer provides mechanical stability / strength to the trench layer 204. In addition, the via layer 203 may dissipate higher heat than the trench dielectric material and may be etched at a different rate than the trench dielectric described below. Materials with low modulus in the range of about 60 GPa to 120 GPa and thermal conductivity in the range of about 9.0 mW / cm-K to 17.0 mW / cm-K can be used with the via dielectric layer. Preferred materials include, but are not limited to, silicon dioxide and fluorine doped silicon dioxide (known as fluorosilicate glass (FSG)).

After forming the via dielectric, the trench dielectric 204 is formed over the via dielectric with a good thickness of 300 nm to 800 nm. Trench dielectric layers can be deposited by PECVD as well as standard rotation in the art. Preferred trench dielectric materials are low dielectric organic polymers (e.g., DOW Chemical's trademark, SILK), hybrido organo siloxane polymers (e.g., signal association Corporate trade name, HOSP), nanoporousous silicate glass (e.g., signal federation company tradename, Nanoglass) and organic silicate glass (e.g., material association company tradename, COREL). In a preferred embodiment, the dielectric constant of layer 204 is less than the dielectric constant of layer 203. For example, the trench layer 204 may have a dielectric constant of about 2.0 to about 3.7. However, what has been described above may be within the scope of the present invention using a material such as trench dielectric 203 having a dielectric constant of less than 2.0. Low-k trench dielectrics reduce the overall dielectric constant of the interlayer dielectric (ILD) by reducing line-to-line capacitance as is known.

2B shows via 205. In a preferred embodiment, the etching of the vias 205 is performed by reactive theoretical etching. The etching can be performed by known techniques to achieve vertical side etching. The via etch method ends before the bottom passivation layer (not shown) of the underlying layer located over the conductive element 202. As a result, the conventional chemistry used to etch silicon dioxide and FSG is used in the via etch step.

As shown in Fig. 2C, the photoresist layer 206 is defined and used as a trench. In FIG. 2 (d), trench 207 is shown to be etched by reactive ion etching using a method that provides a high selectivity between trench layer 204 and via layer 203. Thus, the complexity of having an etch-stop layer may be preceded by the prior art as required.

Examples of etching chemistries for any good material are described below. As an example, SILK When a pure organic material such as is used in the trench layer 204 and the via layer is SiO ₂ or FSG, the use of an etching chemistry comprising oxygen and hydrogen (fluorine) may provide an etch selectivity of about 20: 1. will be. When the trench layer 204 is nanoglass (porous SiO ₂ ) and the via layer 203 is SiO ₂ or FSG, conventional oxide etch chemistries such as CHF ₃ / CF ₄ or C ₄ F ₈ / CO may be applied to the layer ( An etching selectivity of about 4: 1 is provided between 204 and layer 203.

As a result, the etch selectivity improves the control of trench depth in the wafer from wafer to wafer results. Further, etching of the trench 207 is performed to achieve vertical side etching. As a result, the trench etch can use an endpoint detection technique as known to those skilled in the art to finish the etch after reetching the via. As a result, the double damascus structure is shown in FIG. 2E after vias 205 and trenches 207 fill conductor 208 by standard techniques.

3 and 4 show another manufacturing technique within the scope of the present invention. The materials and methods using the other embodiments shown in FIG. 3 have substantially the same description of the structure, and filled vias are first made. 3 shows a preferred embodiment according to the known invention, wherein trenches are made through the selectivity between layers 203 and 204. After etching from trench layer 207 to trench layer 204, via photoresist 301 is deposited and filled via 205 is etched. In the structure shown in FIG. 4, some vias are formed as shown at 401. Afterwards, trench photoresist 402 is deposited over trench layer 204. The plasma etch step is then performed by standard techniques of the resulting trenches and filled vias.

Modifications and variations of the present invention will become apparent from the detailed description within the scope of the art. Such modifications are made within the scope of fabrication methods with reduced ILD dielectric constants through the use of known integrated circuits and multilayer dielectric structures.

Claims (23)

In the method of manufacturing an integrated circuit, Forming a multilayer dielectric over the substrate, Wherein said multilayer dielectric further comprises a structural layer and a low-k layer. The method of claim 1, And the low-k layer is formed between two or more conductive elements. The method of claim 1, Wherein said low-k layer has a dielectric constant on the order of 2.0 to 3.7. The method of claim 1, And wherein said low-k layer has a dielectric constant of less than 2.0. The method of claim 1, The low-k layer is SILK , HOSP, Nanoglass and Black Diamond. The method of claim 1, Wherein said structural layer is selected from the group consisting of SiO ₂ and fluorine doped silicon oxide. The method of claim 1, And said structural layer has a small coefficient in the range of 60 GPa to 120 GPa. In the method of manufacturing an integrated circuit, Depositing a layer on the substrate, Depositing a low-k over said layer, Etching vias in the layer, and Etching a trench in the low-k layer. The method of claim 8, Wherein said low-k layer has a dielectric constant on the order of 2.0 to 3.7. The method of claim 8, And wherein said low-k layer has a dielectric constant of less than 2.0. The method of claim 8, And said layer has a small coefficient in the range of 60 GPa to 120 GPa. The method of claim 8, And said layer is etched later than said low-k layer. The method of claim 8, At least one conductive element is deposited between the substrate and the layer. The method of claim 8, The low-k material is SILK , HOSP, nanoglass and black diamond. The method of claim 8, Wherein said layer is selected from the group consisting of SiO ₂ and fluorine doped silicon dioxide. The method of claim 8, And a conductive material is deposited in the via and in the trench. In the method of manufacturing an integrated circuit, Forming a multilayer dielectric over a substrate, the multilayer dielectric having a low-k layer formed over the structural layer and directly formed over one or more conductive elements. The method of claim 17, Wherein said at least one conductive element is formed over said structural layer. The method of claim 17, Wherein said low-k layer has a dielectric constant on the order of 2.0 to 3.7. The method of claim 17, And wherein said low-k layer has a dielectric constant of less than 2.0. The method of claim 17, The low-k layer is SILK , HOSP, nanoglass and black diamond. The method of claim 17, Wherein said structural layer is selected from the group consisting of SiO ₂ and fluorine doped silicon dioxide. The method of claim 17, And said structural layer has a small coefficient in the range of 60 GPa to 120 GPa.