KR20010027373A - Semiconductor having static memory cell array area and dynamic memory cell array area in the same memory area - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to prevent increment of access time due to larger memory capacity. CONSTITUTION: The device includes plural memory banks(A-BANK,A-BANK,A-BANK,A-BANK). In each memory bank(A-BANK,A-BANK,A-BANK,A-BANK), plural memory cells are arranged along row and column directions. A memory area of each memory bank(A-BANK,A-BANK,A-BANK, A-BANK) is divided into a dynamic memory-cell array area(102) and a static memory-cell array area(104). Memory cells to be selected by external addresses are located in the static memory-cell array area(104). Memory cells to be selected by internal addresses are located in the dynamic memory-cell array area(102). Thereby, increment of access time due to larger memory capacity can be prevented.

Description

Semiconductor memory device having a static and dynamic memory cell array area in the memory area {Semiconductor having static memory cell array area and dynamic memory cell array area in the same memory area}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a static memory cell array region and a dynamic memory cell array region in a memory cell region.

In accordance with the trend of higher integration of semiconductor memory devices, a technology for reducing the minimum unit of a memory device is rapidly developed. Thus, although the chip area can be reduced, the chip area is increased due to the increase in the area occupied by the memory array area as the capacity increases. Increasing the chip area increases the load of the internal signal lines, which inevitably leads to signal delays, thereby causing a problem of slowing the access time of the semiconductor memory device.

1 is a diagram schematically illustrating a semiconductor memory device including only a dynamic memory cell array region according to the related art. Referring to this, the semiconductor memory device 1 has a plurality of banks A-BANK, B-BANK, C-BANK, and D-BANK, and each of the banks A-BANK, B-BANK, and C-BANK. The memory cells in memory area 2 in D-BANK are selected by row decoder 10 and column decoder 20. The peripheral circuit unit and the pad area 30 include signal pads PAD, address buffers and output buffers connected to the signal pads, respectively, to control data input / output.

FIG. 2 is a diagram illustrating a general operation timing diagram of the semiconductor memory device of FIG. 1, and describes a method of outputting memory cell data in a pipeline structure. The applied commands, for example, a row active command, a column active command, and the like are synchronized with the clock signal CLK. However, the column active command should be applied after a predetermined time after the row active command, and this section is called tRCD. The memory cell data is output after the column active command. The time taken from the column active command to the output of the memory cell data corresponding to the external address is referred to as tAA. Subsequently, in order to satisfy the data output format of the pipeline structure, a counter for increasing or decreasing an external address internally is provided, and memory cell data corresponding to internal addresses are output.

The memory area 2 of FIG. 1 is an area in which dynamic memory cells are arranged, and the dynamic memory cell is shown in FIG. 3. The memory cell of FIG. 3 represents a general DRAM cell. That is, one transistor TR and one capacitor C are configured so that the gate G of the transistor TR is a word line, the drain D is a bit line BL, and the source S is It is connected to the storage electrode of the capacitor (C) and the plate electrode of the capacitor (C) is connected to the plate voltage (VP). In this DRAM cell structure, memory cell data is stored in a capacitor (C).

4 is a timing diagram illustrating an internal path in which tRCD of FIG. 2 is determined. Referring to this, when the word line WL is enabled by a row active command, data stored in the corresponding memory cell is transferred to the bit line and the complementary bit line BL / BLb. At this time, the voltage level of the memory cell data transferred on the bit line and the complementary bit line BL / BLb is determined by a charge sharing method. In this charge sharing method, the cell data stored in the capacitor (C, FIG. 2) of the DRAM cell is gradually transferred while being transferred to a bit line having a large load, and is activated by a column active command. In response to the selection signal CSLi, bit line and complementary bit line BL / BLb data having a certain voltage difference are transferred to the data line. Here, the charge distribution time takes a lot of time in determining tRCD. Therefore, as the area of the chip increases with the increase in the capacity of the semiconductor memory device, the increased bit line load has a problem of lengthening the tRCD time to slow the access time of the semiconductor memory device.

Therefore, even if the semiconductor memory device is increased in capacity, a memory architecture in which the access time, in particular, the tRCD time is not increased is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of combining static and dynamic memory cell array regions in a memory region, thereby preventing an increase in access time due to a large memory capacity.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram schematically illustrating a semiconductor memory device including only a dynamic memory cell array region according to the related art.

FIG. 2 is a diagram illustrating an operation timing diagram of the semiconductor memory device of FIG. 1.

3 is a diagram illustrating the dynamic memory cell of FIG. 1 in detail.

4 is a timing diagram illustrating an internal path in which tRCD of FIG. 2 is determined.

5 is a diagram illustrating a semiconductor memory device having dynamic and static memory cell array regions in a memory cell region according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a static memory cell of FIG. 5.

FIG. 7 is a diagram schematically illustrating a memory cell addressing method in one bank A-BANK.

FIG. 8 is a diagram schematically illustrating a connection relationship from the column address buffer of FIG. 7 to an internal column address counter.

9 is a diagram illustrating an operation timing diagram of FIG. 6.

In order to achieve the above object, the present invention provides a semiconductor memory device having a plurality of memory blocks and inputting and outputting memory cell data in a selected memory block, the internal memory receiving a plurality of internal addresses and generating a plurality of internal addresses sequentially increased or decreased. With an address counter, a static memory area and a dynamic memory area within each memory block, a memory cell selected by an external address is located in the static memory area and is selected by internal addresses. The cell is located in the dynamic memory area.

Preferably, the memory cell data corresponding to the external address and the internal addresses are suitably input and output in a pipelined structure.

According to the present invention, the first data output in response to the external address is the data output from the static memory cell array area, and the data output from the conventional dynamic memory cell array area due to the characteristics of the static memory cell, that is, SRAM, Since the required charge distribution time is not needed, even if the memory capacity of the semiconductor memory device is increased, the access time, in particular the tRCD time, is no longer increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

FIG. 5 is a diagram schematically illustrating an overall architecture of a semiconductor memory device according to an embodiment of the present invention. Referring to this, the semiconductor memory device 100 includes a plurality of memory blocks, a so-called banks A-BANK, B-BANK, C-BANK, and D-BANK, and each of the banks A-BANK, B. -BANK, C-BANK, and D-BANK have a memory area in which a plurality of memory cells are arranged in rows and columns. The memory area in each of the banks A-BANK, B-BANK, C-BANK, and D-BANK is divided into a dynamic memory cell array area 102 and a static memory cell array area 104. In the array region 102, a DRAM cell, which is the dynamic memory cell of FIG. 3, described above, and an SRAM cell, which is a static memory cell, are arranged in the static memory cell array region 104. The SRAM cell is shown in FIG. 6.

In the SRAM cell of FIG. 6, two resistors R1 and R2 connected to the power supply voltage VCC, drains are connected to the respective resistors R1 and R2, and the gates of the resistors R1 and R2 are connected to each other. ) Are cross-connected to each other, and the sources are connected to the cross transistors TR1 and TR2 to which the ground voltage VSS is connected, and to the drains of the resistors R1 and R2 and the cross transistors TR1 and TR2. Pass transistors TR3 and TR4 gated to the word line WL. The configuration of the SRAM is general, and may alternatively be composed of six transistors including inverter cells that are closed-circuit using PMOS transistors instead of two resistors R1 and R2.

In this operation of the SRAM cell, when the word line WL is activated to the “high level”, the bit line BL data and the data of the complementary bit line BLB having a logic level opposite thereto pass through the transistors TR3. The logic levels of the nodes A and B are transferred to the nodes A and B through TR4, and the logic levels of the nodes A and B are maintained and stored by the cross transistors TR1 and TR2. Thus, data is stored in the SRAM cell.

In addition, even when the SRAM cell includes six transistors including inverter cells, cell data is stored while being latched to each other by the inverter cells. Therefore, the cell data stored in the SRAM cell is represented by a logic level having a complete voltage level, that is, a power supply voltage (VCC) level when "high" data, and a ground voltage (VSS) level when "low" data.

Therefore, unlike the DRAM cell described with reference to FIG. 3, the SRAM cell requires a time for cell data to sense and amplify its voltage level through charge distribution on the bit line BL and the complementary bit line BLB. I never do that. This means that the SRAM cell has a shorter data access time than the DRAM cell.

Referring again to FIG. 5, memory cells of each of the banks A-BANK, B-BANK, C-BANK, and D-BANK are addressed by the row decoder 110 and the column decoder 120. The row decoder 110 and the column decoder 120 decode predetermined row addresses and column addresses input from the outside to memory cells in the banks A-BANK, B-BANK, C-BANK, and D-BANK. Select.

Predetermined row addresses and column addresses are received in the address buffers (not shown), and memory cell data selected by the row decoder 110 and the column decoder 120 is a data input / output line (not shown). And an output buffer (not shown) to the pad. The address buffers (not shown) and output buffers (not shown) are disposed in the center of the semiconductor memory device 100, that is, in the peripheral circuit portion and the pad region 130.

FIG. 7 is a diagram schematically illustrating a memory cell addressing method in one bank A-BANK. As described above, the memory area is divided into a dynamic memory cell array area 102 and a static memory cell array area 104. The column addresses A0 to AN applied from the outside are directly provided to the column address generator 107 through the column address buffer 106 or the column address generator through the column address buffer 106 and the internal column address counter 108. 107 is provided.

The path in which the column addresses A0 to AN are directly provided to the column address generator 107 through the column address buffer 106 is a memory cell corresponding to the first column address A0 to AN applied externally. The path is set to be located in the array region 104. The path provided to the column address generator 107 through the column address buffer 106 and the internal column address counter 108 is such that the first column addresses A0 to AN applied from the outside are sequentially ordered in the internal column address counter 108. Increase, decrease according to the second, third,… In this case, the memory cells corresponding to the N-th internal column addresses are set in the dynamic memory cell array region 102. Specifically, an internal address generation path is illustrated in FIG. 8 according to each column address received, and thus an operation timing diagram of the semiconductor memory device of FIG. 5 is illustrated in FIG. 9.

Referring to FIG. 9, an output is performed to a data line in response to a row address X-Addr input by a row active command synchronized with a clock signal CLK and a column address Y-Addr input by a column active command. The first data to be output is the data output from the static memory cell array area corresponding to the row address X-Addr and the column address Y-Addr. The data output thereafter is data output from the dynamic memory cell array area corresponding to the internal addresses sequentially increased by the internal column address counter receiving the column address Y-Addr as described with reference to FIG. 8.

In the semiconductor memory device having both the static and dynamic memory cell array regions of the present invention, data output in response to a row address (X-Addr) and a column address (Y-Addr) received from the outside is a static memory cell array region. Since the data is outputted from, the charge distribution time required for data output from the conventional dynamic memory cell array region is not necessary due to the characteristics of the static memory cell, that is, the SRAM described in FIG. 6. Therefore, even if the memory capacity of the semiconductor memory device is increased, the access time, especially the tRCD time, is no longer increased.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the semiconductor memory device having both the static and dynamic memory cell array regions of the present invention described above, since the data output in response to the row address and column address received from the outside are the data output from the static memory cell array region, the static memory cells That is, due to the characteristics of the SRAM, the charge distribution time required for data output from the conventional dynamic memory cell array region is not required. Therefore, even when the memory capacity of the semiconductor memory device is increased, the access time, in particular, the tRCD time, is no longer increased.

Claims (3)

A semiconductor memory device having a plurality of memory blocks and inputting / outputting memory cell data in a selected memory block, An internal address counter that receives an external address and generates a plurality of internal addresses that are sequentially incremented; And Each memory block includes a static memory area and a dynamic memory area, And the memory cell selected by the external address is located in the static memory area, and the memory cell selected by the internal addresses is located in the dynamic memory area. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And memory cell data corresponding to the external address and the internal addresses are input / output in a pipelined structure. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And reducing the tRCD time from a row address active command to a column address active command when the external external address is input.