KR20010026926A - Universal serial bus transmitter of computer system - Google Patents

Abstract

PURPOSE: The USB(Universal Serial Bus) transmitter of the computer system is provided to output the stable output data about the external change by controlling the crossing point of the output data. CONSTITUTION: The USB(Universal Serial Bus) transmitter of the computer system comprises a control circuit(100), a bias voltage generating/clamping circuit(200), and an output buffer(300). The control circuit receives the data(NRZI) from the outside, and generates the complementary first and second data(DM,DP) and the bias enable signal(BIAS_ENH) by responding to the transmission enable signal(ENL) and the first and the second control signal(EOP, XCON). The output buffer includes the first and the second output buffer(310,320). Each output buffer(310,320) receives the first, second, third, and forth bias voltage(PBIAS1, PBIAS2, NBIAS1, NBIAS2), and outputs the variable output data(DM_OUT, DP_OUT) according to the voltage level of the first and the second clamping signal(SUMP, SUMM). So, the USB transmitter outputs the stable output data(DM_OUT, DP_OUT) about the external change by controlling the crossing point of the output data according to the control of the XCON, the SUMP, and the SUMM.

Description

USEBI transmitter of computer system {UNIVERSAL SERIAL BUS TRANSMITTER OF COMPUTER SYSTEM}

The present invention relates to a computer system, and more particularly to a USB transmitter of the computer system.

The universal serial bus (USB) solves many of the problems associated with connecting traditional personal computers (PCs) and peripherals (e.g. keyboards, mice, etc.) and allows Intel to implement a better multimedia environment. Intel is a new interface standard between PCs and peripherals, jointly developed by companies such as Microsoft, Compaq, and NEC.

The USB has two data transmission / reception lines D + and D− for transmitting and receiving signals, and a cable having two power lines VDD and GND for power supplies VDD and GND is used. However, the USB has two wires (D + and D-) for transmitting and receiving signals, and are specified at speeds of up to 5 meters per unit cable and at a speed of 1.5 Mbps (low speed) or 12 Mbps (full speed). Since data must be transmitted and received according to the protocol, a USB transmitter having a structure different from that of a conventional transmitter is required.

These specifications were first defined by the "USB Serial Bus Specification V1.0" on January 15, 1996, and after many field tests, the "USB Serial Bus Specification V1. Was revised to 1 ". Existing passive buffers or out buffers that meet the USB SPEC V1.0 have met certain tiers under certain loading conditions, but USB low speed buffers (USB) As in SPEC V1.1, p111, and p145, various load capacitance variations from 200 pF to 600 pF, pull-up / down resistors, operating voltage, temperature and Even with changes in the production process, it is practically difficult to provide a stable output buffer that satisfies the USB SPEC.

Referring to FIG. 1, a general USB transmitter is provided with controllers 10 and 20 that process, ie, control data DM and DP, respectively. These controllers 10 and 20 control the output buffers, i.e., the output drivers 30 and 40, respectively, and output the output data DM_OUT and DP_OUT corresponding to the data DM and DP. However, there is a problem in that the USB transmitter having such a structure cannot adjust a crossing point of the output data DM_OUT and DP_OUT in response to the condition change.

Accordingly, it is an object of the present invention to provide a USB transmitter suitable for the new USB protocol.

1 is a conceptual diagram of a USB transmitter of a general computer system;

2 is a conceptual diagram of a USB transmitter of a computer system according to the present invention;

3 is a block diagram of a USB transmitter of a computer system according to the present invention;

4 is a detailed circuit diagram of the control circuit of FIG. 3;

5 is a detailed circuit diagram of the bias voltage generation and clamp circuit of FIG. 3;

FIG. 6 is a circuit diagram on top of the first output buffer of FIG. 3.

* Explanation of symbols on the main parts of the drawings

100: control circuit 200: bias voltage generation and clamp circuit

300: output buffer

(Configuration)

According to one aspect of the present invention for achieving the object as described above, the USB transmitter of the computer system according to the present invention accepts mutually complementary first and second data from the outside and transmit transmission signal, first, second And control means for generating a bias-activated signal and said first and second data having been converted in format in response to a third control signal; Generating an output activation signal and first, second, third and fourth bias voltages swinging between a predetermined voltage level in response to the bias activation signal and first and second clamp signals from the control means. Bias voltage generation and clamp means; Accept the first and second data and the first, second, third and fourth bias voltages, generate the first and second clamp signals in response to the output activation signal, and generate the first and second clamp signals. Output means for outputting mutually complementary third and fourth data corresponding to data, each of said third and fourth data having a voltage level that varies with the voltage level of said first and second clamp signals; .

In this embodiment, the output means accepts the first data and the first, second, third and fourth bias voltages and outputs the first clamp signal and the third data in response to the output activation signal. A first output buffer, and a second receiving the first data and the first, second, third and fourth bias voltages and outputting the second clamp signal and the fourth data in response to the output activation signal. Contains an output buffer.

(Action)

By such a device, the crossing point of the output data is adjusted, so that output data stable against external changes is output.

(Example)

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, the USB transmitter according to the present invention includes a control circuit 100, a bias voltage generation and clamp circuit 200, and an output buffer 300. The control circuit 100 receives data NRZI from the outside, and complementary to each other the first and second data mutually complementary in response to the transmission activation signal ENL and the first and second control signals EOP and XCON. DM, DP) and a bias activation signal (BIAS_ENH). In this case, an output time point of the first and second data DM and DP is controlled by the second control signal XCON. In response to the bias activation signal BIAS_ENH from the control circuit 100 and the first and second clamp signals SUMP and SUMM from the output buffer 300, the output activation signal DOEH and the first, Generate second, third and fourth bias voltages PBIAS1, PBIAS2, NBIAS1 and NBIAS2. The output buffer 300 includes first and second output buffers 310 and 320. Each of the output buffers 310 and 320 receives the first, second, third and fourth bias voltages PBIAS1, PBIAS2, NBIAS1, and NBIAS2 and receives the output activation signal DEOH and the first and second. In response to the clamp signals SUMP and SUMM, output data DM_OUT and DP_OUT that are variable according to voltage levels of the first and second clamp signals SUMP and SUMM are output. As described above, the USB transmitter according to the present invention adjusts the crossing points of the output data DM_OUT and DP_OUT by controlling the second control signal XCON and the first and second clamp signals SUMP and SUMM. As a result, output data DM_OUT and DP_OUT stable to external changes are output.

3 to 5, the USB transmitter of the computer system according to the present invention includes a control circuit 100, a bias voltage generation and clamp circuit 200, and an output buffer 300. As illustrated in FIG. 4, the control circuit 100 includes a filter circuit 110, a first logic circuit 120, a delay circuit 130, and a second logic circuit 140. The filter circuit 110 includes inverters 111, 113, and 115 and filters 112, 114, and 116, and transmits an external transmission enable signal ENL, an initialization signal EOP, and input data NRZI. Filter out the noise and glitch contained in the.

The first logic circuit 120 includes inverters 121, 122, 123, and 125 and end gates 124 and 126, and transmits a transmission activation signal ENL outputted from the filter circuit 110 and initializes the initialization logic signal 120. Invert, delay, and logically operate on signals EOP and data NRZI. The delay circuit 130 includes first and second delay circuits 131 and 132, and may be formed from the AND gates 124 and 126 in response to an external control signal XCON <0: 5>. Delays the output signals. The second logic circuit 140 includes end gates 141 and 143 and or gates 142 and 144, and a transmission activation signal ENL and the delay circuit 130 from the filter circuit 110. Logic output signals of the first logic circuit 120 delayed by

The bias voltage generation and clamp circuit 200 includes a bias voltage generation circuit 210 and a clamp circuit 220. The bias voltage generation circuit 210 is configured to MOS transistors PM1, PM2, ..., PM6, PM7, NM1, NM2, ..., NM6, NM7 and resistors R1, R2, R3, R4. And first, second, third, and fourth bias voltages PBIAS1, PBIAS2, NBIAS1, and NBIAS2 and midpoint voltage CNTR by controlling the bias activation signal BIAS_ENH from the control circuit 100. Occurs. The clamp circuit 220 includes MOS transistors PM8, PM9, NM8, and NM9, wherein the midpoint is controlled by the control of the first and second clamp signals SUMP and SUMM from the output buffer 300. The voltage level of the voltage CNTR is clamped between the predetermined voltage levels.

The output buffer 300 includes first and second output buffers 310 and 320, and draws data DM and DP and an output activation signal DOEH from the control circuit 100 and the bias voltage. Accepts the first, second, third and fourth bias voltages PBIAS1, PBIAS2, NBIAS1, NBIAS2 and midpoint voltage CNTR from the generation and clamp circuit 200 to correspond to the data DM, DP. Output data DM_OUT and DP_OUT.

3 to 5, the operation of the USB transmitter of the computer system according to the present invention is described.

3 to 5, the control circuit 100 of the USB transmitter according to the present invention operates as a function controller, and the USB transmitter may be operated by input signals. It is a block that generates control signals. Signals ENL, EOP, NRZI, and XCON are used as input signals of the control circuit 100, and various control signals DOE, DM_P_EN, DM_P_ENB, DM_N_EN, and DM_N_ENB are output as output signals. The function of the control circuit 100 is as shown in the following table.

[table]

INPUT OUTPUT STATE ENL NRZI EOP DM DP One X X Z Z high impedance 0 X One 0 0 signalendzero 0 0 0 One 0 diff zero 0 One 0 0 One diff one

Although the original output data DM_OUT and DP_OUT output from the USB transmitter are two, in the control circuit 100 of the USB transmitter of the present invention, instead of the data DM and DP, a signal having a form defined in USB SPEC is used. Signals NRZI, EOP were used. Signals of this type NRZI and EOP have an advantage of reducing time difference jitter between signals that may be generated in a manufacturing process.

Among the signals, the signal XCON is an input signal for controlling the cross point of the data DM and DP presented by the USB SPEC, and the delay circuit 130 of the control circuit 100 is controlled to change the manufacturing process. It compensates for the change of cross point. The signal ENL is a transmission activation signal for operating the USB transmitter. The signal EOP is a signal for making the output data DM_OUT and DP_OUT of the USB transmitter to the mode logic low according to the USB SPEC. The signal NRZI serves to output the output data DM_OUT and DP_OUT according to the USB SPEC according to a given signal.

The bias voltage generation and clamp circuit 200 serves as a voltage source of the output buffer 300. The output buffer 300 allows stable output data DM_OUT and DP_OUT to be output from the USB transmitter of the present invention. Since the first and second output buffers 310 and 320 of the output buffer 300 have a similar configuration, the operation of the first output buffer 310 will be described in this description.

The first output buffer 310 is output from the integration using the amplifiers OP1 and OP2 and the feedback using the capacitor C and from the bias voltage generation and clamp circuit 200. The concept of virtual ground of the midpoint voltage CNTR and clamp signal SUM is used.

The first output buffer 310 draws an output activation signal DOEH and data DM, DP from the control circuit 100 and first, second, and second signals from the bias voltage generation and clamp circuit 200. The third and fourth bias voltages PBIAS1, PBIAS2, NBIAS1 and NBIAS2 and the midpoint voltage CNTR are received to output the output data DM_OUT and DP_OUT and the first clamp signal SUMM.

First, it is assumed that the midpoint voltage CNTR maintains the VDD / 2 value by the bias voltage generation and clamp circuit 200, and the first clamp signal SUMM also has the value of VDD / 2. At this time, when a change of the output data DM_OUT occurs due to the operation of the USB transmitter, the feedback current I _fb corresponding to the first clamp voltage SUMM is transferred through the capacitor C as shown in the following equation. It is fed back to the amplifiers OP1 and OP2.

[expression]

I _fb = C _fb (dv / dt)

That is, when the slope of the output data DM_OUT is too small, the amount of feedback current I _fb fed back through the capacitor C may cause the bias voltage generation and the voltage level of the midpoint voltage CNTR from the clamp circuit 200. Is less than the amount of current corresponding to. As a result, the voltage level of the first clamp voltage SUMM becomes higher than VDD / 2. The change in the first clamp voltage SUMM causes a change in the voltage level of the output signal PDRVM of the amplifier OP2, thereby increasing the magnitude of the current flowing through the NMOS transistor NM5. As such, the current flowing through the NMOS transistor NM5 is increased, so that the slope of the output data DM_OUT is increased.

Conversely, if the slope of the output data DM_OUT is too large, the amount of feedback current I _fb flowing through the capacitor C corresponds to the bias voltage generation and the voltage level of the midpoint voltage CNTR from the clamp circuit 200. It becomes more than the amount of current to make. Accordingly, the voltage level of the first clamp voltage SUMM is lower than VDD / 2, and the change in the first clamp voltage SUMM generates a change in the voltage level of the output signal PDRVM of the amplifier OP2. As a result, the amount of current flowing through the PMOS transistor PM4 is increased. As such, the current flowing through the PMOS transistor PM4 is increased, so that the slope of the output data DM_OUT is increased.

As described above, the USB transmitter of the computer system according to the present invention controls the crossing points of the output data DM_OUT and DP_OUT by controlling the control signal XCON and the first and second clamp signals SUMP and SUMM. By adjusting, the output data DM_OUT and DP_OUT stable to external changes are output.

In the above, although the USB transmitter of the computer system according to the present invention has been shown according to the above description and drawings, this is merely an example, and various changes and modifications are possible without departing from the technical idea of the present invention.

As described above, by adjusting the crossing point of the output data, output data that is stable against external changes is output.

Claims (2)

A control that accepts mutually complementary first and second data from outside and generates a transformed first and second data and a bias enabled signal in response to a transmission activation signal, first, second and third control signals Means; Generating an output activation signal and first, second, third and fourth bias voltages swinging between a predetermined voltage level in response to the bias activation signal and first and second clamp signals from the control means. Bias voltage generation and clamp means; Accept the first and second data and the first, second, third and fourth bias voltages, generate the first and second clamp signals in response to the output activation signal, and generate the first and second clamp signals. Output means for outputting mutually complementary third and fourth data corresponding to the data, Each of the third and fourth data is And a voltage level that varies with the voltage levels of the first and second clamp signals. The method of claim 1, The output means, A first output buffer receiving said first data and said first, second, third and fourth bias voltages and outputting said first clamp signal and said third data in response to said output activation signal; And a second output buffer receiving the first data and the first, second, third and fourth bias voltages and outputting the second clamp signal and the fourth data in response to the output activation signal. USB transmitter.