KR20010026905A - Infrared signal receiver - Google Patents

Abstract

PURPOSE: An infrared signal receiver is provided to receive finite impulse response infrared signals to correctly recover original pulse signal. CONSTITUTION: The receiver(1) includes a delay(10) for receiving an infrared signal to delay the signal for a predetermined period of time, and a detector for detecting the rising edge of the delayed infrared signal. The infrared signal receiver further has a state machine(30) for generating a pulse signal having a predetermined pulse width in response to the delayed infrared signal and the rising edge detection signal, and a digital phase locked loop(40) for receiving the pulse signal to generate a pulse signal synchronized with an inner clock signal. The state machine judges the infrared signal to be a single pulse or double pulse based on the level of the delayed infrared signal to output a corresponding status signal when the pulse signal synchronized with the inner clock signal is changed from the first level to the second level. The state machine outputs the pulse signal synchronized with the inner clock signal as an infrared detection signal in response to the status signal.

Description

Infrared signal receiver {INFRARED SIGNAL RECEIVER}

The present invention relates to an infrared communication system, and more particularly, to an infrared signal receiver for receiving an infrared signal and detecting a finite impulse response (FIR) pulse signal.

An infrared communication system is a communication system that transmits and receives data wirelessly using infrared rays, and may perform wireless communication at speeds of up to 4 Mbps. The transmitting side of the infrared communication system converts an electrical signal in the form of a digital pulse into an infrared signal in the form of a FIR pulse and emits it into the air. The receiving side receives the FIR infrared signal radiated wirelessly and restores the original pulse train. However, there is a problem that the pulse widths of the infrared signals radiated from the transmitter of the infrared communication system vary depending on the characteristics of the transmitter.

In other words, if the active area width of the FIR infrared signal emitted into the air is 'Δ', then the received infrared signal may have a significant shift from this value.

The FIR pulse signal transmitted wirelessly from the infrared transceiver follows the 4 PPM method according to Infra-Red Data Association (IrDA) standard protocol V1.1. 4 PPM pulse signals are shown in Table 1 below.

TABLE 1

According to the standard protocol, a receiver receiving a 4 Mbps FIR signal modulated by the 4PPM scheme is defined to receive a signal that is changed within a range of 115 to 135 ns based on a pulse width of 125 ns. However, according to the characteristics of the infrared receiver actually used, the width of the digital pulse signal recovered from the infrared pulse is very widely distributed from the minimum of 60 ~ 80ns to the maximum of 165 ~ 185ns. Therefore, the infrared receiver needs to extract valid data among the received pulse signals.

One bit data (for example, '0' or '1') has a pulse width of 60 to 165 ns, which is called a single pulse. '11', in which two 1-bit data '1' are consecutively attached, has a pulse width of 185 to 300 ns, which is called a double pulse.

The infrared signal receiver must be able to accurately distinguish between single and double pulses when a single pulse and a double pulse are received randomly.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and to provide an infrared signal receiver that receives an FIR infrared signal emitted into the air and accurately restores the original pulse signal.

1 is a block diagram showing a circuit configuration of an infrared signal receiver according to a preferred embodiment of the present invention; And

FIG. 2 is an operation timing diagram of the infrared signal receiver shown in FIG. 1.

* Description of the symbols for the main parts of the drawings *

10: delay circuit and edge detector 20: 4-bit counter

30: state machine 40: DPLL circuit

According to a feature of the present invention for achieving the object of the present invention as described above, a receiver for receiving an infrared signal comprises: delay means for receiving the infrared signal and delaying it for a preset time; Detection means for detecting a rising edge of the infrared signal delayed by the delay means; A state machine for generating a pulse signal having a predetermined pulse width in response to the infrared signal delayed by the delay means and the rising edge detection signal detected by the detection means; And a digital phase locked loop that receives the pulse signal and generates a pulse signal synchronized with an internal clock signal. The state machine determines the infrared signal as a single pulse or a double pulse according to the level of the infrared signal delayed by the delay means when the pulse signal synchronized with the internal clock signal transitions from the first level to the second level. A corresponding state signal is output, and a pulse signal synchronized with the internal clock signal is output as an infrared detection signal in response to the state signal.

In a preferred embodiment, the counter further includes a counter that counts in response to a count enable signal.

In this embodiment, the state machine activates the count enable signal in response to the rising edge detection signal. Further, when the infrared signal delayed by the delay means is the first level when the count value input from the counter is a predetermined value, a status signal indicating that the infrared signal is a single pulse is output, and the count enable signal is deactivated. On the other hand, when the infrared signal delayed by the delay means is the second level when the count value input from the counter is the predetermined value, a status signal indicating that the infrared signal is a double pulse is output, and the activation state of the count enable signal is activated. Keep it.

Such a device not only accurately determines whether the received infrared signal is a single pulse or a double pulse, but also synchronizes the received signal with the DPLL clock signal of the DPLL circuit even if the pulse width of the received infrared signal is widely distributed. By doing so, an infrared signal receiver capable of accurate signal detection can be implemented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a circuit configuration of an infrared signal receiver according to a preferred embodiment of the present invention, and FIG. 2 is an operation timing diagram of the infrared signal receiver shown in FIG. Referring to FIG. 1, the infrared signal receiver 1 demonstrates an infrared signal rxdata input from the outside for a predetermined time, detects a rising edge of the infrared signal, and outputs an edge detection signal edge_sig. Delay circuit and edge detector 10, 4-bit counter 20, the delayed signal received from the delay circuit 10 receives a single pulse (single pulse) and double pulse (double pulse), and three states A state machine 30 for outputting signals states_b [0] to state_b [2], and a digital phase locked loop (DPLL) circuit 30 are included. The delay circuit and the edge detector 10, the 4-bit counter 20, the state machine 30, and the DPLL circuit 40 operate by receiving a reference clock signal sclk.

The delay circuit and the edge detector 10 delay the infrared signal rxdata received from the outside for a predetermined time, and synchronize the delayed signal with the falling edge of the reference clock signal sclk. Then, the synchronized signal rxdata_syn is provided to the state machine 30. In addition, the rising edge of the synchronized signal rxdata_syn is detected and an edge detection signal edge_sig of an activation level (eg, a high level) is provided to the state machine 30.

The state machine 30 generates a pulse signal rxd having a predetermined pulse width when the synchronized signal rxdata_syn is input from the delay circuit 10, and generates the pulse signal rxd into the DPLL circuit ( 40). The DPLL circuit 40 oversamples the pulse signal rxd four times, and then provides the DPLL clock signal dpll_clk and data dpll_data back to the state machine 30. The data dpll_data output from the DPLL circuit 40 is a signal obtained by synchronizing the pulse signal rxd with the clock signal dpll_clk. Meanwhile, the state machine 30 activates the counter enable signal count_ena when generating the pulse signal rxd.

The 4-bit counter 20 starts counting from decimal '1' in response to the counter enable signal count_ena input from the state machine 30.

The state machine 30 determines the counter according to the state of the signal rxdata_syn input from the delay circuit and the edge detector 10 when the count value input from the counter 20 is a decimal number '4'. The enable signal count_ena is changed. That is, when the count value counter is a decimal number '4', if the signal rxdata_syn input from the delay circuit and the edge detector 10 is in an inactive level, the counter enable signal count_ena is inactivated and the signal is disabled. If (rxdata_syn) is an activation level, the counter enable signal count_ena is maintained at an activation level.

The counter 20 is initialized to a decimal number '0' when the counter enable signal count_ena is deactivated.

The state machine 30 outputs the first state signal state_b [0] to an activation level (for example, a high level) in a normal state, and the edge detection signal edge_sig is an activation level. The second state signal state_b [1] is output at an activation level. When the signal 'rxdata_syn' input from the delay circuit and the edge detector 10 is still maintained at the activation level when '4' is input from the counter 20, the third state signal state_b [2] is supplied. Output to the activation level.

In other words, if the count value input from the counter 20 is less than or equal to '4', the state machine 30 converts the signal rxdata_syn input from the delay circuit and the edge detector 10 into a single pulse. If the count value is greater than the decimal number '4', the signal rxdata_syn input from the delay circuit and the edge detector 10 is recognized as a double pulse. The state machine 30 outputs the third state signal state_b [2] at an activation level when the signal rxdata_syn is recognized as a double pulse.

The state machine 30 receives the data dpll_data and the clock signal dclk_out from the DPLL circuit 40 and outputs the data dpll_data as an infrared detection signal dpll_out. At this time, if the third state signal state_b [2] is in an inactive level, the data dpll_data input from the DPLL circuit 40 is output as it is as the infrared detection signal dpll_out, and the third state signal ( When state_b [2]) is at the activation level, the data dpll_data input from the DPLL circuit 40 is delayed for two clock cycles and output as a double pulse signal.

For example, the case where the reference clock signal CLK is 32 MHz and the delay time of the delay circuit and the edge detector 10 are set to two clock cycles will be described. In this case, the period T1 of one clock cycle is 1 / (32 * 10 ⁶ ), that is, 0.03125 seconds (sec), and the period T2 of two clock cycles is 0.0625 seconds, that is, 62.5 ns. That is, the delay circuit and the edge detector 10 delay the infrared signal IR by 62.5ns and provide it to the state machine 30. Thus, the state machine 30 receives the 62.5 ns delayed signal rxdata_syn from the delay circuit 10 and generates a signal having a pulse width of 125 ns (the FIR mode standard pulse width defined by the IrDA standard). Accordingly, the time point at which the state machine 30 determines the received infrared signal IR as a single pulse or a double pulse is about 187.5 ns (= 62.5 ns + 125 ns) from the start of the activation level of the received infrared signal IR. It is a delayed time.

In other words, the state machine 30 determines a single pulse when the activation level of the received infrared signal IR is 187 ns or less, and a double pulse when 187 ns or more. That is, by adjusting the delay time of the delay circuit 10, the reference for discriminating the received infrared signal into a single pulse and a double pulse can be changed.

Therefore, the infrared signal receiver 1 of the present invention not only accurately determines whether the received infrared signal rxdata is a single pulse or a double pulse, but also the pulse width of the received infrared signal rxdata is widely distributed. Accurate signal detection is possible by synchronizing the received signal with the DPLL clock signal dpll_clk of the DPLL circuit 40.

The following is a "Verilog" code for programming the operation of the infrared signal receiver 1 shown in FIG. The signal names of the following programs coincide with the names of the signals shown in Figs.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, not only accurately determine whether the received infrared signal is a single pulse or a double pulse, but also receives the received signal even if the pulse width of the received infrared signal is widely distributed. By precisely synchronizing with, the signal can be detected accurately.

Claims (3)

In a receiver that receives an infrared signal: Delay means for receiving the infrared signal and delaying it for a preset time; Detection means for detecting a rising edge of the infrared signal delayed by the delay means; A state machine for generating a pulse signal having a predetermined pulse width in response to the infrared signal delayed by the delay means and the rising edge detection signal detected by the detection means; And A digital phase locked loop receiving the pulse signal to generate a pulse signal synchronized with an internal clock signal; The state machine, When the pulse signal synchronized with the internal clock signal transitions from the first level to the second level, the infrared signal is determined as a single pulse or a double pulse according to the level of the infrared signal delayed by the delay means, and a corresponding state signal is obtained. And output a pulse signal synchronized with the internal clock signal as an infrared detection signal in response to the status signal. The method of claim 1, And a counter for counting in response to the count enable signal. The method of claim 2, The state machine, Activate the count enable signal in response to the rising edge detection signal; Outputting a status signal indicating that the infrared signal is a single pulse when the infrared signal delayed by the delay means is a first level when the count value input from the counter is a predetermined value, and deactivating the count enable signal, Outputting a status signal indicating that the infrared signal is a double pulse when the infrared signal delayed by the delay means is a second level when the count value input from the counter is the predetermined value, and maintains the active state of the count enable signal; Infrared signal receiver, characterized in that.