KR20010019208A - Decoding circuit for selecting gradation voltage of source driver of tft-lcd - Google Patents

Abstract

PURPOSE: A decoding circuit for selecting tone voltage of a source driver of a thin film transistor liquid crystal display device is provided to offer a tone voltage decoder circuit a length direction size thereof is decreased by improving a layout of a tone voltage decoder circuit. CONSTITUTION: Sixty four kinds of tone voltage are connected to sixty four tone voltage terminals. The odd number tone voltage terminals(V1, V3, ...V63) are opposed to the even number tone voltage terminals(V2, V4, ..., V64) in both directions of a common output line(400). The odd number tone voltage terminals(V1, V3, ...V63) are connected to the first decoding unit(100), and the even number tone voltage terminals(V2, V4, ..., V64) are connected to the second decoding unit(300). The first decoding unit(100) consists of eight 4x1 decoders(1001, 1002, ..., 1008). The second decoding unit(300) consists of eight 4x1 decoders(3001, 3002, ..., 3008). One 4x1 decoder consists of 4x3 numbers transistor. The output terminals of the first decoding unit(100) and the second decoding unit(300) are connected to the third decoding unit in parallel. The third decoding unit consists of 16x3 numbers transistor. In the third decoding unit, the number of output terminals numbers of the first decoding unit(100) is eight, and the first 8x3 decoder block(200A) is composed by using 8x3 numbers transistors for selecting one tone voltage from the eight output terminals. The second 8x3 decoder block(200B) is composed by using the other 8x3 numbers transistors for selecting one tone voltage from eight output of the second decoding unit(300). The first 8x3 decoder block(200A) and the second 8x3 decoder block(200B) are opposed thereto in the both directions of the common output line(400).

Description

Decoding circuit for selecting gradation voltage of source driver of thin film transistor liquid crystal display device {DECODING CIRCUIT FOR SELECTING GRADATION VOLTAGE OF SOURCE DRIVER OF TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of an image display device, and more particularly to a source driving circuit of a thin film transistor (hereinafter referred to as TFT) liquid crystal display (LCD). .

The research trends related to the source driving circuit of the TFT LCD have been mainly focused on low power consumption, high quality and low cost. Recently, the demand for low power consumption and high image quality can be evaluated to a certain degree due to the active research results. Now, the center of gravity of research and development is shifting to technology that can provide high quality image while lowering power consumption and implementing TFT LCD at low cost. In particular, in implementing a source driving circuit of a TFT LCD, efforts have been actively made to implement a low cost product by simplifying a manufacturing process or reducing a chip size.

The source driving circuit of the TFT LCD is a circuit that converts digital image data into analog image data, that is, a gradation voltage that determines the luminance of each pixel of the LCD. For example, in the case of a TFT LCD having 64 gradation voltages, one specific gradation voltage is selected using 6 bit data. That is, the source driving circuit receives a 6-bit data and is responsible for a decoding function of selecting and outputting one of the 64 voltage levels.

There have been various methods of decoding grayscale voltage using digital input data, and typical methods thereof are shown in FIGS. 1 and 2. Fig. 1 shows a layout of 64 gray voltage selection decoders in accordance with the 64x1 method conventionally applied to a TFT LCD. In the decoder of Fig. 1, 64 voltage terminals V1, V2, V3, ..., V64 are arranged in a line in the length (vertical) direction, and each of these voltage terminals is connected through six transistors connected in series. It is connected to the output terminal 10. In addition, the input terminal is provided with 6 bits of input data. Since 1 bit of input data has a value of 0 or 1, 12 data input lines are connected to the input terminal. Gates of six transistors connected to each voltage terminal are connected to the input lines in the following manner. That is, when the 6-bit input data has a value of '000000', that is, when the on signal is applied to the input terminals of IB0, IB1, IB2, IB3, IB4 and IB5, the six transistors connected to the V1 terminal are turned on. Therefore, the gray voltage output through the output terminal 10 becomes V1. In order for the gray voltage of the V64 terminal to be selected and output, the 6-bit input data must be '111111', which is a case where an ON signal is applied to the input terminals of I0, I1, I2, I3, I4, and I5.

Another method of the layout configuration of the 64 gradation voltage selection decoders is shown in FIG. 2 is a configuration in which eight 8x1 sub-decoding circuits are combined in the longitudinal direction. That is, the lower three bits of the six bits of input data are used to select eight gray voltages in each sub decoding circuit, and the upper three bits are used to select one sub decoding circuit among the eight sub decoding circuits. . This method can be seen as an improved layout in that the number of transistors required to select the gradation voltage can be reduced compared to the method of FIG.

However, both of the above methods are based on the arrangement of 64 gray voltage terminals in the longitudinal direction. Therefore, such a layout method has a disadvantage in that the chip size of the decoding circuit, especially the length in the longitudinal direction, must be increased.

The driving circuit for the TFT LCD is composed of various functional blocks and generally implements these functional blocks as integrated circuit chips. Among the functional blocks of the driving circuit, a decoder circuit which decodes the gray scale voltage occupies a large area. This decoder circuit is implemented in various forms depending on the number of bits or the scheme of the input digital image data. Among them, a register-to-digital analog converter (R-DAC) method is typical. According to this method, for example, when the digital input data is 6 bits, the occupied area of the upper decoder circuit of the entire area of the chip for the driving circuit is used. Is about 15% and occupies about 40% or more when the input data is 8 bits. Since the proportion of the area occupied by the decoder circuit is so high, the technique of reducing its size has an important influence on the miniaturization of the driver circuit.

Accordingly, an object of the present invention is to provide a gradation voltage decoder circuit having a reduced size in the length (vertical) direction by improving the layout of the gradation voltage decoder circuit.

1 is a layout diagram of 64 gray voltage selection decoders according to a conventional 64 × 1 scheme.

2 is a layout diagram of 64 gray voltage selection decoders according to eight 8x1 schemes according to the related art.

3 is a block diagram of 64 gray voltage selection decoders according to an embodiment of the present invention.

FIG. 4 is a block diagram of FIG. 3, which is a layout diagram of 64 gray voltage selection decoders.

<Description of the code | symbol about the principal part of drawing>

100: 4x1 decoder 200: 16x1 decoder

300: 4x1 decoder

In order to achieve the above object, there is provided a gradation voltage decoding circuit of an image display device for selecting and outputting one of 2 ^N gradation voltages using N bit image data. Gray-scale voltage decoding circuit 2 ^N of gray levels and the first gray level voltage terminal connecting group and the 2 ^N of gray-scale voltage even a single gray-scale voltage among the respective odd-numbered one gray level voltage associated with each of the voltage, based on the common output line of the first And a second gray voltage terminal group disposed to face the gray voltage terminal group. Further, the gray voltage decoding circuit is connected to a first gray voltage terminal group and connected to a first decoding unit and a second gray voltage terminal group for selectively controlling an output of an odd gray voltage using lower N / 2-bit image data. And a second decoding unit configured to selectively control an output of an even gray level voltage using the lower N / 2-bit image data. The gray voltage decoding circuit is further connected to output terminals of the first and second decoding units to select output voltages of the first and second decoding units using upper N / 2-bit image data and output them to the common output line. And a third decoding unit.

In particular, each of the two input lines for the least significant bit of the N-bit image data is connected to the first and second decoding units and used to determine whether the gray level voltage to be selected is an even number or an odd number.

As an example of the gradation voltage decoding circuit, when the image data is 6 bits, the first decoding unit and the second decoding unit are configured to include eight 4x1 decoders. In addition, the third decoding unit is composed of a 16x1 decoder.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a block diagram of a gradation voltage selection decoding circuit for selecting and outputting one gradation voltage using 6-bit image data when 64 gradation voltages are used. FIG. 4 is a layout of the decoding circuit of FIG. This is a detailed circuit diagram.

In general, to reduce the chip size, a process design rule or a method of increasing the number of metal layers can be used. On the other hand, the chip size can be adjusted by optimizing the arrangement of circuit elements or terminals. Can be reduced. The present invention is a configuration that can reduce the size in the longitudinal direction on the premise that the same design rules and the same number of metal layers.

Referring to Fig. 4, it is a decoding circuit when the image data is 6 bits. The number of gray voltages that can be selected using 6-bit video data is 2 ⁶ , that is, 64. The 64 gray voltages are coupled to 64 gray voltage terminals V1, V2, V3, ..., V64. Of the 64 gray voltage terminals, odd-numbered gray voltage terminals V1, V3, ..., V63 and even-numbered gray voltage terminals V2, V4, ..., V64 are common output lines 400. ) Are placed facing each other.

Odd-numbered gradation voltage terminals V1, V3, ..., V63 are connected to the first decoding unit 100, and even-numbered gradation voltage terminals V2, V4, ..., V64 are second-decoded. It is connected to the unit 300. The first decoding unit 100 is composed of eight 4x1 decoders 100 ₁ , 100 ₂ ,..., 100 ₈ . Similarly, the second decoding unit 300 also includes eight 4x1 decoders 300 ₁ , 300 ₂ , ..., 300 ₈ . One 4x1 decoder consists of 4x3 transistors.

Each output terminal of the first decoding unit 100 and the second decoding unit 300 is connected in parallel to the third decoding unit 200. The third decoding unit 200 is composed of 16x3 transistors. Specifically, the third decoding unit 200 has 8 output stages of the first decoding unit 100, and uses the 8x3 transistors to select one gray voltage from the eight 8x3 first decoder blocks (8). 200A). Similarly, another 8x3 transistor is used to configure an 8x3 second decoder block 200B for selecting one gray voltage among the eight outputs of the second decoding unit 300. These two decoder blocks 200A and 200B are disposed to face both sides of the common output line 400.

One bit of input data has a value of 1 or 0. Let 6-bit input data with a value of 1 be I0, I1, I2, I3, I4, I5 and 6-bit input data with a value of 0 be IB0, IB1, IB2, IB3, IB4, IB5. Input lines I1, I2, IB0, IB1, and IB2 related to the lower 3 bits of input data are connected to eight 4x1 decoders 100 ₁ , 100 ₂ , ..., 100 ₈ of the first decoding unit 100, respectively. Each of the decoders selects and outputs one of four types of gray voltages. Input lines I0, I1, I2, IB1, and IB2 related to input data of lower 3 bits are connected to eight 4x1 decoders 300 ₁ , 300 ₂ , ..., 300 ₈ of the second decoding unit 300, respectively. Each of the decoders selects and outputs one of four types of gray voltages. In particular, an input line of least significant input data I0 having a value of 1 is connected to a gate of each transistor connected to an even gray level voltage terminal, and an input line of least significant input data DB0 having a value of 0 is an odd number of gray levels. It is connected to the gate of each transistor connected to the voltage terminal.

The input data I3, I4, I5, IB3, IB4, and IB5 of the upper three bits function to allow the first decoder block 200A to select any one of eight decoders of the first decoder 100. The upper three bits of input data I3, I4, I5, IB3, IB4, and IB5 also function to allow the second decoder block 200B to select any one of the eight decoders of the second decoder 300.

Here, the transistors employed in the first and second decoding units 100 and 300 and the third decoding unit 200 may be any type as long as they can perform a switching operation, for example, an N-type or P-type MOS transistor. Is an example.

When the decoder circuit is physically implemented using an NMOS transistor, the input data I0 to I5 are connected to the polygates forming the NMOS transistor through metal lines, and the gray voltages V1 to V64 are formed through the metal lines to form the NMOS transistor. Connect to the active source. Here, the odd-numbered voltages V1, V3, ..., V63 are connected to the source of the first side (left) active, and the even-numbered voltages V2, V4, ..., V64 are connected to the second side (right). ) Connect to the active source. The common output terminal for outputting the selected voltage is connected to the drain of the active forming the NMOS transistor through the metal line.

In the decoding circuit configured as described above, the operation of selecting and outputting the gray scale voltage according to the state of the input data will be described below.

First, the least significant bit I0 input data having a value of 1 selects even-numbered gradation voltages (V2, V4, ..., V64) of 64 V1 to V64 gradation voltages, and has the least significant bit IB0 input data having a value of 0. Is responsible for selecting odd-numbered gradation voltages (V1, V3, ..., V63) among the 64 gradation voltages.

The lower two-bit input data I1, I2, IB1, and IB2 provided to the first decoding unit 100 select eight voltages among 32 odd gray voltages, and the lower input data provided to the second decoding unit 300. I1, I2, IB1, and IB2 select eight voltages out of the 32 even-numbered gradation voltages. The remaining upper 3 bits of input data I3, I4, I5, IB3, IB4, and IB5 select one of the total 16 gray voltages output from the first decoding unit 100 and the second decoding unit 300, respectively. Allows you to select one of the 64 gradation voltages.

For example, if the 6-bit input image data 'I5, I4, I3, I2, I1, I0' is '000000', that is, on the input line of 'IB5, IB4, IB3, IB2, IB1, IB0'. When the on signal is provided, the bottom three transistors of the eighth 4x1 decoder 100 ₈ of the first decoding unit 100 are turned on and the bottom transistors of the first decoding block 200A of the third decoding unit 200 are turned on. 3 are turned on. As a result, the gradation voltage selected and output through the common output line 400 becomes V1. Similarly, if the value of the 6-bit input data 'I5, I4, I3, I2, I1, I0' is '000001', V2 is selected, and if '000010', V3 is selected. If V64 is selected as the same reason, the value of input data 'I5, I4, I3, I2, I1, I0' is '000001', and in this case, the six top right of the common output line 400 Transistor is on. The selected gray voltage is output through the common output line 400.

As can be seen from the above description, the present invention has an effect of remarkably reducing the size of the decoder circuit in the vertical (length) direction when implementing the R-DAC decoding circuit as a chip. When the design rules of the same process are applied, the vertical size of the decoder circuit is basically reduced in half compared to the conventional method of arranging the gray voltage terminals in a vertical direction. For example, when applied to a 6-bit TFT LCD source driver, the chip length is reduced by about 5%, and in the case of an 8-bit TFT LCD source driver, the chip length is reduced by about 20%.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (4)

A gradation voltage decoding circuit of an image display device for selecting and outputting one of 2 ^N gradation voltages using N bit image data, A first gradation voltage terminal group each connected to an odd gradation voltage among the 2 ^N gradation voltages; A second gray voltage terminal group connected to an even number of gray voltages among the ^2N gray voltages and disposed to face the first gray voltage terminal group based on a common output line; A first decoder connected to the first gray voltage terminal group to selectively control an output of the odd gray voltage using lower N / 2-bit image data; A second decoder connected to the second gray voltage terminal group to selectively control the output of the even gray voltage using the lower N / 2-bit image data; And And a third decoder connected to the output terminals of the first and second decoders to select output voltages of the first and second decoders using upper N / 2-bit image data and output the output voltages to the common output line. Gray voltage decoding circuit. The gradation voltage decoding circuit of claim 1, wherein the gradation voltage to be selected is determined by using even-numbered or odd-numbered images using the least significant bit of image data. The gray voltage decoding circuit of claim 1, wherein the first and second decoding units comprise eight 4 × 1 decoders, respectively, when the image data is 6 bits. The gray voltage decoding circuit of claim 1, wherein the third decoding unit is a 16 × 1 decoder when the image data is 6 bits.