KR20010011501A - Memory cell disturbance prohit circuit - Google Patents

Abstract

PURPOSE: A circuit within a semiconductor memory device is provided to prevent a program interference for memory cell arrays so that speed and accuracy for a program are improved. CONSTITUTION: The device includes a word-line interference preventer(50) and a bit-line interference preventer(60). The word-line interference preventer(50) includes a first decoder(51) and switches(SW10-SW12). The bit-line interference preventer(60) includes a second decoder(61) and switches(SW20-SW22). According to a control signal from a cell array controller(20), the first decoder(51) decodes X-addresses and outputs decoded signals corresponding to word lines(WL1-WL3). According to the decoded signals from the first decoder(51), word lines which are not selected go to be a ground potential by the switches(SW10-SW12). According to a control signal from the cell array controller(20), the second decoder(61) decodes Y-addresses and outputs decoded signals corresponding to bit lines(BL1-BL3). According to the decoded signals from the second decoder(61), bit lines which are not selected go to be a ground potential by the switches(SW20-SW22).

Description

Programmable interference prevention circuit of memory cell array {MEMORY CELL DISTURBANCE PROHIT CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly, to a program interference prevention circuit of a memory cell array.

Electrically erasable programmable read on memory (EEPROM) is a programmable ROM that can electrically program and erase data using cell transistors having floating gates. The upper gate of the cell transistor is connected to a word line so that an external signal can be applied, and the lower gate is formed of a floating gate surrounded by SiO 2. Therefore, during the program operation, electrons are injected into the lower floating gate of the cell transistor to increase the threshold voltage of the cell transistor, and during the erase operation, electrons are extracted from the floating gate to lower the threshold voltage of the cell transistor.

Since the threshold voltage of the cell transistor (memory cell) changes according to the amount of charge of the floating gate, that is, the programmed data, the data is determined accordingly. For example, assuming that the injection of electrons is an operation of writing data "0", and the extinction of electrons is an operation of writing data "1", the threshold voltages of the cell transistors for data "0" and "1" are respectively. 9.5V and 2V. Therefore, if 5V is applied to the word line during the read operation, the cell transistor programmed with "0" is turned off and the cell programmed with "1" is turned on, so that the cell data is determined based on the current difference flowing through the cell transistor. Done.

1 is a schematic structure of a general flash memory and includes a memory cell array 10, a cell array controller 20, a word line decoder 30, and a bit line decoder 40.

The memory cell array 10 includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells EEPROM positioned at intersections of the plurality of word lines and the plurality of bit lines. In the case of the NOR type, a gate of each memory cell is connected to a word line, a drain is connected to a bit line, and a source is connected to a source control circuit (not shown) through a plurality of source lines. 1, three word lines WL1 to WL3, three bit lines BL1 to BL3, three source lines SL1 to SL3, and word lines WL1 to WL3 and bit lines are shown in FIG. 1 for convenience of description. Only nine memory cells A to I located at the intersections of the BL1 to BL3 are shown.

The cell array control unit 20 controls the word line decoder 30 and the bit line decoder 40 according to an external control signal. The word line decoder 30 decodes an X-address to generate one of a plurality of word lines. And bit line decoder 40 decodes the Y-address to select one of the plurality of bit lines. In addition, the plurality of bit lines BL1 to BL3 are connected not only to the bit line decoder 40 but also to an erase circuit, a write circuit, a sense amplifier, and the like, which are controlled by the cell array controller 20, and detailed circuit configurations thereof will be omitted. do. The write circuit provides a program voltage to a selected memory cell through a bit line during programming, and the sense amplifier senses data on the bit line and outputs the data to the outside during a read operation.

The operation of the conventional flash memory configured as described above is as follows.

When a control signal indicating a program operation is input from the outside, the cell array controller 20 enables the word line decoder 30 and the bit line decoder 40. The word line decoder 30 decodes an X-address signal input from an X-address buffer (not shown) to select one of a plurality of word lines, and the bit line decoder 40 selects a Y-address buffer (not shown). One of a plurality of bit lines is selected by decoding the Y-address inputted from S). Thus, the program voltage is provided from the write circuit to the selected memory cell through the selected bit line to program the data.

For example, consider a case where the memory cell E selected by the word line WL2 and the bit line BL2 is being programmed. When programming the memory cell E, a word line voltage having a Vpp (12 V or higher) level output from the word line decoder 30 is applied to the word line WL2, and an external source line is applied to the source lines SL1 to Sl3. A voltage of 0 V output from the controller (not shown) is applied.

However, since the selected word line WL2 is connected not only to the memory cell E but also to a plurality of memory cells, for example, the memory cells B and H, the bit lines BL1 and BL3 are connected. Is not selected, but the memory cells D and F are also subjected to voltage stress caused by Vpp. This phenomenon is more likely to occur as the number of memory cells connected to the selected word line and bit line increases, and the stress time becomes longer. As a result, not only the selected memory cell E but also the unselected memory cells D and F are subjected to program interference by the word line WL2. Therefore, data of a memory cell that is already programmed due to program interference is lost or data is programmed in an unprogrammed memory cell, which causes cell failure.

In addition, when the semiconductor memory device alternates between the program operation and the read operation at high speed, the word lines not selected in the read operation must be sufficiently discharged. However, if another word line WL2 is selected while the charge is not sufficiently discharged in the unselected word line WL1 or WL3, the unwanted memory cell D or F during the read operation of the memory cell E is selected. Is also read, causing bad cell data. This phenomenon not only reduces the program efficiency of the memory cell, but also shortens the life of the cell, and may even cause the entire system to become unstable and cause system malfunction.

Accordingly, an object of the present invention is to provide a program interference prevention circuit which can prevent program of an unwanted memory cell and improve program efficiency.

It is still another object of the present invention to provide a program interference prevention circuit capable of stably outputting cell data by sufficiently discharging an unselected word line during a read operation.

In order to achieve the above object, the present invention provides a memory cell array having a plurality of word lines and a plurality of bit lines, and a memory cell located at an intersection of each word line and a bit line. A word line decoder for selecting one, a bit line decoder for selecting one of the plurality of bit lines, a word line interference prevention circuit for decoding an X-address and grounding unselected word lines in a read operation; A bit line interference prevention circuit for decoding an address and grounding unselected bit lines during a program operation.

1 is a schematic structure of a general flash memory.

2 is a program interference prevention circuit of a memory cell array according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: memory cell array 20: cell array controller

30: word line decoder 40: bit line decoder

50: word line interference prevention circuit 51: first decoder

60: bit line interference prevention circuit 61: second decoder

SW10 to SW12, SW20 to SW22: switch

2 is a program interference prevention circuit of a memory cell array according to the present invention, and further includes a word line interference prevention circuit 50 and a bit line interference prevention circuit 60 in addition to the flash memory structure shown in FIG. . In FIG. 2, three word lines WL1 to WL3, three bit lines BL1 to BL3, three source lines SL1 to SL3, and the word lines WL1 to WL3 and bits are illustrated in FIG. 2 for convenience of description. Only nine memory cells A to I are shown, respectively located at the intersections of the lines BL1 to BL3.

The word line interference prevention circuit 50 is connected to the word lines WL1 to WL3 of the memory cell array 10 and grounds a word line that is not selected during a read operation. The bit line interference prevention circuit 60 is connected to the plurality of bit lines BL1 to BL3 of the memory cell array 10 and grounds the bit lines which are not selected during the program operation.

The word line interference preventing circuit 50 may decode the X-address under the control of the cell array control unit 20 to output a decoding signal corresponding to the word lines WL1 to WL3, and A plurality of switches SW10 to SW12 for grounding unselected word lines in accordance with the decoding signal output from the first decoder 51 are provided.

The bit line interference prevention circuit 60 decodes the Y-address according to the cell array controller 20 to output a decoded signal corresponding to the bit lines BL1 to BL3, and the second decoder 61. It consists of a plurality of switches SW20 to SW22 for grounding unselected bit lines according to the decoding signal output from the decoder 61. In this case, the plurality of switches provided in the word line interference prevention circuit 50 and the bit line interference prevention circuit 60 may be configured as MOS transistors or separate logic.

The operation of the program interference prevention circuit of the memory cell array according to the present invention configured as described above will be described with reference to the accompanying drawings.

When the memory cell E selected by the word line WL2 and the bit line BL2 is being programmed, the word line WL2 has a Vpp (12V or higher) level output from the wordline decoder 30 as described above. The word line voltage is applied. In addition, a voltage of 0 V is applied to the source lines SL1 to Sl3.

At this time, the second decoder 61 of the bit line interference prevention circuit 60 decodes the Y-address and outputs decoding signals corresponding to the bit lines BL1 to BL3, respectively. As a result, the switches SW20 and SW22 are turned on and the switches SW21 are turned off by the decoding signal output from the second decoder 61 so that the potentials of the bit lines BL1 and BL3 are turned off. It is connected to ground Vss. Therefore, even though the memory cells B and H on the word line WL2 are subjected to voltage stress due to the Vpp voltage, the potentials of the bit lines BL1 and BL3 maintain the ground Vss level. Channels are not formed in the cells B and H. Therefore, according to the present invention, all the bit lines BL1 and BL3 except the selected bit line BL2 are connected to ground, thereby preventing program interference due to voltage stress during programming.

On the other hand, the word line voltage of the Vdd level (5 V) output from the word line decoder 30 is applied to the word line WL2, and the voltage of 0 V is applied to the source lines SL1 to Sl3. At this time, the first decoder 51 of the word line interference prevention circuit 50 decodes the X-address and outputs a decoding signal corresponding to each of the bit lines WL1 to WL3. As a result, the switches SW10 and SW12 are turned on and the switches SW11 are turned off by the decoding signal output from the first decoder 51 so that the word lines WL1 and WL3 are grounded. Vss). As a result, the charges of the word lines WL1 and WL3 are sufficiently discharged while the data of the memory cell E is read. Therefore, according to the present invention, all the word lines WL1 and WL3 except the selected word line WL2 are connected to the ground, thereby stably outputting data of the selected memory cell E during the read operation.

The present invention is not limited to the first and second decoders 50 and 60, and the first and second drivers directly receiving the outputs of the word line decoder 30 and the bit line decoder 40 may be used. It can be provided to control a plurality of switches.

The preceding embodiments in this invention are by way of example only and not intended to limit the scope of the claims, and various alternatives, modifications and variations will be apparent to those skilled in the art.

As described above, the present invention minimizes voltage stress applied to the memory cell by connecting all bit lines except the selected bit line to the ground to the ground. As a result, the program speed can be improved by extending the life of the memory cell and preventing program interference. In addition, the present invention has the effect of preventing the malfunction of the system by stably outputting the cell data by connecting all word lines except the selected word line to ground when reading the cell data.

Claims (8)

A memory cell array having a plurality of word lines and a plurality of bit lines, the memory cells being located at intersections of the word lines and the bit lines; A word line decoder for selecting one of the plurality of word lines; A bit line decoder for selecting one of the plurality of bit lines; A word line interference prevention circuit for decoding the X-address to ground word lines that are not selected during a read operation; And a bit line interference prevention circuit for decoding a Y-address to ground bit lines that are not selected during a program operation. 2. The program interference prevention circuit of claim 1, wherein the memory cell is EEPROM. The word line interference preventing circuit of claim 1, further comprising: a first decoder configured to output a decoding signal corresponding to a plurality of word lines; And a plurality of switches for grounding word lines that are not selected according to the decoding signal of the first decoder. 4. The program interference prevention circuit of claim 3, wherein the plurality of switches comprise a MOS transistor. 2. The apparatus of claim 1, wherein the bit line interference prevention circuit comprises: a second decoder for outputting a decoding signal corresponding to a plurality of bit lines; And a plurality of switches for grounding bit lines that are not selected according to the decoding signal of the second decoder. 6. The program interference prevention circuit of claim 5, wherein the plurality of switches comprise a MOS transistor. The word line interference preventing circuit of claim 1, further comprising: a first driver configured to receive an output of the word line decoder and to output a plurality of switching signals; And a plurality of switches for grounding word lines that are not selected according to the switching signal of the first driver. The semiconductor device of claim 1, wherein the bit line interference prevention circuit comprises: a second driver configured to receive an output of the bit line decoder and output a plurality of switching signals; And a plurality of switches for grounding bit lines that are not selected according to the switching signal of the second driver.