KR20010009727A - Two-stage ring voltage controlled oscillator utilizing one pair of variable delay elements - Google Patents

Abstract

PURPOSE: A two-stage ring voltage controlling oscillator by using a couple of variable delay elements is provided to carry out the function as a voltage controlling oscillator even if accuracy, security and reappearance in the manufacturing progress aren't outstanding. CONSTITUTION: A two-stage ring voltage controlling oscillator by using a couple of variable delay elements includes the first analog mixer(321), the fist variable delay element portion(33), the first, M-delay or reversing element(323), the second, M-delay or reversing element(322), the second analog mixer(331), the second variable delay element portion(33), the second M-delay or reversing element(333) and the second, first delay or reversing element(332). In the first analog mixer(321) of the fist variable delay element portion(33) inputs the output of the first, M-delay or reversing element(323) and output of the second, M-delay or reversing element(322) and mixes them with analog and outputs them with the input of the first, first delay or reversing element(322). The first, first delay or reversing element(322) and the first, M-delay or reversing element(323) generate the delayed or reversed signal with adding the amplitude of the input signal. The second analog mixer(331) of the second variable delay element portion(33) inputs the output of the second M-delay or reversing element(333) and output of the second, M-delay or reversing element(332) and mixes them with analog and outputs them with the input of the second, first delay or reversing element(332). The second, first delay or reversing element(322) and the second, M-delay or reversing element(333) generate the delayed or reversed signal with adding the amplitude of the input signal.

Description

Two-stage ring voltage controlled oscillator utilizing one pair of variable delay elements

The present invention relates to a ring voltage controlled oscillator, and more particularly, to a two-stage ring voltage controlled oscillator using two pairs of variable delay elements.

The voltage controlled oscillator using the pull-down current method, which is one of the conventional ring oscillators, directly changes the rise and fall times of inverters constituting the oscillation loop by using a voltage controlled bias current source. This is D.L. It is described in detail in US Pat. No. 4,565,976 to D.L. Cambell. This type of voltage controlled oscillator has a limitation in increasing the oscillation frequency due to the capacitance component of the voltage controlled bias current source. In particular, when the oscillation period is shortened, the inverter may not be operated unstable and the inverter delay must be controlled for each inverter. There is a disadvantage.

As an example of another voltage controlled oscillator, US Patent No. 5,675,293 describes a high frequency voltage controlled oscillator using a general integrated circuit. This reduces the gain of the voltage-controlled oscillator in the process of high frequency accuracy and high reproducibility, and operates stably in external noise. However, in a process having general accuracy, stability and reproducibility, if the gain of the voltage controlled oscillator is small, the oscillation or the control function of the oscillation may be lost.

As another method, U.S. Patent No. 4,884,041 proposes a voltage controlled oscillator which uses an analog mixer to control the oscillation frequency with a delay difference between two loops (shortest delay loop and longest delay loop). This structure has the advantage that the oscillation frequency can be higher than the voltage controlled oscillator using the conventional pull-down current method, but the phase difference between the two input signals should be 180 degrees or less due to the operation characteristics of the analog mixer. In addition, considering the stability and linearity of the oscillator, the phase difference drops to near 180 degrees, which degrades the performance of the overall voltage controlled oscillator.

In general, in order to provide an oscillable voltage controlled oscillator, the delay time of the longest delay loop should be less than twice the delay time of the shortest delay loop. Therefore, there is a way to improve the voltage-controlled oscillation gain by arbitrarily adjusting the number of delay elements used in the two loops, but there is a method of using a voltage-controlled oscillator with a series-connected multistage structure. Has the disadvantage of being lowered.

1 is a block diagram of a conventional voltage controlled oscillator using an analog mixer, in which reference numeral 11 is an inverting combination circuit, and reference numerals 12, 13, and 14 are three delay elements that generate delays, respectively.

The second delay element 13 provides the first input signal Vy of the inversion combination circuit 11, and the third delay element 14 provides the second input signal Vx of the inversion combination circuit 11. do. The output signal Vz of the inversion combination circuit 11 is represented by-[VcVx + (1-Vc) Vy], which is a linear combination of two input signals Vy and Vx. In the above equation, '-' means that the signal waveform is inverted, and Vc is a control signal applied to the inversion combination circuit 11 and is equal to or greater than 0 and equal to or less than 1.

When constructing the voltage controlled oscillator in this manner, the stable maximum oscillation frequency is obtained when the total delay time d1 + d2 by the first delay element 12 and the second delay element 13 is equal to the delay times of the three inverters. The minimum oscillation frequency is obtained when the total delay time d1 + d3 by the first delay element 12 and the third delay element 14 is equal to the delay times of the five inverters.

Because the number of inverters operating in the longest delay loop, which is the loop generating low frequency, is less than twice the number of inverters operating in the shortest delay loop, which is the loop generating high frequency, it is possible to oscillate by the difference of delay time between two paths. There is a constraint.

As described above, in the shortest delay loop composed of three inverters and the longest delay loop composed of five inverters, the delay of one inverter is 3D, and the maximum total delay time is 5D. In addition, the oscillation frequency range is 1 / 6D to 1 / 10D and the oscillation gain is low.

FIG. 2 is a configuration diagram illustrating an example of an oscillator having a voltage controlled oscillation gain improved by configuring the voltage controlled oscillator shown in FIG. 1 in multiple stages. Reference numerals 21 and 22 are analog mixers, and 23 to 29 are inverters.

When the control voltage Vc is 0, the total delay time is 3D, when Vc is 0.5, the total delay time is 4.5D, and when Vc is 1, the total delay time is 7D. Therefore, the oscillation frequency range is increased from 1 / 6D to 1 / 14D, so that the voltage controlled oscillation gain can be improved. However, the delay time 5D of the longest delay loop which is the input Vx of the first analog mixer 21 is 4D which is twice the delay time 2D of the shortest delay loop which is the other input Vy of the first analog mixer 21. Since it is late, in a voltage controlled oscillator using an analog mixer, even if oscillation is stopped or oscillated, linearity and stability are deteriorated, thereby degrading the performance of the voltage controlled oscillator.

Accordingly, the present invention has been made to solve the problems of the prior art as described above, while maintaining the highest frequency of the voltage-controlled oscillator compared to the voltage-controlled oscillator using a conventional analog mixer to implement the integrated circuit to maintain the highest frequency An object of the present invention is to provide a two-stage ring voltage controlled oscillator using two pairs of variable delay elements capable of performing a voltage controlled oscillation function without having excellent accuracy, stability, and reproducibility in the process.

1 is a block diagram of a ring voltage controlled oscillator using a conventional analog mixer,

2 is a block diagram of a multi-stage ring voltage controlled oscillator using a conventional analog mixer;

3 is a block diagram of an overall configuration of a ring voltage controlled oscillator according to an embodiment of the present invention;

4 is a configuration diagram of a ring voltage controlled oscillator according to an embodiment of the present invention;

5 is a configuration diagram of a ring voltage controlled oscillator according to another embodiment of the present invention.

※ Explanation of code about main part of drawing ※

11: reverse combination circuit 12: first delay element

13: second delay element 14: third delay element

21: first analog mixer 22: second analog mixer

23-29: inverter

31: control signal of the first and second analog mixer

32: first variable delay element 321: first analog mixer

322: first, first delay or inverting element 323: first, M delay or inverting element

33: second variable delay element 331: second analog mixer

332: second, first delay or inverting element 333: second, M delay or inverting element

41: control signal of the first and second analog mixer

42: first variable delay element 421: first analog mixer

422: first delay or inverting element 43: second variable delay element

431: second analog mixer 432: second delay or inverting element

51: control signal of the first and second analog mixer

52: first variable delay element 521: first analog mixer

522: first, first delay or inverting element 523: first, M delay or inverting element

53: second variable delay element 531: second analog mixer

532: second, first delay or inverting element 533: second, M delay or inverting element

In order to achieve the above object, the ring voltage controlled oscillator according to the present invention comprises a variable delay element part using an analog mixer and at least one delay or inversion element, and two variable delay element parts having the same configuration are connected in series. It is characterized by.

The present invention defines an analog mixer and a delay or inversion element as one variable delay element portion, and has a structure in which two variable delay element portions are connected in series. Each variable delay element unit has an analog mixer, and can vary the delay time of the two signals input to the analog mixer and limit the phase difference between the two input signals up to 90 degrees. As a result, stability and linearity are improved and the maximum oscillation frequency can be generated while having a high voltage controlled oscillation gain.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

The control voltage Vc is provided to the first analog mixer 321 and the second analog mixer 331 through the control signal 31. The first variable delay element unit 32 includes a first analog mixer 321 and a first, first delay or inversion element 322, ..., a first, M delay or inversion element 323.

The first analog mixer 321 of the first variable delay element unit 33 receives the output of the first, M delay or inversion element 323 and the output of the second, M delay or inversion element 333, respectively. The analog signal is mixed by the control signal 31 and output to the input of the first, first delay or inverting element 322. The first, first delay or inverting element 322, ..., the first, M delay or inverting element 323 generates a delayed or inverted signal while increasing the amplitude of the input signal.

The second variable delay element unit 33 includes a second analog mixer 331 and a second, first delay or inversion element 332,..., A second, M delay or inversion element 333.

The second analog mixer 331 of the second variable delay element unit 33 receives the output of the first, M delay or inversion element 323 and the output of the second, M delay or inversion element 333, respectively. The analog signal is mixed by the control signal 31 and output to the input of the second, first delay or inverting element 332. The second, first delay or inversion element 332, ..., the second, M delay or inversion element 333 increases the amplitude of the input signal and generates a delayed or inverted signal.

Referring to the operation and effects of the ring voltage controlled oscillator according to the present invention configured as described above are as follows.

The control signal 31 is a control voltage Vc input to the first and second analog mixers 321 and 331 and has a value between 0 and 1. FIG. If the control voltage Vc is 0, the frequency is output with the oscillation period proportional to the delay time input to the shortest delay loop. If the control voltage Vc is 1, the oscillation period is proportional to the delay time input to the longest delay loop. Output the frequency. In addition, when the control voltage Vc is 0.5, frequencies having an oscillation period proportional to a median value of two delay times input to the shortest delay loop and the longest delay loop are respectively output.

That is, when the control signal gradually changes from 0 to 1, the control signal changes from an frequency having an oscillation period proportional to the delay time input to the shortest delay loop to an oscillation frequency proportional to the delay time input to the longest delay loop.

In the first variable delay element unit 32, the output signal of the first, M delay or inverting element 323 is input to the first input terminal Vy of the first analog mixer 321, and the second, M The output signal of the delay or inversion element 333 is input to the second input terminal Vx. In addition, the final output signal (Vz) is received as a control voltage (Vc) generated from the control signal 31 from the outside is represented by-[VcVy + (1-Vc) Vx], '-' outside the parentheses in the above equation is a signal This means that the waveform is inverted.

The first, first delay or inverting element 322 is the amplitude of the signal input to the first, first delay or inverting element 322 when the output signal Vz of the first analog mixer 321 is the minimum amplitude of the oscillation condition. Amplify, delay or invert the attenuated output signal Vz to be at least equal to or greater than. The first, M delay or inversion element 323 amplifies and delays or inverts the output signal of the first, M-1 delay or inversion element.

The second analog mixer 331 of the second variable delay element unit 32 receives the output signal of the second, M delay or inverting element 333 through the first input terminal Vy, and receives the second, M delay or The output signal of the inverting element 323 is input to the second input terminal Vx. In addition, the control voltage Vc generated from the control signal 31 is input from the outside to output-[VcVy + (1-Vc) Vx]. In the above equation, '-' outside the parentheses means that the signal waveform is inverted.

The second, first delay or inverting element 332 is at least equal to or greater than the amplitude of the signal input to the second analog mixer 331 when the output signal of the second analog mixer 331 is the minimum amplitude of the oscillation condition. Amplify and delay or invert the output signal. The second, M delay or inversion element 333 amplifies, delays or inverts the output signal of the second, M-1 delay or inversion element.

4 is a view illustrating a state in which only one delay or inversion element is used as an embodiment of the present invention. Reference numeral 41 denotes a control signal of the first and second analog mixers, 42 and 43 are variable delay element units, 421 and 431 are analog mixers, and 422 and 432 are delay or inverting elements. Here, the analog mixers 421 and 431 and the delay or inverting elements 422 and 432 operate in a differential mode, respectively, so that an oscillation frequency may be increased because a separate inversion element is not required. Each device uses source coupled FET LOGIC (SCFL) that is resistant to temperature and supply voltage noise.

The delay times of the respective analog mixers 421 and 431 are the same as the propagation delay times of the delay or inverting elements 422 and 432, but are ignored on the assumption that only the mixer functions as a comparison with the conventional invention described above. If each delay or inversion element 422, 432 is 1D, the minimum delay time is 1D (loop: 422-> 421) and the maximum delay time is 2D (loop: 422-> 431-> 432-> 421). to be.

The control signal 41 simultaneously applies the control voltage Vc to the first analog mixer 421 and the second analog mixer 431. If 0 is applied to the control voltage Vc (fst = 0, slw = 1; differential mode), the first input terminal Vy of the first analog mixer 421 and the second analog mixer 431 is input. The signal is output to the output terminal Vz in preference to the signal input to the second input terminal Vx. This output signal corresponds to the shortest delay loop, and the delay time is the delay time 1D of the first delay or inversion element 422, and the output frequency is 1 / 2D. The two signals input to the first analog mixer 421 pass through the same number of delay or inverting elements to generate the same frequency so that the phase difference between the two signals becomes 0 degrees.

If 1 is applied to the control voltage Vc (fst = 1, slw = 0; differential mode), a signal input to the input terminal Vx of the first analog mixer 421 and the second analog mixer 431 is input. It is output to the output terminal Vz in preference to the signal input to the input terminal Vy.

This output signal corresponds to the longest delay loop, and the delay time is a total of 2D by adding a delay time 1D of the first delay or inversion element 422 and a delay time 1D of the second delay or inversion element 432. Is input to the input terminal Vx of the first analog mixer 421. Therefore, the total output delay time is 2D and the oscillation frequency is 1 / 4D. Since the phase of the signal input to the input terminal Vx of the first analog mixer 421 is 180 degrees, the phase delays of the first delay or inversion element 422 and the second delay or inversion element 432 are respectively 90. Since the phase delay of the signal input to the input terminal Vy is the same as the phase delay of the first delay or the inverting element 422, the phase delay is 90 degrees. Therefore, the phase difference between the two input signals input to the first analog mixer 421 varies from 0 degrees to a maximum of 90 degrees when the control voltage Vc changes from 0 to 1.

When the control voltage Vc is 0.5 (fst = 0.5, slw = 0.5; differential mode), the weight of 0.5 is multiplied by the input terminal Vx and the input terminal Vy of the second analog mixer 431, respectively. The delay time output to the terminal Vz is 1D relative to the delay time 1D provided by the first delay or inversion element 422 and the delay time 1D provided by the second delay or inversion element 432. [(1/2) x (1D + 1D)]. The output of the second delay or inverting element 432 delays the delay time 1D with respect to the output of the second analog mixer 431 and is delayed by 2D to the input terminal Vx of the first analog mixer 421. A signal is input, and a signal, which is a delay time 1D output from the first delay or inversion element 422, is input to the other input terminal Vy of the first analog mixer 421, respectively, 0.5 to the output terminal Vz. The total delay time by the weight of is 3D / 2 and the oscillation frequency is 1 / 3D.

5 illustrates another embodiment of the present invention using a plurality of delay or inversion elements.

Reference numeral 51 is a control signal input from the outside, and 521 and 531 are analog mixers. 522 is a first, first delay or inversion element, 523 is a first, M delay or inversion element, 532 is a second, first delay or inversion element, and 533 is a second, M delay or inversion element. Each device uses SCFL (Source Coupled FET LOGIC) which is strong against temperature and power voltage noise. Since each analog mixer and delay or inverting device operate in differential mode, it does not need a separate inverting device to increase the oscillation frequency. have.

In addition, the delay times of the analog mixers 521 and 531 are the same as the propagation delay times of the delay or inverting elements 522, 523, 532, and 533. When the delay time of each delay or inverting element is 1D, the minimum delay time is MD (loop: 522-> ...-> 523-> 521) and the maximum delay time is 2MD (loop: 522-> ...). -> 523-> 531-> 532-> ...-> 533-> 521).

The control signal 51 simultaneously applies the control voltage Vc to the first analog mixer 521 and the second analog mixer 531. If 0 is applied to the control voltage Vc (fst = 0, slw = 1; differential mode), a signal input to the input terminals Vy of the first analog mixer 521 and the second analog mixer 531. Is output to the output terminal Vz in preference to the signal input to the input terminal Vx. This output signal corresponds to the shortest delay loop and the delay time is for M, the number of delay and inversion elements from the first, first delay or inversion element 522 to the first, M delay or inversion element 523. The total delay time is MD, and the output frequency at this time is 1 / 2MD. The two signals input to the first analog mixer 521 pass through M delay or inverting elements to generate the same frequency so that the phase difference between the two signals becomes 0 degrees.

If 1 is applied to the control voltage Vc (fst = 0, slw = 1; differential mode), a signal input to the input terminals Vx of the first analog mixer 521 and the second analog mixer 531. Is output to the output terminal Vz in preference to the signal input to the input terminal Vy. This output signal corresponds to the longest delay loop, and the delay time is 2MD, which is the total delay time for the M delay or inversion elements 522 and 523 and the M delay or inversion elements 532 and 533, which is the first. It is input to the input terminal Vx of the analog mixer 521. Therefore, the total delay time is 2MD and the oscillation frequency is 1 / 4MD.

Since the phase of the signal input to the input terminal Vx of the first analog mixer 521 is 180 degrees, the phase delays of the first, first to second, M delays, or the inverting elements 522, 523, 532, and 533 are different. Are respectively 180 degrees / 2M, and the phase delay of the signal input to the input terminal Vy is the same as the first, first to first, M delay, or the phase delay via the inverting elements 522 and 523 (180). 2M) xM, which has a phase delay of 90 degrees. Accordingly, the phase difference between the two input signals input to the first analog mixer 521 varies from 0 degrees to a maximum of 90 degrees when the control voltage Vc changes from 0 to 1.

In addition, if 0.5 is applied to the control voltage Vc (fst = 0, slw = 1; differential mode), the weights of 0.5 are multiplied by the input terminals Vx and Vy of the second analog mixer 531, respectively, and output. The delay time of the terminal Vz is output with respect to the delay time MD provided by the first, M delay or inversion element 523 and the delay time MD provided by the second, M delay or inversion element 533. The delay time at terminal Vz becomes MD [(1/2) x (MD + MD)]. The output of the second, M delay or inverting element 533 is further delayed by MD by M delay and inverting elements to input a signal delayed by 2MD to the input terminal Vx of the first analog mixer 521. The other input terminal Vy of the first analog mixer 521 receives a signal which is a delay time MD output from the first, M delay or inversion element 523, and each of the output terminals Vz is 0.5. A signal with a total delay time of 3MD / 2 and an oscillation frequency of 1 / 3MD by weight is output.

Since the present invention has a frequency range from the highest 1 / 2MD to the lowest 1 / 4MD as can be seen in the above two embodiments, minimizing the number and delay time of the delay or inversion element will increase the oscillation frequency of the oscillator to the maximum. It is possible to adjust the center frequency to a constant frequency of the oscillation range regardless of the number of delay or inversion elements and the change of delay time.

Therefore, the present invention can maintain the maximum frequency at the same time while increasing the voltage-controlled oscillation gain can be implemented as a differential circuit can perform a voltage-controlled oscillation function even in a process technology that does not have a high degree of accuracy, stability, and reproducibility. In addition, it is possible to overcome the instability and nonlinearity of the voltage controlled oscillator by limiting the phase difference between the two signals input to the analog mixer up to 90 degrees.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, according to the present invention, the voltage-controlled oscillator using the conventional analog mixer is improved and improved, and has the following unique effects.

First, when the voltage controlled oscillator is implemented as an integrated circuit, the voltage controlled oscillation gain is improved to perform the voltage controlled oscillation function even when the accuracy, stability, and reproducibility of the process are not high. Second, the peak frequency drop and the instability and nonlinearity of the voltage controlled oscillator are overcome. Third, since the circuit in the variable delay element unit uses the electrically identical circuit, when the circuit design for one variable delay element unit is completed, there is an effect of facilitating the circuit design of the other variable delay element unit.

Claims (1)

A two-stage ring voltage controlled oscillator using a pair of variable delay elements comprising an analog mixer and at least one delay or inverting element to form a variable delay element portion, and two variable delay element portions configured in series. .