KR20010008674A - Bit line pull-up circuit for static random access memory - Google Patents

Abstract

PURPOSE: A bit line pull up circuit of SRAM is provided to cut a direct current of a direct equalizing portion using an auto power cutting signal cutting a word line CONSTITUTION: A pull up circuit includes a DC equalizing portion(120) and an AC equalizing portion(110). The DC equalizing portion outputs a power voltage to a bit line pair by an auto power cutting signal. The AC equalizing portion is inputted an equalization signal and equalizes the bit line pair by means of the power voltage. The DC equalizing portion includes first through fourth PMOS transistors. The first and second PMOS transistors respectively are conducted by a ground voltage and output a power voltage of a source to a drain. The third and fourth PMOS transistors are conducted and controlled by the auto power cutting signal and output a power voltage outputted from the first and second PMOS transistors of the source to a bit line and a bit line bar of the drain.

Description

BIT LINE PULL-UP CIRCUIT FOR STATIC RANDOM ACCESS MEMORY

The present invention relates to a bit line pull-up circuit of an SRAM, and more particularly, to a DC line of a direct current equalizer using an automatic power cut-off signal that blocks a word line by using a sum of signals detected by an external input in an S-RAM bit line pull-up circuit. It relates to a bit line pull-up circuit of an SRAM for breaking current.

1 is a core circuit diagram of a conventional SRAM, as shown in the bit line pair BL ( A bit line pull-up unit 20 for equalizing (); The bit line pair BL (by a word line signal WL) And a cell 10 for storing data applied through the bit line pull-up unit 20. The bit line pull-up unit 20 is always turned on to form the bit line pair BL. DC equalizer 22 for pulling up the power supply voltage VCC; The bit line pair BL (by the equalization signal EQ) The equalizer 21 is configured to equalize (), and the cell 10 is electrically controlled by the word line signal WL, so that the bit line BL and the bit line bar are respectively controlled. NMOS transistor NM1 (NM2) for transmitting ()); An inverter (11) composed of a PMOS and an NMOS transistor (PM2) (NM4) for receiving an output signal of the NMOS transistor (NM1) and inverting and outputting the output signal; The inverter 12 which receives the output signal of the NMOS transistor NM2 and the output signal of the inverter 11 through the PMOS and NMOS transistors PM1 and NM3 and inverts the output signal to the input terminal of the inverter 11. And the AC equalizer 21 is electrically controlled by the equalization signal EQ to control the source voltage VCC of the source and drain bit lines BL and bit line bars, respectively. PMOS transistors PM5 and PM6 which are outputted to the PMOS transistors; PMOS transistors PM7 connected to the drains of the PMOS transistors PM5 and PM6 by conduction control by the equalization signal EQ. The DC equalizers 22 are each gated and grounded. The power supply voltage VCC of the bit line BL and the bit line bar A PMOS transistor (PM3) (PM4) for outputting to the) is described in detail the operation process according to the prior art configured as described above.

First, the AC pull-up unit 21 constituted by PMOS transistors PM5 to PM7 conductingly controlled by the equalization signal EQ in the bit line pull-up unit 20 has a low potential equalization signal applied every time a new cycle is started. The bit line pair BL to the PMOS transistors PM5 to PM7 conducted by EQ. Precharge quickly.

In addition, the DC pull-up unit 22 may execute the bit line pair BL ( After the precharging is completed, when the word line WL is enabled, the bit line pair BL is turned on as the NMOS transistors NM1 and NM2 in the cell 10 are turned on. ) To receive and store data.

At this time, the bit line pair BL ( And a potential difference occurs between the PMOS transistors PM3 and PM4 applied with the ground voltage VSS to the gate of the DC pull-up unit 22. ) To limit the difference between

In the static state, the bit line pair BL ( The low node potentials of the transistors are PMOS transistors PM3 and PM4 in the pull-up unit 22 and NMOS transistors NM1 and NM2, which are access transistors in the cell 10, and inverters 12 and 11. It is determined by the equivalent resistance ratios of the internal MOS transistors PM1 and NM3 (PM2 and NM4). Accordingly, in order to reduce the equivalent resistance value, the PMOS transistors PM3 and PM4 of the DC pull-up unit 22 are reduced. The size will be set larger.

In addition, when the corresponding cell block is not selected or the chip is in the standby mode, the DC pull-up unit 22 compensates for the leakage caused by the cell or the like to compensate for the bit line pair BL ( ) Is maintained at the power supply voltage VCC level.

In addition, the bit line pull-up unit 20 maintains a constant conductance regardless of the power supply voltage VCC level as PMOS transistors PM3 to PM7 are used. Since the line responds quickly, a read-out characteristic when a VCC bump occurs, that is, a read and write characteristic of the cell 10 is guaranteed even when a power fluctuation is applied.

However, in the conventional SRAM as described above, the chip operating current increases as the current in the PMOS transistor operating in the direct current of the bit line pull-up part increases during the high power voltage operation, thereby increasing the ground voltage level of the cell, thereby causing noise effects. Noise was generated by the noise effect, causing a circuit malfunction.

Accordingly, the present invention has been made to solve the above-mentioned problems, and is made up of the sum of the signals detected by the external input to block the DC current of the DC equalizer by using an automatic power cutoff signal that blocks the word line. The purpose is to provide a bit line pull-up circuit of SRAM.

1 is a core circuit diagram of a conventional SRAM.

2 is a core circuit diagram of an SRAM to which the present invention is applied.

3 is a diagram illustrating waveforms of respective input and output voltages of FIG. 2;

*** Description of the symbols for the main parts of the drawings ***

100: bit line pull-up unit 110: AC equalizer

120: DC equalizer PM1 to PM9: PMOS transistor

NM1 to NM4: NMOS transistor

The configuration of the present invention for achieving the above object is a DC equalizer for outputting the power supply voltage to the bit line pair by the automatic power off signal; And an equalization unit configured to receive an equalization signal and equalize the bit line pair with a power supply voltage.

First and second PMOS transistors each of which is connected to the DC equalizer by a ground voltage and outputs a source power supply voltage to a drain; And third and fourth PMOS transistors which are electrically controlled by an automatic power cut-off signal and output power voltages output from the first and second PMOS transistors of the source to the bit lines and bit line bars of the drain, respectively. It features.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

2 is a core circuit diagram of an SRAM to which the present invention is applied, and as shown therein, a bit line pair BL ( A bit line pull-up unit 100 for equalizing (); The bit line pair BL (by a word line signal WL) And a cell 10 for storing data applied through the cell line 10, wherein the bit line pull-up unit 100 sets the power supply voltage VCC to the bit line pair BL by an automatic power cutoff signal APD. DC equalizer 120 for outputting; The bit line pair BL receives an equalization signal EQ. ) Is configured as an AC equalizer 110 for equalizing the power supply voltage VCC, and the DC equalizer 120 is electrically connected to the ground voltage VSS applied to the gate to supply the source power supply voltage VCC of the source. A PMOS transistor PM3 and PM4 output to the drain; The power supply voltage VCC, which is electrically controlled by the automatic power cut-off signal APD and is output from the PMOS transistors PM3 and PM4 of the source, respectively, has a bit line BL and a bit line bar of a drain. PMOS transistor (PM8) (PM9) output to the), the BC equalizer 110 and the cell 10 is configured in the same manner as in Figure 1, attached to the operation process according to the present invention configured as described above A detailed description will be given with reference to the voltage waveform diagram of FIG. 3.

First, when a valid address ADD is input as shown in FIG. 3A, an address transition detection signal ATD for detecting the same is generated as an internal control signal as shown in FIG. 3B.

Then, in the section where the equalization signal EQ is applied at a low potential as shown in FIG. 3C, the PMOS transistors PM5 to PM7 in the BC equalizer 120 are turned on to turn on the bit line pair BL ( Equalize () and at the same time enable an automatic power off signal (APD) that is enabled at low potential by the address transition detection signal (ATD) to disable word lines, sense amplifiers (not shown), and write drivers (not shown). It is applied to the direct current equalizing unit 110 as shown in 3 (d).

Accordingly, the DC equalizer 110 performs the bit line pair BL through the PMOS transistors PM8 and PM9 controlled by the automatic power cutoff signal APD output at a low potential. The power supply voltage VCC is applied to the pull-up, and when the automatic power cut-off signal APD is applied at a high potential, the word line signal WL is enabled as shown in FIG. By selecting a word line, the data stored in the cell 10 is transferred to the bit line pair BL as shown in FIG. )

As described above in detail, the present invention blocks the direct current of the direct current equalizer by using an automatic power cutoff signal that blocks the word line by the sum of the signals detected from the external input, thereby minimizing the amount of DC current at high power voltages. Therefore, there is an effect of preventing the occurrence of noise and malfunction of the circuit.

Claims (2)

A DC equalizer for outputting a power supply voltage as a bit line pair by an automatic power off signal; An SRAM bit line pull-up circuit, comprising: an equalization unit configured to receive an equalization signal and equalize the bit line pair to a power supply voltage. The semiconductor device of claim 1, wherein the DC equalizer comprises: first and second PMOS transistors respectively connected to the ground voltages to output a source power supply voltage to a drain; And third and fourth PMOS transistors which are electrically controlled by an automatic power cut-off signal and output power voltages output from the first and second PMOS transistors of the source to the bit lines and bit line bars of the drain, respectively. SRAM's bit line pull-up circuit.