KR20010008321A - Integrated chip for high frequency and fabricating method therefor - Google Patents

Abstract

PURPOSE: A high frequency laminated chip part and method of manufacturing the same is provided to cancel inductance by adjusting internal electrode pattern by which a current flow in the electrode is bent in a certain angle. CONSTITUTION: A number of device sheets(701) are prepared by using a slurry of a certain composition. First internal electrode pattern(702) is printed in the shape of S on the sheet so that a current flow is bent into reverse direction. Second internal electrode pattern(704) is printed in the opposite direction of the first pattern(702). At lease two device sheets(701) are stacked to form a laminate so that current flows are directed oppositely in internal electrodes(708,709) of adjacent upper and lower layers. The laminate is heat treated for aging. External electrodes(710) are formed on both ends of the laminate to be alternately connected to the internal electrodes(708,709).

Description

Integrated chip for high frequency and fabricating method therefor}

DETAILED DESCRIPTION The present invention provides a stacked chip capacitor, a stacked chip varistor, a stacked chip negative temperature coefficient (NTC) device, a stacked chip positive temperature coefficient (PTC) device, a stacked chip resistor, and the like. The present invention relates to a high frequency inductance chip component manufactured by specially designing an internal electrode pattern to reduce high frequency equivalent inductance and equivalent series resistance of a stacked chip component, and a method of manufacturing the same. It is characterized by a chip component and a manufacturing method that mutually cancel the inductance generated by designing the electrode pattern in the r-shape to reverse the current flow of the electrode pattern (180 degrees).

Recently, the frequency of personal portable communication and personal computers has been rapidly shifted to high frequency, such as the GHz band, and electronic components mounted therein are absolutely required to be used at high frequencies or have high frequency characteristics. In the case of chip components, in general, the characteristics of the chip part itself at low frequencies, for example, in the case of chip capacitors, are pure pure capacitors. (12) A component is generated. Equivalent series resistors cause unnecessary power consumption, while equivalent series inductances reduce the resonant frequency (LC or RC resonance) to cause parasitic oscillation or increase the impedance to slow down the response to the signal. In the case of chip varistor, it plays a role of protecting important electronic components such as high-density IC and digital IC from high frequency overvoltage and surge voltage. As described above, the response delay at high frequency caused by equivalent inductance is high frequency overvoltage and surge voltage. The electronic components can no longer be protected from.

In general, except for the chip inductor, the internal electrodes of the general multilayer chip component are stacked two terminal electrodes alternately with each other on two axes as shown in FIG. 2 to form two electrodes ultimately. As a result, current flow is formed, which is like the effect of hanging wires, causing inductance. In other words, in the case of a general multilayer chip capacitor, as shown in FIG. 2, the current starts to flow from one terminal (eg, the + terminal) to pass through the dielectric layer and enter the opposite electrode. As can be seen, when the current flows through the wire, the magnetic inductance is generated on the chip as the induced electromotive force of the opposite polarity to interrupt the current flow by magnetic induction.

As such, the conventional multilayer chip component has a problem in that equivalent series inductance and equivalent series resistance are generated when used at a high frequency.

In addition, the generation of unwanted equivalent series resistance and equivalent series inductance component causes unnecessary power consumption in case of equivalent series resistance, and in case of equivalent series inductance, the resonance frequency is lowered to cause parasitic oscillation or increase the impedance value. There is a problem of slowing down the response speed.

In addition, the conventional composite chip component has a problem that it is difficult to control the device characteristics of the chip due to the complexity and difficulty in the manufacturing process, it is difficult to array the multiple chip can accommodate.

SUMMARY OF THE INVENTION An object of the present invention for solving the conventional problems as described above is to manufacture a multilayer chip component device that cancels the inductance by adjusting the internal electrode pattern inside the chip component to bend the direction of current flow in the electrode at a predetermined angle. There is. It is also an object of the present invention to provide a manufacturing method for manufacturing such a stacked chip component device.

In particular, by designing the internal electrode pattern in the chip in the form of a letter r, the current flow of the electrode pattern is reversed (180 degrees) to cancel the mutually generated inductance to produce a stacked chip component device having the desired device characteristics even at high frequencies There is a purpose.

In addition, it is an object of the present invention to manufacture a composite chip component having various device characteristics by minimizing the equivalent inductance value by monolayering or stacking an internal electrode pattern having a current direction difference inside the device, and by changing the number of stacked layers.

Fig. 1 High frequency equivalent circuit of capacitor

2 is a block diagram of a conventional stacked chip component

3 is a manufacturing diagram of the stacked chip component according to the first embodiment of the present invention

Figure 4 is a schematic diagram of the current direction of the stacked chip component manufactured by Example 1 of the present invention.

5 is a manufacturing diagram of the stacked chip component according to the second embodiment of the present invention

6 is a schematic diagram of current direction of a multilayer chip component manufactured by Example 2 of the present invention.

7 is a manufacturing diagram of the stacked chip component according to the third embodiment of the present invention

8 is a manufacturing diagram of a stacked chip component having an array structure according to the fourth embodiment of the present invention

9 is a manufacturing diagram of a stacked chip component having an array structure according to the fifth embodiment of the present invention.

The stacked chip component device according to the present invention for solving the object as described above is produced in a thin ceramic sheet (Sheet) using a doctor blade method, etc., a slurry of a predetermined composition prepared according to the desired device characteristics, and the desired After printing the internal electrode pattern in the form, and stacking the sheet with the internal electrode formed by the desired number together, the laminate is fired, and is formed by forming an external electrode connected to each internal electrode. At this time, the internal electrode pattern is designed as an internal electrode pattern bent at a predetermined angle so that the direction of current flow in the device is bent at a predetermined angle to cancel the inductance. The internal electrode pattern is preferably designed to be bent by 180 degrees to form a letter-shaped on the same sheet. In addition, when the sheets on which the predetermined internal electrode patterns are printed are laminated by the desired device characteristics, the internal electrode patterns of the upper and lower layers to be laminated are arranged in the opposite direction so that the direction of current flow is bent at a predetermined angle at the same position. It is preferable to design in a pattern bent at a predetermined angle.

In addition, the composite chip device according to the present invention for solving the above object is to produce a thin ceramic sheet using a doctor blade method or the like with a slurry of a predetermined composition prepared in accordance with the desired device characteristics, and a conductive paste on the ceramic sheet The internal electrode pattern designed by the internal electrode pattern folded at a predetermined angle so as to cancel the inductance by printing by bending the direction of current flow in the device at a predetermined angle, laminating the sheet with the internal electrode formed as many times as desired, and then stacking the stack It bakes and manufactures by forming the terminal electrode connected with the internal electrode of a laminated body. In this case, it is preferable that the internal electrode pattern is designed to be bent at 180 degrees by forming the letter L on the same sheet.If the internal electrode patterns are arranged in the width direction of the chip, the area where the current flows is increased to decrease the equivalent series resistance and the current is 180 degrees. By increasing the length of the break, the inductance can be more and more canceled out, ultimately lowering the equivalent series inductance. In addition, increasing the number of stacked layers of the sheet on which the internal electrode patterns are formed increases the area of the internal electrodes, further reducing the equivalent series resistance.

In addition, the composite chip device according to the present invention for solving the above object is to produce a thin ceramic sheet using a doctor blade method or the like with a slurry of a predetermined composition prepared in accordance with the desired device characteristics, and a conductive paste on the ceramic sheet The internal electrode pattern designed by the internal electrode pattern folded at a predetermined angle so as to cancel the inductance by printing by bending the direction of current flow in the device at a predetermined angle, laminating the sheet with the internal electrode formed as many times as desired, and then stacking the stack It bakes and manufactures by forming the terminal electrode connected with the internal electrode of a laminated body. In this case, the inner electrode pattern is preferably designed to be bent at 180 degrees by forming a L-shape on the same sheet, and is also designed so that the direction of the current and the adjacent layer in the middle layer of the chip is 180 degrees and is not connected to the external electrodes on both sides of the chip. The addition of a floating electrode not only lowers the equivalent inductance, but also widens the internal electrode, effectively reducing the equivalent series resistance.

In addition, the composite chip according to the present invention may change the internal electrode pattern of the device or the number of laminated sheets of the device layer according to the purpose of use thereof. For example, the equivalent series resistance of the chip is reduced by increasing the area of the internal electrode or increasing the number of stacked layers, and the capacitance value is changed by changing the number of laminated sheets of the element layer, for example, the capacitor layer.

An embodiment of manufacturing a stacked chip component device according to an exemplary embodiment of the present invention will be described in detail with reference to a stacked chip capacitor.

Example 1.

Using a commercially available raw material powder for capacitor devices, a slurry for the device is manufactured in a desired composition, and the slurry is formed into a ceramic molded sheet having a desired thickness as shown in FIG. 3 by a doctor blade or the like. (301, Ceramic Green sheet).

In order to manufacture a capacitor layer, a conductive sheet such as silver (Ag), silver-palladium (Ag-Pd), or nickel (Ni) paste, which is commercially available on the ceramic sheet manufactured as described above, is used as shown in FIG. The internal electrode pattern is printed so as to be repeatedly connected one or more times in a L-shape in the longitudinal direction (L direction). That is, the first capacitor sheet 303 is manufactured by designing the first internal electrode pattern 302 which is bent by 180 degrees in the shape of R, and printing by screen printing method, and the like. The second capacitor sheet 305 is manufactured by designing the second internal electrode pattern 304 having a r-shape in which the flow is reversed and printing by screen printing or the like.

When the first and second sheets printed with the L-shaped internal electrode patterns in the longitudinal direction of the ceramic sheet are alternately stacked as many times as desired, and each sheet is laminated by covering the cover sheet 306 with FIGS. As described above, the inner electrode patterns are alternately connected to the outer electrodes at both ends of the stack, and then pressed by applying heat and pressure so that the stacked layers are in close contact.

In order to remove all the organic components such as various binders in the laminate 307 prepared as described above, after baking at a suitable temperature and bake-out, the temperature is raised to sinter the laminate at an appropriate firing temperature, and then fired. An external electrode 309 connected to the internal electrode 308 of the stack 307 is formed on the outside of the stacked stack as shown in FIG. 3B to manufacture a stacked capacitor chip.

In the multilayer capacitor chip manufactured as described above, when the positive / negative voltage is applied to the external electrodes at both ends, the current flow direction of the internal electrode formed on the surface of the capacitor sheet is changed to the internal electrode pattern in each layer. As a result, the direction of the current is reversed by 180 degrees to interfere with each of the electromagnetic fields generated by the current flow, thereby canceling the inductance. As shown in FIG. 4A, the first and second internal electrode patterns 401 and 402 of the upper and lower layers are cancelled. Since the current flows in reverse direction (180 degrees), the inductance is further canceled, and the equivalent inductance is greatly reduced even when used at high frequency. In addition, as shown in FIG. 4B, even when the internal electrode pattern having the letter “L” is repeatedly designed a plurality of times in one layer, the direction of current flow in the layer and the direction of current flow between adjacent layers 403 and 404 are opposite to each other. Therefore, the inductance is canceled out.

Example 2.

Another embodiment of a multilayer capacitor chip component is a multilayer capacitor chip component in which an equivalent series resistance is reduced by increasing an electrode area through which current flows while further reducing inductance of capacitance components generated at high frequencies.

In the same manner as in Example 1, a plurality of ceramic sheets 501 for capacitor devices are manufactured.

In order to manufacture the capacitor layer, a conductive sheet such as silver (Ag), silver-palladium (Ag-Pd), or nickel (Ni), which is commercially available on the ceramic sheet manufactured as described above, is used to The internal electrode pattern is printed so as to be repeatedly connected one or more times in the letter L shape in the width direction (W direction). That is, the first capacitor sheet 503 is manufactured by designing the first internal electrode pattern 502 that is bent 180 degrees in the shape of R, by printing by screen printing or the like in the width direction of the ceramic sheet, and manufacturing the first capacitor sheet 503 at the same position of the ceramic sheet. The second capacitor sheet 505 is manufactured by designing a second internal electrode pattern 504 having a letter-shape in which an internal electrode pattern and a current flow are reversed, and printing the same by a screen printing method. Since the internal electrode patterns are printed in the width direction of the sheet as shown in FIG. 5A, the area of the internal electrodes through which current flows increases. In addition, the absolute length of the r-shaped internal electrode flows by 180 degrees, and thus the length becomes longer, so that the equivalent inductance can be further reduced by further canceling mutual inductance.

When the first and second sheets with the L-shaped internal electrode patterns printed in the width direction of the ceramic sheet are alternately stacked as many times as desired, and the sheets are covered by covering the cover sheet 506, the sheets of FIGS. As described above, the inner electrode patterns are alternately connected to the outer electrodes at both ends of the stack, and then pressed by applying heat and pressure so that the stacked layers are in close contact.

In order to remove all the organic components such as various binders in the laminate 507 prepared as described above, after baking at a suitable temperature and bake-out, the temperature is raised to sinter the laminate at an appropriate firing temperature, and then fired. An external electrode 509 connected to the internal electrodes 508 of the stack 507 is formed at both ends of the outside of the stacked stack 507 to manufacture a stacked capacitor chip.

In the multilayer capacitor chip manufactured as described above, when the positive / negative voltage is applied to the external electrodes at both ends, the current flow direction of the internal electrodes formed on the surface of the capacitor sheet has the internal electrode pattern in each layer. As a result, the direction of the current is reversed by 180 degrees to interfere with each electromagnetic field generated by the current flow, and thus the inductance is canceled, and the direction of the current is also reversed between the first and second internal electrode patterns 601 and 602 of the upper and lower layers. 180 degrees), the inductance is further canceled and the equivalent inductance is greatly reduced even when used at high frequencies. At this time, as shown in FIG. 6 (b), even if the internal electrode pattern of the letter “R” is repeatedly designed a plurality of times in one layer, the direction of current flow in the layer and the direction of current flow between adjacent layers 603 and 604 are opposite to each other. Therefore, the inductance is canceled out. In addition, since the internal electrode pattern is designed in the form of a letter “L” in the width direction, the area of the current flows to increase the equivalent series resistance, and the flow of the current which is bent by 180 degrees becomes longer, thereby reducing the equivalent series inductance and increasing the number of stacked layers. As the area of the internal electrode increases, the equivalent series resistance is further reduced.

Example 3.

Another embodiment of a multilayer capacitor chip component is a capacitor generated at high frequency by adding a floating internal electrode which is designed so that the direction of the current and the adjacent layer are reversed in the middle layer of the chip and not connected to the external electrodes on both sides of the chip. It is a multilayer capacitor chip component that reduces the equivalent series resistance by reducing the inductance of the component and increasing the electrode area through which current flows.

In the same manner as in Example 1, a plurality of ceramic sheets 701 for capacitor devices are manufactured.

In order to manufacture a capacitor layer, a conductive paste such as silver (Ag), silver-palladium (Ag-Pd), or nickel (Ni) paste, which is commercially available on the ceramic sheet manufactured as described above, is used to form a ceramic sheet as shown in FIG. The internal electrode pattern is printed so as to be repeatedly connected one or more times in the letter L form. That is, the first capacitor sheet 703 is formed by printing the first internal electrode pattern 702, which is connected to the voltage terminals at both ends of the sheet and insulated at the center part by a screen printing method, by an internal electrode pattern that is bent 180 degrees in the shape of a letter. And a second internal electrode pattern 704 having a floating L-shape in which the flow of the first internal electrode pattern and the current are reversed at the same position of the ceramic sheet and insulated from the voltage terminals at both ends thereof. The second capacitor sheet 705 is manufactured by printing by screen printing or the like.

As described above, when the first and second sheets having the L-shaped internal electrode patterns printed on the ceramic sheet are alternately stacked as many times as desired, and the cover sheets are stacked to cover each sheet, the first internal electrodes (as shown in FIG. 708 is connected to an external electrode at both ends of the stack, and the floating second internal electrode 709 is insulated from the external electrode and then pressed by applying heat and pressure to bring the stacked layers into close contact.

In order to remove all the organic components such as various binders in the laminate prepared as described above, after baking at a suitable temperature to bake out, the temperature is raised to sinter the laminate at an appropriate firing temperature, and the calcined laminate An external electrode 710 connected to the first internal electrode 708 of the stack 707 is formed outside the 707 to manufacture a multilayer capacitor chip.

In the multilayer capacitor chip in which the floating electrode is manufactured as described above, when a positive / negative voltage is applied to the external electrodes at both ends, the current flow direction of the internal electrodes formed on the surface of the capacitor sheet is along the inner electrode pattern in each layer. Since the direction of the current is reversed by 180 degrees to interfere with each electromagnetic field generated by the current flow as shown in the electric field schematic diagram 711 of FIG. 7 (b), the inductance is canceled, and the first internal electrode pattern of the upper and lower layers is suspended. Since the direction of the current flows also reversely between the second internal electrode patterns 702 and 704, the inductance is further canceled, so that the equivalent inductance is greatly reduced even when used at a high frequency. Also, by inserting the second internal electrode pattern suspended in the intermediate layer, the equivalent series resistance is reduced since the area of the internal electrode for obtaining the same capacitance is increased compared with a general multilayer capacitor that does not use the floating electrode.

In addition, when the floating electrode designed as described above is inserted into a stacked varistor chip component, the same characteristics are realized as compared with a varistor having no floating electrode installed, but the capacitance is lowered, thereby increasing the response speed.

Example 4.

The stacked chip component manufactured as described above is designed not as a pattern of a stacked chip having one internal electrode pattern, but as a pattern of a plurality of stacked stacked chips, for example, four or more repeated stacked chips, and then stacked chips as described above. 8 to produce an array chip in which unit device chips having a parallel structure are repeated as shown in FIG. 8.

In the same manner as in Example 1, a plurality of ceramic sheets 801 for capacitor devices are manufactured. At this time, the ceramic sheet is sized according to the arrangement and structure of the array.

In order to manufacture the capacitor layer, a conductive paste such as silver (Ag), silver-palladium (Ag-Pd), or nickel (Ni) paste, which is commercially available on the ceramic sheet manufactured as described above, is used to form the ceramic sheet as shown in FIG. Print a plurality of internal electrode patterns that are repeatedly connected one or more times in the r-shape. That is, when the first internal electrode pattern 802 bent 180 degrees in a letter shape to manufacture a plurality of elements, for example, an array element of four elements on the same sheet, four internal electrode patterns on one ceramic sheet may be used. Is printed by screen printing or the like to manufacture the first capacitor sheet 803, and the second internal electrode pattern 804 having a r-shape in which the flow of the current is reversed from the first internal electrode pattern at the same position of the adjacent ceramic sheet. The second capacitor sheet 805 is manufactured by printing the same number of internal electrode patterns as the internal electrode patterns printed on the first capacitor sheet by screen printing or the like.

As described above, when the first and second sheets having a plurality of internal electrode patterns printed on the ceramic sheet are alternately stacked as many times as desired, and the cover sheets 806 are covered to stack the respective sheets, the internal electrodes as shown in FIG. The patterns are alternately connected to the external electrodes at both ends of the stack, and then pressed by applying heat and pressure to bring the stacked layers into close contact.

In order to remove all the organic components such as various binders in the laminate prepared as described above, after baking at a suitable temperature to bake out, the temperature is raised to sinter the laminate at an appropriate firing temperature, and the calcined laminate A plurality of external electrodes 808 connected to a plurality of internal electrodes of the laminate 807 are formed outside as shown in FIG. 8B to manufacture a multilayer capacitor chip having an array structure.

In the multilayer capacitor chip of the array structure manufactured as described above, when the positive / negative voltage is applied to the external electrodes at both ends, the current flow direction of the internal electrode formed on the surface of the capacitor sheet is along the inner electrode pattern in one internal electrode pattern. Since the direction of the current is reversed by 180 degrees to interfere with each electromagnetic field generated by the current flow, the inductance is canceled, and the direction of the current is reversed between adjacent internal electrode patterns on the same ceramic sheet to cancel the inductance. Since the direction of current flows also reversely between the first and second internal electrode patterns 802 and 804, the inductance is further canceled, so that the equivalent inductance is greatly reduced even when used at a high frequency. In this case, even if one internal electrode pattern is repeatedly designed in the form of a letter “L” in one layer, the inductance is canceled because the direction of current flow in the layer and the direction of current flow between adjacent layers are opposite to each other.

Example 5.

Another embodiment of the multilayer capacitor chip component of the array structure is designed with a plurality of chip patterns, and the floating layer is designed to be 180 degrees in the direction of the adjacent layer and the current in the middle layer of the chip and is not connected to the external electrode. In addition, an array structure multilayer capacitor chip component that reduces the inductance of capacitance components generated at high frequencies and increases the electrode area through which current flows, thereby reducing equivalent series resistance.

In the same manner as in Example 1, a plurality of ceramic sheets 901 for capacitor devices are manufactured. At this time, the ceramic sheet is sized according to the arrangement and structure of the array.

In order to manufacture the capacitor layer, a conductive paste such as silver (Ag), silver-palladium (Ag-Pd), or nickel (Ni) paste, which is commercially available on the ceramic sheet manufactured as described above, is used to attach the ceramic sheet to the ceramic sheet as shown in FIG. Print a plurality of internal electrode patterns that are repeatedly connected one or more times in the r-shape. That is, a plurality of first internal electrode patterns 902 connected to the voltage terminals at both ends of the sheet and insulated from the center portion of the internal electrode pattern bent by 180 degrees in the shape of a letter, for example, as many as four elements on the same sheet. In the case of manufacturing an array element, four internal electrode patterns are printed on one ceramic sheet by screen printing or the like to manufacture the first capacitor sheet 903, and the first internal electrode patterns are formed at the same positions of adjacent ceramic sheets. Designed as a floating L-shaped second internal electrode pattern 904 in which current flow is reversed and insulated from voltage terminals at both ends, the same number of internal electrode patterns printed on the first capacitor sheet 2 The second capacitor sheet 905 is manufactured by printing the internal electrode patterns by screen printing or the like.

As described above, when the first and second sheets printed with the r-shaped internal electrode patterns on the ceramic sheet are alternately stacked as many times as desired, and each sheet is stacked by covering the cover sheet, as shown in FIG. The electrode pattern is connected to the external electrode at both ends of the stack, and the floating second internal electrode is insulated from the external electrode and then pressed by applying heat and pressure to bring the laminated layer into close contact.

In order to remove all the organic components such as various binders in the laminate, it is heated at a suitable temperature to bake out and then the temperature is raised to sinter the laminate at a suitable firing temperature. As described above, a plurality of external electrodes 908 connected to the plurality of first internal electrodes of the stack 907 are formed to manufacture the stacked capacitor chip.

In the multilayer capacitor chip of the array structure in which the floating electrode is inserted as described above, when a positive / negative voltage is applied to the external electrodes at both ends, the current flow direction of the internal electrode formed on the surface of the capacitor sheet is in the inner layer. 180 degrees along the pattern reverses the direction of the current and interferes with each of the electromagnetic fields generated by the current flow, canceling the inductance, and the direction of the current is reversed between adjacent internal electrode patterns on the same ceramic sheet to cancel the inductance. In addition, since the direction of current flows inversely between the first internal electrode patterns of the upper and lower layers and the floating second internal electrode patterns 902 and 904, the inductance is further canceled, so that the equivalent inductance is greatly reduced even when used at a high frequency. Also, by inserting the second internal electrode pattern suspended in the intermediate layer, the equivalent series resistance is reduced since the area of the internal electrode for obtaining the same capacitance is increased compared with a general multilayer capacitor that does not use the floating electrode.

In addition to the above-described devices, a technology for manufacturing a stacked composite chip manufactured as described above may include various stacked chips such as a stacked chip varistor, a stacked chip NTC, a stacked chip PTC device, or a stacked chip resistor. (Chip) Used to manufacture parts. Based on the basic structure of the above embodiment, the internal electrode pattern is designed in various patterns so that the current flow of the internal electrode pattern is reversed on the same sheet (180 degrees) and reversed in the adjacent layers to cancel the inductance generated. By controlling the design of the pattern and the number of stacked layers, a high frequency stacked chip component device having desired device characteristics is manufactured.

The technology for manufacturing a multilayer chip component manufactured as described above easily manufactures a multi-chip module (MCM) device in which a composite device combining chip or a single device structure is incorporated, and combines two or more devices according to desired device characteristics. It can be applied in various ways to manufacture a device for a composite electronic component manufactured by.

As described above, the stacked chip device according to the present invention changes the internal electrode pattern so that the current flow of the internal electrode pattern interferes with the electromagnetic field to cancel the inductance, and the current flow in the opposite direction is generated between the adjacent internal electrodes to reduce the inductance. It is manufactured as a stacked chip device with minimum equivalent inductance and can be used as a stable chip component even at high frequency.

Therefore, by manufacturing a multilayer chip component as described above, the present invention can be used as a stable chip component even at a high frequency, and manufactures a compact, thin and compact multilayer chip component that realizes desired electrical characteristics by a simple process without adding a separate process. There is an effect that can be done.

The stacked chip device of the present invention described above has the effect of manufacturing a stacked chip component having reduced equivalent series resistance by controlling the area and the number of stacked layers of the internal electrode patterns in the same chip.

In addition, the stacked chip device of the present invention described above has an effect of manufacturing an element having a reduced equivalent series resistance by inserting a floating electrode insulated from the external electrode to increase the internal electrode area.

In addition, since the multilayer chip device as described above is manufactured by a simple process without adding a separate process, the production cost is lowered, and the multilayer chip device having an array structure can be easily manufactured.

Claims (20)

In the stacked chip component device, A stacked chip component device in which an internal electrode pattern having a L-shape is designed such that current flow is reversed in a predetermined layer. The multilayer chip component device of claim 1, wherein a plurality of internal electrode patterns are stacked to reverse current flow between adjacent layers. In the stacked chip component device, A body in which at least two layers of a plurality of element sheets having desired characteristics are laminated; Internal electrodes formed on the stacked element sheets, An external electrode formed at an end of a body in which the element sheets having the internal electrodes formed thereon are laminated, and connected to the internal electrodes; Stacked chip component device, characterized in that the internal electrode of the predetermined sheet is designed as an internal electrode pattern of the L-shape so that the current flow is reversed. The multilayer chip component device according to claim 4, wherein the current flow is reversed between adjacent layers of the upper and lower parts in the multilayer electrode stack. In the stacked chip component device, A body in which at least two layers of a plurality of element sheets having desired characteristics are laminated; Internal electrodes formed on the stacked element sheets, An external electrode formed at an end of a body in which the element sheets having the internal electrodes formed thereon are laminated, and connected to the internal electrodes; The internal electrode of the predetermined sheet is a laminated chip component device characterized in that the r-shape so that the current flow is reversely reversed and is designed in the width direction of the device sheet. 6. The stacked chip component device of claim 5, wherein the current flow is reversed between upper and lower adjacent layers in the plurality of stacked internal electrode patterns. In the stacked chip component device, A body in which at least two layers of a plurality of element sheets having desired characteristics are laminated; A first internal electrode connected to a voltage terminal at both ends of the sheet and insulated from a central portion thereof by an internal electrode pattern having a L-shape so that the current flow formed on the stacked element sheets is reversed; A floating second internal electrode having a L-shape formed on the stacked sheet for device and having a current flow opposite to that of the first internal electrode and insulated from the external electrode; Stacked chip component device, characterized in that the sheet for the element formed with the inner electrode is formed at the end of the laminated body is connected to both ends of the first inner electrode is connected to the outer electrode. The multilayer chip component device of claim 1, wherein the internal electrode pattern is designed such that the letter-shaped pattern is repeatedly connected a plurality of times. 8. The stacked chip component device according to any one of claims 1 to 7, wherein the stacked chip component is a stacked chip capacitor, a stacked chip varistor, a stacked chip NTC device, a stacked chip PTC device, or a stacked chip resistor. The multilayer chip component device according to any one of claims 1 to 7, wherein two or more kinds of stacked chip components are combined to form a composite device. 8. The stacked chip component device according to any one of claims 1 to 7, wherein the stacked chip component is manufactured from an array type stacked element in which a plurality of chips are repeated. 12. The stacked chip component device according to claim 11, wherein the plurality of chips are manufactured so that the direction of the currents of adjacent internal electrodes on the same sheet is reversed in the stacked type device having the repeated array. 8. A multi-chip module (MCM) device according to any one of claims 1 to 7, wherein said stacked chip component device is incorporated. In the manufacturing method of a laminated chip component element, Manufacturing a device sheet using a slurry having a predetermined composition, Forming an internal electrode by printing an internal electrode pattern having a letter L shape on the sheet such that the direction of current flow is reversed; Stacking at least two or more layers of the molded sheet on which the internal electrode patterns are printed to form a laminate in which current flow of the internal electrodes of upper and lower adjacent layers is reversed; Calcining the laminate by heat treatment, And forming external electrodes alternately connected to the internal electrodes at both ends of the stack. In the manufacturing method of a laminated chip component element, Manufacturing a device sheet using a slurry having a predetermined composition, Forming an internal electrode by printing an internal electrode pattern having a letter L shape in the width direction of the sheet so that the direction of current flow is reversed on the sheet; Stacking at least two or more layers of the molded sheet on which the internal electrode patterns are printed to form a laminate in which current flow of the internal electrodes of upper and lower adjacent layers is reversed; Calcining the laminate by heat treatment, And forming external electrodes alternately connected to the internal electrodes at both ends of the stack. In the manufacturing method of a laminated chip component element, Manufacturing a device sheet using a slurry having a predetermined composition, Forming a first internal electrode connected to the voltage terminals at both ends of the sheet and insulated from the center by an internal electrode pattern having a L-shape so as to reverse the flow of current on the device sheet; Forming a floating second internal electrode having a r-shape on the device sheet, in which a current flows opposite to the first internal electrode and is insulated from the external electrode, Stacking at least two layers of the device sheets on which the first and second internal electrode patterns are printed alternately to form a laminate in which current flow of internal electrodes of upper and lower adjacent layers is reversed; Calcining the laminate by heat treatment, And forming an external electrode connected to the first internal electrode at both ends of the stack. 17. The method of claim 14, wherein the internal electrode pattern is designed such that the r-shape is repeatedly connected a plurality of times. The multilayer chip component element according to any one of claims 14 to 16, wherein the stacked chip component is a stacked chip capacitor, a stacked chip varistor, a stacked chip NTC device, a stacked chip PTC device, or a stacked chip resistor. Manufacturing method. The method of manufacturing a stacked chip component device according to any one of claims 14 to 16, wherein the stacked chip component is a combination of two or more different chip components to produce a composite device. The method of manufacturing a stacked chip component device according to any one of claims 14 to 16, wherein the stacked chip component is manufactured as an array type stacked element in which a plurality of chips are repeated.