KR20010007175A - Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics - Google Patents

Abstract

PURPOSE: An integrated video processing system having plural video source for realizing picture-in-picture by on-screen display graphics is provided to apply simultaneous plural picture display functions by adding a P-in-P function at the minimum costs to an integrated digital video system such as a digital video set top box or a digital video disk player. CONSTITUTION: A 2:1 MUX(202) selects any of an extended video, a non- compressed video, and a video obtained by setting the expanded or non- compressed video in a P-in-P display support according to a pixel selection control signal from a processor, and transmits it to an OSD mixing logic(204) as a basic input. Also, the arrangement and size of inserted pictures can be arbitrarily controlled. Moreover, ODS graphics can be superimposed on an OSD mixing logic(204), and they are integrated and transmitted to a display device. Those functions can be integrated into an integrated digital video system as one chip.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-screen display forming method and system for an asynchronous screen television system, an analog video signal processing method and system thereof, and a product implementing the method and systems using a computer program. PICTURE-IN-PICTURE WITH ON-SCREEN DISPLAY GRAPHICS}

This application is a continuation-in-part of co-pending U.S. Serial No. 09 / 237,601, co-assigned by Campisano et al. Entitled " MPEG Video Decoder With Integrated Scaling And Display Functions " And the contents thereof are referred to.

This application also incorporates the subject matter of the following U.S. patent application and patent application assigned to the assignee of the present application. Each of the applications described below are incorporated herein by reference.

- U.S. Patent Application No. (Attorney Docket No. EN998086), co-filed with the present application: "Programmable External Graphics / Video Port For Digital Video Decode System Chip" by Cheney et al.

US Patent Application Serial No. 09 / 237,600 entitled " Anti-Flicker Logic For MPEG Video Decoder With Integrated Scaling And Display Functions "by D. Hrusecky et al.

US Patent Application Serial No. 09 / 094,753, entitled " Color Mapped And Direct Color OSD Region Processor With Support For 4: 2: 2 Profile Decode Function "by Hrusecky et al.

- U.S. Patent No. 5,576,665: "Video Decoder" by Cheney et al.

The present invention relates generally to video signal processing and, more particularly, to a method and apparatus for processing compressed digital video signals, with or without overlaying of on-screen display graphics, And an integrated digital video processing system capable of receiving uncompressed analog video signals and merging them into a picture-in-picture display. As an example, the integrated digital video processing system may be implemented as a digital video set-top box (STB) or a digital video disc (DVD) player.

Today, it is common to integrate multiple functions into a single system chip. For example, in order to improve the marketability of integrated digital video processing system chips such as set-top boxes or digital video system chips for digital video disc players, it may be desirable to allow external inputs or functions to be connected to the integrated system chip .

In general, a picture-in-picture television system displays a picture with a main screen and a number of sub-screens, wherein the sub-screen is displayed on the main screen They are arranged in predefined locations and have the same image source. Conventionally, a television system includes or does not include a co-screen module, in which case the television system includes a non-picture-in-picture system. The co-screen feature of a television system is typically different between a high-end television system and a low-end television system. A system that provides a co-screen often involves a considerable additional load than a similar television that does not have a co-screen.

It would be desirable to provide an unscreened television system capable of simultaneously displaying multiple pictures by adding a co-screen feature to an integrated digital video system, such as a digital video decode set-top box or a digital video disk player, As shown in FIG.

In summary, in one aspect, the invention includes a method of forming a multi-screen display for presentation to an unscreened television system. The method includes receiving and decoding a compressed digital video signal to generate a decompressed digital video signal, receiving the decompressed video signal, And combining the digital video signal and the uncompressed video signal to generate a multi-screen display signal for the television system, thereby providing an unscreened television system capable of simultaneously displaying multiple screens.

In another aspect, the present disclosure provides a method of processing an analog video signal. The method includes digitizing an analog video signal for input to a digital video processing system, and blending the digitized video signal with on-screen display (OSD) graphics in a digital video processing system .

In another aspect, a system is provided for forming a multi-screen display for an asynchronous screen television system. The system includes a video decoder that decodes a compressed digital video signal from a first video source to generate a decompressed digital video signal. The video decoder of the system also includes an input for receiving an uncompressed video signal from a second video source. The video decoder is adapted to combine the decompressed digital video signal and the uncompressed video signal to generate a multi-screen display for the television system, thus providing an unscreened television system capable of simultaneously displaying multiple screens.

In another aspect, a system for processing an analog video signal is provided. The system includes a digital video processing system and a digital multi-standard decoder. A digital multi-standard decoder digitizes an analog video signal for input to a digital video processing system. The digital video processing system is adapted to combine digitized video signals with on-screen display (OSD) graphics and output the combined video signals.

In yet another aspect, the present invention provides a computer usable medium having computer readable program code means therein for forming a multi-screen display for an asynchronous screen television system, The article of manufacture comprising a computer program product having a computer program product. The computer program product code means of the computer program product comprises computer readable program code means for causing a computer to perform decoding of a compressed digital video signal to generate a decompressed digital video signal, Computer readable program code means for causing the computer to perform the merging of the decompressed digital video signal and the uncompressed video signal to cause a multi-screen display for the television system to occur, A non-simultaneous screen television system capable of simultaneously displaying multiple images is provided.

In another aspect, the invention includes an article of manufacture comprising a computer program product having a computer usable medium having computer readable program code means therein for processing analog video signals. The computer readable program code means in the computer program product comprises computer readable program code means for causing a computer to perform digitization of an analog video signal and means for causing the computer to convert the digitized video signal to on- Screen display (OSD) graphics. ≪ RTI ID = 0.0 > [0002] < / RTI >

In other words, the present invention provides, as an embodiment, an integrated digital video processing system capable of receiving compressed digital video signals and uncompressed analog video signals and incorporating them into a co-screen display, for a television system with no co-picture capability do. As an improvement thereof, it is also possible that the co-screen display generated by the integrated digital video processing system overlaps with the on-screen display (OSD) graphics. As an alternative embodiment, an integrated digital video processing system is provided in which an analog video signal is received and can be overlapped with OSD graphics before being presented to the television system for display.

An integrated digital video processing system may be implemented as a digital video set top box (STB) or a digital video disk (DVD) player as an example. According to the present invention, besides minimizing the addition of the production cost, the OSD graphics overlapping capability as well as the simultaneous display capability can be added through the set-top box controller chip. Uncompressed analog video forming part of the final coincidental picture may be transmitted to a number of sources including video cassette recorders, camcorders, television cameras, laser discs, DVD players, computers with TV outputs, cable television signals, phase analog channels, ≪ / RTI > Advantageously, as one embodiment of the present invention, since the mixing / combining of uncompressed video and decompressed video is performed in the final stages of video processing with respect to the video decoder, the logic necessary to provide video decompression and on- Continues to freely release video decompression, display refresh, and video downscaling.

1 is a general block diagram of a video decoder unit,

Figure 2 is a block diagram of a video decoding system that implements a co-screen with on-screen display (OSD) graphics in accordance with the principles of the present invention;

Figure 3 is a block diagram illustrating a multiple screen display (i.e., a piconet) implemented in accordance with the principles of the present invention;

4 is a block diagram of one embodiment of an integrated video decode system in accordance with the principles of the present invention having a first digital video source and a second analog video source for inputting video signals for merging into an integrated system,

5 illustrates in detail one technique for merging decompressed digital video and uncompressed analog video into a multi-screen display, with the ability to combine the final video with on-screen display (OSD) graphics, in accordance with the principles of the present invention The drawings,

Figure 6 is a detailed illustration of a video decoding system in accordance with the principles of the present invention,

6A is a diagram illustrating frame buffer subdivisions in normal mode and video scaling mode according to the present invention,

Figure 7A is a timing diagram showing delayed display timings in a video scaling mode in accordance with the principles of the present invention;

FIG. 7B is a diagram illustrating an example of switching of the small frame buffers 2, 4, 6 of FIG. 6A according to the present invention,

Figure 8 is a block diagram of one embodiment of a decimation unit in accordance with the principles of the present invention in connection with the video decoding system of Figure 6;

Figure 9 is a block diagram of one embodiment of display mode switch logic in accordance with the principles of the present invention in connection with the video decoding system of Figure 6;

Figure 10 is a flow diagram of one embodiment of a process implemented by the sync generator of Figure 9 in accordance with the principles of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

40: Decode system 52: Memory controller

54: Video decoder 58: Display and OSD interface

59: Digital Video Encoder / Digital-to-Analog Converter

100: Integrated Digital Video Decode System

105: Digital multi-standard decoder (DMSD)

106: Video decoder // Display and OSD logic

107: Internal Digital Video Encoder (DENC) macro

202: 2: 1 multiplexer 204: OSD combination logic

653: SDRAM frame buffer memory 678: motion compensator

682: Decimation unit 692: Display fetch unit

694: Up sample logic

696: Display mode switch logic

The foregoing objects, advantages and features of the present invention and others will become more readily apparent when the following detailed description of certain preferred embodiments of the invention is taken in conjunction with the accompanying drawings.

Broadly speaking, the present invention provides an integrated digital video decode system, such as a digital video set-top box (STB) or a digital video disk (DVD) player, for example, which provides co-picture capability to an unscreened television system. Further, the present disclosure provides an integrated digital video processing system capable of combining on-screen graphics with uncompressed analog input signals from, for example, a cable, satellite, video cassette recorder or external tuner. The integrated digital video processing system can also combine OSD graphics with its composite multi-screen display.

The input of an analog (or secondary digital) video stream is possible, for example, via an external graphics / video (EGV) port, the EVG port of which is entitled " Programmable External Graphics / Video Port For Digital Video Decode System Chip & Which is incorporated herein by reference in its entirety. In summary, the EVG port consists of a programmable bidirectional port for a video decoder system with video decoder and internal digital display generator circuitry. The EVG port employs a predetermined number of signal input / output (I / O) pins for the video decode system, while an external graphics controller for the video decoder of the chip or the internal digital display generator circuit, an external digital display generator circuit, For a configuration of a multi-standard decoder, a number of connection configurations are provided. The EVG port includes a receiver / driver circuit that includes a pixel data signal and a corresponding synchronization signal, and receives a plurality of input / output signals in parallel.

Furthermore, the above-mentioned patent application entitled " MPEG Video Decoder With Integrated Scaling And Display Functions "is an example of generating decompressed video signals of reduced size for display on a conventional television system, . The downscaling of the decompressed video is discussed in the discussion that follows in connection with Figures 6-10. One embodiment of the OSD region processor is described in detail in the application entitled " Color Mapped And Direct Color OSD Region Processor With Support For 4: 2: 2 Profile Decode Function " (OSD overlaying of graphics) is a commonly available capability as will be discussed in more detail below. In one embodiment, the capabilities described in the applications referenced herein are incorporated to be employed in an integrated digital video decode system in accordance with the principles of the present invention. However, the gist of these applications is only reflected as an example. Other solutions will be apparent to those skilled in the art based on the description provided herein.

As is well known, the MPEG-2 standard describes a digital video encoding method in which bandwidth reduction is substantially caused by lossless compression after subjective lossy compression. The encoded digital data is then decompressed and decoded by the MPEG-2 decoder. As an example, video decoding according to the MPEG-2 standard is described in detail in commonly assigned U.S. Patent No. 5,576,665, entitled " Video Decoder "

As discussed in U.S. Patent No. 5,576,765, although the present invention has been described in connection with an MPEG-2 video decoder thereafter, rather than being limited to being used with an MPEG-2 decoder, enhanced graphics and / May be introduced into any integrated video processing system that desires to implement video processing.

As a background, Fig. 1 is a block diagram of a conventional video decoder. The compressed data is input as the signal 11 and stored in the compressed data memory 12. [ The variable length decoder (VLD) 14 reads the compressed data as a signal 13, transmits motion compensation information as a signal 16 to a motion compensation (MC) unit 17, inverse quantization (IQ) unit 18 as a signal 15. The motion compensation unit reads the reference data from the reference frame memory 20 as a signal 19 to form a predicted macroblock and sends it to the adder 25 as a signal 22. The inverse quantization unit calculates an inverse quantization coefficient and sends it as an inverse transform (IDCT) unit 23 as a signal 21. The inverse transform unit computes a reconstructed difference macroblock as the inverse of the dequantization coefficient. The reconstructed difference macroblock is sent as a signal 24 to an adder 25 and added to the predictive macroblock. The adder 25 calculates a reconstructed macroblock as a sum of a reconstructed difference macroblock and a predictive macroblock. The reconstructed macroblock is then sent as a signal 26 to a demultiplexer 27 which demultiplexes the macroblock as a signal 29 in the reference memory if the reconstructed macroblock is from a reference picture Otherwise, it is output as signal 28 (memory or display). The reference frame is sent out as a signal 30 from the reference frame memory.

A partial embodiment of a decode system chip 40 incorporating the concept of the present invention is shown in FIG. System 40 includes, for example, a PCI bus interface 44 that couples decode system 40 to PCI bus 42. The MPEG-encoded video data is fetched from the PCI bus 42 by the DMA controller 46 and written into the first-in / first-out (FIFO) buffer 48. The DMA controller also fetches on-screen display (OSD) and / or audio data from the PCI bus 42 and writes to the OSD / audio FIFO 50. The memory controller 52 will place the video data in the correct memory buffer in the DRAM 53. [ Next, the MPEG compressed video data is retrieved from the DRAM 53 by the video decoder 54 and decoded as described above in connection with Fig. Normally, the decoded video data is then stored back into the frame buffer of the DRAM 53 for later use. The data stored in the DRAM 53 is retrieved by the memory controller when the reference frame is required or when the video data is to be output from the decode system and sent to the digital video encoder / - analog converter chip 59 and is then sent for output. Also, the audio data retrieved by the video controller 52 is output through the audio interface 60.

As mentioned briefly above, the present invention deals with an aspect for providing a digital video decoding system with the ability to implement a co-screen feature. Another aspect of the present invention is to provide a method and system that can be used in a wireless communication system such as, for example, via an external graphics / video (EVG) port, as described in the above co-filed patent application entitled " Programmable External Graphics / Video Port For Digital Video Decode System Chip & There is provided a digital video decoding system capable of overlapping graphics with an analog video signal input to a digital video processing system. The present invention employs two features of the integrated digital video decode system described in the aforementioned applications, which are incorporated herein by reference. Specifically, the present invention relates to the ability to combine analog video channels and on-screen display (OSD) graphics, such as those described above, and the ability to downscale decompressed digital video for an area corresponding to a portion of the overall screen size It adopts. These features are described in greater detail below and are also described in detail in the applications referenced herein.

Figure 3 illustrates one embodiment of a display screen 70 of a television system for displaying images generated by an integrated digital video decode system in accordance with the principles of the present invention. As is well known, the screen 70 displays an image through a plurality of pixels 71 spread throughout the screen. Within the screen 70, the first image 72 is shown positioned within the larger image 74. Thus, Figure 3 is an example of a co-screen or multi-screen display.

Figure 4 illustrates one embodiment of a digital video decode system chip 100 that incorporates the principles of the present invention. The system 100 receives the digital video signal 101 from a first video source, such as, for example, a cable or satellite video signal source. The signal 101 is transmitted via a network interface module (NIM) 102 which outputs an MPEG transport stream to the transport logic 103 which is part of the integrated system 100 . Transmission logic 103 demultiplexes the transport stream and sends the compressed video stream to a video decoder 106 (see FIG. 2) within the integrated system. The video decoder generates an uncompressed MPEG video signal which is eventually sent to an internal digital video encoder (DENC) macro 107 for formatting for a television system (not shown). The digital-to-analog conversion of the video signal occurs prior to being output 110 to the television system.

According to the principles of the present invention, the downscaling capability of the video decoder 106 (described in more detail below with respect to Figures 6-10) is provided as a secondary window, e.g., window 72 of Figure 3 In order to reduce the size of the decompressed digital video to a very small image display size, in one embodiment. Other images forming a co-screen display may be displayed on an external graphics / video port as described in the above-referenced patent application entitled " Programmable External Graphics / Video Port For Digital Video Decode System Chip " And is retrieved as a compressed video signal. Alternatively, a dedicated port for inputting the uncompressed video signal to the integrated digital processing system, including a video decoder, may be configured by one skilled in the art. This uncompressed signal may be received from a second video source and may include another digital or analog signal.

For example, when an analog video signal 104 is received from a cable, satellite, VCR or tuner source, a digital multi-standard decoder (DMSD) 105 receives an analog signal 104 for input to the integrated digital video decode system 100, . The interfacing of the DMSD 105 to the video decoder and associated display and OSD logic is described in the application related to the EVG port described above. The DMSD 105 will provide a digital conversion of the analog video signal as well as (in one embodiment) a video decoder and a sync master for the internal DENC. The DMSD 105 provides a synchronization signal to the display / OSD unit of the video decoder and the internal DENC through, for example, 'CCIR-656 SAV / EVA code words' which are horizontal and vertical sync input ports . The above-mentioned Display / OSD unit and the internal DENC are responsible for interpreting synchronization information and processing the data correctly. The means for accomplishing this may be a standard operation employing, for example, sync slave signals.

Figure 5 illustrates one embodiment of modifying the video decoder / display and OSD logic 106 to include merge and combine capabilities in accordance with the present invention. In this embodiment, the 2: 1 multiplexer 202 controlled by the "pixel selection control" signal generated by the processor receives the decompressed digital video (i.e., (Or digital) signal received via the DMSD 105. In one embodiment, the "pixel selection control" selects one of the three The host processor has the pixel selection control that can (1) send the decompressed video onto the display, (2) send the uncompressed video on the display, and (3) Dynamically selects decompressed video and uncompressed video for display. In mode (3), switching between decompressed and uncompressed video for simultaneous display Auxiliary image based on the location of the (secondary picture) (72) (see Fig. 3) which is carried out at a predetermined speed.

In one embodiment, the decompressed digital video is downscaled to form a window within a large image of uncompressed video. Accordingly, the "pixel selection control" signal indicates from the leftmost position on the upper part of the display screen whether the pixel information of the decompressed video will be adopted or the uncompressed video will be adopted when the raster scanning line progresses from left to right , And these instructions are made from the top to the bottom of the display screen. In this regard, it should be noted that the position selection and size of the embedded image can be easily modified by those skilled in the art without departing from the spirit of the present invention. The final video output from the 2: 1 multiplexer 202 is provided as the primary input of the OSD combinatorial logic 204 of the integrated digital video decode system chip 100 (see FIG. 4). The OSD graphics to be combined with the final video are also input to the logic 204, the output of which is the desired co-screen with graphics. The function of the OSD combination logic 204 is the same as that already known when simply superimposing the OSD graphics on decompressed digital video.

The OSD combination function provides a weighted average of pixel luma and chroma values between video and OSD graphics sources. This average is based on a weighting factor a ranging between 0 and 1. This average is calculated as follows.

(Video x a) + (OSD x (1-a))

Also, most OSD graphics areas are implemented as one or more areas (spheres), wherein the coefficients a are individually selectable for each area (i.e., the combination need not be constant for the entire OSD). The decompressed digital video and OSD combination function to be used is available in the industry, for example, as a product such as "MPEG 2CS Digital Audio / Video Decoder"

In summary, the aforementioned EVG port patent application, which is incorporated herein by reference, describes an integrated digital video decoding system capable of generating an uncompressed video stream and synchronizing the output video / audio presentation to this stream. The present disclosure also relates to mixing and / or combining graphics in an output video stream consisting of an uncompressed video stream or a merged co-screen video stream comprising decompressed digital and uncompressed video It is possible. The combined stream is output to an internal digital video encoder macro (DENC macro) for encoding into television format. Thus, uncompressed (e.g., analog) channels are provided with the same graphical characteristics, functionality, and programming model capabilities as existing digital channels utilizing an integrated digital decode system. Typical uncompressed analog video sources include video cassette recorders (VCRs), camcorders, television cameras, laser discs, digital video disc players, computers with TV outputs, cable television analogue channels, satellite analogue channels, to be. Some of these sources can provide composite television or S-video signals to a digital multi-standard decoder (DMSD) chip, which in turn transmits digitized video to an integrated decode system for video signal combination and graphics mixing.

As mentioned briefly above, the present preferred embodiment also introduces downscaling of decoded digital video to provide a stream of picture-in-picture video for display on a conventional non-co- ) Is generated. The downscaling of the decompressed digital video is described in the above-mentioned patent applications, which are hereby incorporated by reference in its entirety, to freely expand the area of the television display surface for graphics information that the viewer is instantly more interested in at the time of viewing have. The graphics information may be Internet information, programming guide information, or arbitrary adjustments to audio or video provisioning. The downscaled video can be placed at various locations on the screen.

Since the mixing / combining of the uncompressed video described herein is performed as a final step of video processing (see FIG. 2), all of the logic necessary to provide video decompression and on-screen display can be decompressed, Continue downscaling freely. Mixing / combining has been proposed here as being performed between OSD graphics and uncompressed digital video (or uncompressed analog video). By controlling the video source selection to dynamically switch between decompressed digital video and uncompressed video sources for the reduced screen, the uncompressed video for the entire screen is presented in the background, and the reduced digital video is displayed in the foreground ). The location of the foreground video can be moved under software and user control so that the reduced image does not cover the main section of the video image stream for the entire screen. OSD graphics can be combined with both images to cover the entire viewing area. If desired, it is also possible to draw a border around the reduced foreground image using OSD graphics.

As discussed initially herein, the present invention includes a decoding system with integrated scaling capabilities that can scale the size of an MPEG-2 video offering to a predefined reduction rate. Because the market for MPEG-2 video decoders is becoming increasingly competitive, high performance integration at the lowest possible price is required to succeed in the market. In view of this need, the present invention provides a scaling mode that reduces the size of the display image by, for example, 2 and / or 4 predefined coefficients on the horizontal and vertical axes.

Figure 6 illustrates one embodiment of a video decoding system in accordance with the principles of the present invention. The video decode system includes an external memory 653, which in the illustrated embodiment is a SDRAM frame buffer memory. The memory 653 is connected to the memory control unit 652. The memory control unit 652 receives the decoded video data from the video decoder 654 and provides the video data via the video display unit 690 for display. In accordance with the principles of the present invention, a video decoding system includes many features that implement video scaling mode capabilities.

For example, a decimation unit 682 is modified to include both a normal video decimation mode and a video scaling mode. The frame buffer 653 can store the decoded video data in a full-frame format or can be stored so as to be stored in a combination of a full frame format and a scaled video format. The display mode switch logic 696 is provided within the video display unit 690 to facilitate smooth switching between the regular video mode and the scaled video mode. Frame buffer pointer control 686 is modified to provide the correct frame buffer pointer based on the new partitioning of the frame buffer when in normal video mode and in the scaled video mode.

In operation, the MPEG input video source is supplied to the input of the video decoder 654 via the memory control unit 652 as coded MPEG-2 video data. The decoder 654 includes a Huffman decoder 672, an inverse quantizer 674, an inverse DCT 676, a motion compensator 678 and an adder 680, Which is the same as that described in connection with the video decoder. The internal processor 670 supervises the video decoding process in accordance with the principles of the present invention and receives a signal from the host system whenever the host wishes to switch the video display, for example between a regular video display and a scaled video display. This signal is indicated as "host control format change" in Fig. In response to the host format change, upsample logic 694 from internal processor 670 to Huffman decoder 672, inverse quantizer 674, motion compensator 678, and video display 690, The display fetch unit 692, and the display mode switch logic 696, as shown in FIG. Again, these control signals are sent to a video decoding system in accordance with the principles of the present invention to switch the display output, for example between regular video mode and scaled video mode (as described below).

Size macroblocks of the decoded video data are sequentially output from the video decoder 654 to the decimation unit 682 where the full size macroblocks in one embodiment are one of two types of compression Experience. First, if full-size video is required, only decimation of B-coded pictures is preferably performed. In this regular video mode, decimation is a process of reducing the amount of data by interpolating or averaging the combined values to obtain the interpolated pixel value. Interpolation reduces the number of pixels, thus requiring less external memory for the entire system. In the second mode, the decimation unit 682 performs picture scaling in accordance with the principles of the present invention. For example, this type of scaling employed may reduce the overall size of the display image by a factor of two or four on the horizontal and vertical axes.

In addition to providing a stream of decoded full size macroblocks to decimation unit 682, the video decoder sends a "motion compensation unit block complete" signal to output line 683, Unit 682 will know when the macroblock has been fully decoded. Similarly, the decimation unit 682 provides a "decimator busy" signal to the motion compensation unit 678 of the video decoder 654 via the output line 681. This "decimator in operation" signal notifies the motion compensation unit when the decimation unit is in operation and when the operation is completed, after which the motion compensation unit can proceed to the next macroblock.

The motion compensation unit 678 of the video decoder 654 provides straight read video addresses to the memory control unit 652 and decoded video data for the external memory 653 (full size) and / Or write viedo addresses to the decimation unit 682 for the writing of the scaled macroblocks. Along with the read video address and write video address, the memory control unit is provided with pointers by a frame buffer pointer control 686. These pointers define which frame buffer area within SDRAM 653 is to be accessed by a given read video address or write video address in accordance with the division of the frame buffer memory space in accordance with the present invention do. This pointer is represented by a current pointer and a current small pointer in FIG. 6, where the current pointer is a pointer for a full size macro block, and the current small pointer is a pointer for a scaled macro block.

Decimation unit 682 receives the decoded full size macroblock, internally stores the information, and, once the scaling mode is activated, performs scaling as described below. In normal mode, the decimation unit 682 outputs the decoded video data full size macro block to the memory control unit 652 for storage in the frame buffer 653. In the scaling mode, the decimation unit 682 scales the full-size macroblock, and outputs the scaled macroblock to the memory control unit 652 for storage in the frame buffer 653.

The frame buffer pointer control 686 is important and controls the rotation of the frame buffer, i.e., the frame buffer assignments, in the regular video mode and the video scaling mode according to the principles of the present invention box).

The decimation unit 682 functions as part of the video display unit 690 when retrieving data for display, as described in the aforementioned applications referenced herein. More specifically, the decoded video data, which consists of full-size scan lines, is retrieved from the frame buffer storage 653 to provide a B-frame re-expansion of pictures And is supplied through the decode unit 682. This is done so as to maintain consistency for the video in the group of pictures, and thus the reduced resolution of any one picture can not be perceived. After re-stretching, a full-size scan line is provided to the display output interface 698.

Alternatively, in the video scaling mode, the decoded video consisting of scaled scan lines is retrieved from the frame buffer storage 653 and provided directly to the scan line video buffer 684. The scan line is divided into luminance and color data and the current scan line and the previous scan line are supplied from the scan line video buffer 684 to the vertical and horizontal up sample logic 694. [ Up sample control is received from the display fetch unit 692, which adjusts letterbox formatting, SIF upsampling, 4: 2: 0 vs. 4: 2: 2 upsampling and flicker reduction.

The display fetch unit 692 provides a readout video address for retrieval of the scan lines from the frame buffer storage 653. The "current pointer, current small pointer" sync signal for display is received by the memory control unit 652 from the display mode switch logic 696 of the video display unit 690. As described above, the current pointer, the current small pointer, signals the point for the particular frame buffer area in which the scan line will be searched, while the read video address signal indicates the particular scan line to be searched in the frame buffer area.

The display mode switch logic 696 is provided in accordance with the principles of the present invention, for example, to ensure smooth switching between a scaled video mode and a regular video mode. Logic 696 receives a control signal as input from an internal processor 670 of video decoder 654 and a vertical sync (VSYNC) signal (from display output interface 698) Also receives a B picture "MPEG-2 Repeated Field" signal from the Huffman decoder 672. [ VSYNC is an external synchronization signal indicating the start of a new display field. In addition to the current pointer, the current small pointer synchronization for display, the output of the display mode switch logic 696 is also a "display format sync for display" signal supplied to the display fetch unit 692, and also to the decimation unit 682, Is also a "display format sync for decode" signal supplied to the decode logic of the decoder. The display mode switch logic 696 also outputs a "block video" signal to the display output interface 698, which suppresses noise in the display when switching between display modes in accordance with the principles of the present invention. To block one display frame. Video data is received from the upsample logic 694 at the display output interface. The decimation unit, frame buffer division, frame buffer pointer control, and display mode switch logic implemented in accordance with the principles of the present invention are described in further detail below with reference to Figures 6A-10.

First, let's look at the frame buffer. The frame buffer is used for storing the image configured for display and for predicting a subsequent image. Since the B picture is not used for prediction, the frame buffer is available after the picture is displayed. In the case of an I or P picture, in particular, the frame buffer needs to be maintained after the display to predict the B picture.

6A illustrates frame buffer 700 allocation for both regular video mode and scaled video mode in accordance with the principles of the present invention. In normal mode, there are three frame buffers to support decoding and display processing. Frame buffer 0 and frame buffer 1 are allocated for I and P pictures, while frame buffer 2 is allocated for B pictures. The frame buffers are tagged with a buffer pointer, i.e., the current pointer from the frame buffer pointer control 686 of FIG.

In the scaled video mode, at least five frame buffers are employed. Frame buffer 0 and frame buffer 1 also accept full size I and P picture video. At least three different buffers (represented by Frame Buffer 2, Frame Buffer 4, Frame Buffer 6 in the illustrated embodiment) are tagged with small pointers generated by frame buffer pointer control. These small buffers are mainly used for display purposes in scale video mode. The buffers are small in size to be suitable for video scaling. When decoding an I or P picture, the composed picture is stored in buffer 0 or buffer 1 depending on which is available. At the same time, downscaling of the same image is stored in one of the smaller buffers, that is, the frame buffer 2, the frame buffer 4, or the frame buffer 6. Next, full size video is used for prediction, while small size video of a small frame buffer is used for display of downscaled images.

The frame buffer is configured by microcode during the initialization of the video decoding system. A memory base address is assigned to each frame buffer, and this memory base address is selected by a buffer pointer generated by frame buffer pointer control. The read and write video addresses refer to specific addresses in the selected frame buffer. Unless otherwise indicated, the present application then uses the term "frame buffer" as including all frame buffer memories configured during initialization. The "frame buffer area" refers to one of the specific frame buffers shown in FIG. 6A.

Since the video display operates in real time, the frame buffer pointer has to be switched in accordance with the VSYNC timing. Since the decoding always precedes the display, the frame buffer must be made available for storing the decoded picture. Therefore, the frame buffer pointer must be switched after the start of decoding. To avoid disturbance to the display frame buffer, a copy of the display buffer pointer is retained. The buffer switching time is the start time of each image decode. The display buffer pointer also changes at that time, but will not be used until the display pointer time, which is the start time of the picture display, is copied. One embodiment of normal mode buffer pointer rotation is described below.

The following assumes four buffer pointers, each containing two bits to indicate which of the three frame buffers is being accessed.

Current pointer - indicates the frame buffer to be used in relation to the image being constructed,

Display pointer - indicates the frame buffer to be used for display,

Future pointer - Indicates the frame buffer to be used for backward prediction,

Past pointer - Indicates the frame buffer to be used for forward prediction.

At startup, the future pointer is initialized to "1" and the other pointers are set to "0". At the start of the I or P picture decode, the value from the past pointer is loaded into the current pointer, and the value of the future pointer is loaded into the display pointer. The values of the future pointer and the old pointer are exchanged. If the decoded picture is a B picture, the current pointer and the display pointer are set to "2 ". The frame buffer 2 is reserved for a B picture as an embodiment. Future pointers and past pointers remain unchanged. Pointer switching in normal mode is described in greater detail in U.S. Patent No. 5,668,599 to Cheney et al. Entitled " Memory Management For An MPEG-2 Compliant Decoder " . ≪ / RTI >

In the scaled video mode, the display time of the image is delayed by the field time added in accordance with the present invention. The purpose of this delay is to separate the decode process and the display process so that the decoded scaled video can be located anywhere on the screen. Figure 7A shows an example of delayed display timings in a scaled video mode. This display timing is dynamically adjusted according to the mode, that is, the regular mode or the scaled video mode. One field time delay is needed in accordance with the present invention to properly manage the buffer. At least five buffers are again assumed to be in video scaling mode. As described above, two of these five buffers are full-size frame buffers, denoted Frame Buffer 0 and Frame Buffer 1 in FIG. 6A. This full size frame buffer is identical to the corresponding buffer used in normal video mode. At least three small frame buffers, i.e., the frame buffer 2, the frame buffer 4, and the frame buffer 6 are allocated to the same memory space occupied by the frame buffer 2. These three small frame buffers are controlled by other algorithms than those described above.

Specifically, four additional pointers are used in the scaled video mode. These pointers are as follows.

Small current pointer - points to a small buffer for images in decimated configuration,

Small display pointer - indicates a small buffer for display,

Small Future Pointer - Indicates a small buffer for future display,

• Small transition pointer - indicates a small buffer for transitions.

When the decoder is initialized, the small current pointer, small display pointer, small future pointer, and small transition pointer are set to 0, 2, 4, and 6, respectively. At the start of each picture decoding, the small current pointer is loaded from the small transition pointer, and the small transition pointer is loaded from the small display pointer. If the decoded picture is a B picture, the small display pointer is loaded from the small transition pointer, and the small future pointer remains unchanged. If the decoded picture is an I or P picture, the small display pointer is loaded from the small future pointer, and the small future pointer is loaded from the small transition pointer. One example of a small frame buffer switching in accordance with the present invention is shown in FIG.

The full-size frame buffer, frame buffer 0, and frame buffer 1 switch as if the decoder is running in normal mode. These two buffers are needed for prediction, but not for display in scale video mode. When an I or P picture is being decoded, the picture is stored in both buffers indicated by the current (full frame) pointer and the small current pointer. During decoding of the B picture, the frame buffer 2 indicated by the current (full frame) pointer will not be used. Only the small frame buffer indicated by the small current pointer is used for the decimated image. In normal mode, a display pointer is used for display, while in a scale video mode, a small display pointer is used. Two switching algorithms operate simultaneously at the beginning of each picture decoding. The buffer pointer is simply selected depending on what mode the decoder is in.

Next, FIG. 8 illustrates one embodiment of a decimation unit 682 (see FIG. 6) employed in accordance with the present invention.

In the decode decimation unit previously implemented, for example, the decimation unit is limited to operating only for the B picture for the character box or memory reduction. However, in the scaled video mode presented here, the decode decimation unit processes all kinds of images. This is desirable in order to save memory bandwidth at the time of display, because (in one embodiment) the scaled image and the multi-plane high resolution OSD graphics may be mixed at the output.

8, the decimation unit includes decimation logic 800 that receives decoded video data from a video decoder and outputs the decimated data flow to a decimation buffer < RTI ID = 0.0 > 820). The output from the decimation buffer 820 is multiplexed 830 with undecimated decoded video data received from the video decoder and the multiplexer 830 decodes the decoded video data as well as the decoded video data, And outputs a scaled macroblock to be stored in the frame buffers 0, 1, 2, 4, The write video address from the motion compensation unit of the video decoder is supplied to the memory write control 840 in the decimation unit and this memory write control controls the writing of data from the decimation buffer 820. [ Irrespective of whether decimation scaling is applied or not, the write video address is output to the memory control unit via the multiplexer 850 (see FIG. 6).

The multiplexers 830 and 850 are controlled by a decimate control signal. The decimate control logic accepts a signal called "MCU_block_complete" as input from the motion compensation unit of the video decoder. This signal indicates the time at which the decimator can begin writing the scaled macroblock. The decimator notifies the motion compensation unit that the decimator is currently operating with the "decimator_busy" signal.

In the case of a given macroblock, there are two phases. One aspect relates to luminance and the other relates to chrominance. Each view requires the writing of a full size macroblock and a single scaled macroblock under the assumption of a scaled video mode.

We will make various specific changes to the decimation hardware / process previously described. One change in the data flow of the decimation process is the addition of 4 to 1 horizontal reduction, which is implemented with the decimation function of the decimation logic. This supports 1/16 size scaling.

Another change is to increase the size of the decimation buffer to 32 x 32 bits. When the I and P pictures are processed, the full size macro block is written to the memory while the decimator simultaneously scrambles the macroblock and stores the small macroblock in the decimation buffer 820. After the full size macroblock is written to memory, the decimator writes the scaled macroblock to another buffer location in memory (e.g., frame buffer 2, frame buffer 4, or frame buffer 6 in the example described above). Larger decimation buffers allow the storage of small matrox blocks.

In addition, the decimate state machine logic is modified to allow for two modes of operation, assuming a scaled video mode. The first mode is the B image processing, and the second mode is the reference image processing. In the case of B image processing, only small macroblocks are written into the memory through the decimation buffer 820. [ Since the decimation buffer may have a completely scaled macroblock, the data is transmitted through the decimation unit in accordance with the rate at which the motion compensation unit is transmitting. For a reference picture operation, the full size macroblock is first written to the memory via the multiplexer 830, and then the scaled macroblock is written. This requires that the speed of the data flow be adjusted by the memory control unit in accordance with the write request.

Since the size of the compressed image of the source is variable, there is an exception to the process described above. A decimator is required when some sort of reduction is needed to form a scaled image. Some video sources are already small in size, so one or both dimensions may not require scaling. For example, it is common to have an image of 352 x 240 size (which is a typical MPEG-1 size). In this case, it would be unnecessary to perform decimation to provide 1/4 scaling. In the case of a reference frame, since the display process is performed only for the display frame buffer during scaling, it is necessary for the motion compensation unit to write the full size macro block to the reference frame buffer of the memory, and then write it to the display frame buffer.

If the same image size is reduced to 1/16 scaling, a decimation step is required. Likewise, there are exceptions in this case as well.

One of the purposes of scaling is to eliminate interlacing artifacts. In the real MPEG-1 video, there is no interpolation because the picture is frame-encoded exclusively. MPEG-2 allows an interpolated image of the same resolution (352 × 240), and the decimator only uses the top field picture to generate the scaled macroblock. The bottom field is discarded. Therefore, in the case of a reference picture, the MCU needs to write a macroblock for the top field picture into both the reference frame buffer and the display buffer. In the case of a B picture, the MCU only needs to write the topmost field picture to the display frame buffer.

The video decoding system according to the present invention provides a smooth transition when entering or exiting a small image mode. In video scaling mode, frame buffer 2 is used for capture and display of small image images (including reference image and B picture), so care must be taken to avoid interference between the decoding and display processes at the display format switching time. Should be. There is also a latency adjustment of one field time that necessarily occurs during the transition. The regular display mode has a 1.5 frame waiting time between the decoding and display of the reference picture and a 0.5 frame waiting time in the case of the B picture. In the small image mode, the reference frame waiting time is changed to two frames, and the B frame waiting time is changed to one frame.

In order for the display format change to occur smoothly, the display should not be in the process of displaying the B picture when a transition occurs, and if so, the picture will appear disturbed. Therefore, the transition must occur when the reference image is displayed. This is forcefully generated by the microcode during the sequence header when the first frame of the new sequence is the reference frame and the display is being executed for the last frame of the previous sequence.

During transitions to / from the small picture mode, the hardware must adjust the wait time without disturbing the decode or display process. Frame synchronization shall be adjusted for the new mode. Furthermore, the field parity must be maintained. As a result of making adjustments in the small image mode, a delay of one frame time is introduced, which may affect the PTS comparison. After this, it may be necessary to skip the frame to fill the time difference. This occurs only when entering the small image mode. When exiting the small image mode, there is no loss in synchronization. Transitions occur at the point where images are skipped or repeated.

Referring to Fig. 9, the display format change signal is written asynchronously by the host. The format is received as a control signal in the display format register 910 and the microcode waits until the sequence header is processed before writing the information to the display format resister 910. [ This information is then sent to the register stages 930, 940 and 960 as well as to the synchronization generator 900. Resist step 1 930 gathers information at the next frame sync. The decoding process uses the step 1 register 930, and the display process uses the step 3 register 960.

The field counter 920 simply counts backward from the starting field number of the frame to 1 and repeats this. The counter 920 is loaded with a control signal by the synchronization generator 900 as shown. The synchronization generator 900 also receives the VSYNC signal and the output of the step 1 register 930. The sync generator 900 produces three signals: a "frame sync" signal, a "new picture" signal, and a "block video" signal. The "frame sync" signal indicates when to start decoding the new frame to the decode process. The "new picture" signal indicates when to start displaying a new frame to the display process. The "intercept video" signal is used to selectively suppress the video image of one frame while the video decode system transitions from the normal frame to the scaled frame. The frame sync and the new image signal are pulses that are generated once every two field times. In normal mode, the signals are 180 degrees out of phase, but in scaling mode (according to the invention) the signals are in phase. This is described in detail later with respect to the flowchart of Fig.

In all cases where a switch to a scaled picture mode is involved, there is a repeated frame where viewing on the display is blocked. Blocking is necessary because the collision between the current reference frame and the currently displayed reference frame must be buffered. When the video is interrupted, the output of the decoder can be forced to a black background color.

The wait time adjustment is performed as soon as the phase 1 register changes. By absence of frame synchronization, the current display frame can be repeated. Next, the synchronization generator adjusts the waiting time by adjusting the frame synchronization with the new image. During repeated reference frames, the video is interrupted for one frame time.

10 is a flow diagram of one embodiment of the processing implemented by the synchronization generator 900 (see FIG. 9).

In an initial step 1000, a VSYNC signal 1010 indicating the start of a new field is awaited. Upon receiving the VSYNC signal, it generates a "new picture" sync signal and queries 1030 whether this field is repeated based on the received MPEG-2 syntax. The value of the initial field counter FC depends on whether the field is repeated or not. If a 3: 2 pulldown is employed, the initial value of the field counter is 3 (1040); otherwise, a normal interlace is preferred and a field counter is loaded with a value of 2.

Once the field counter is set, it queries whether scaling is to be implemented (1050, 1070), respectively. If not implemented, the decode system is either non-scaling or normal mode. In this case, after waiting for the next VSYNC signal (1080), it inquires whether the field counter is 2 (1090). If not (e.g., because a value of 3 is loaded in the field counter), the field counter is decremented 1110 and processing waits for the next VSYNC signal 1080. Once the field counter is 2, a "frame sync" signal is generated 1100, after which the field counter is decremented 1110 and processing then determines 1120 that the value of the field counter is 1. If the value is 1, a new video signal is generated 1120 after waiting 1010 a new VSYNC.

Assuming that a scaling mode is desired, processing proceeds from query 1050 or 1070 to the next VSYNC wait 1130, after which a determination is made whether the field counter is 1 (1140). If not, the field counter is decremented and processing returns (1130) to wait for the next VSYNC. If the value of the field counter is 1, a new image synchronization signal is generated (1150). Thereafter, a value of 2 is loaded into the field counter and a blocking video signal is generated (1160). Again, the intercepting video signal is output from the sync generator to the display output interface (see FIG. 6) for interception of the next frame of video.

After sending the intercepting video signal, the process enters a steady state and the video scaling subprocess is started by waiting for the next VSYNC signal, after which processing determines whether the field counter is one (1190). If not, the field counter is queried (1240), and if not, the field counter is decremented (1260) and returned (1180) to wait for the next VSYNC signal. Otherwise, a determination is made whether the scaling command is turned off by the host system (1250). If not, the field counter is decremented and waits for the next VSYNC signal (1180). If the scaling mode is switched off, the field counter is decremented in the directive 1110 in the non-scaling process described above.

If the field counter is 1 in query 1190, a "new picture" signal and a "frame sync" Again, in order to implement scaling, in the case of a reference picture, it is necessary to change the waiting time between the decoding process and the display process from 1.5 frame time to 2 frame time to make the new image signal and the frame synchronizing signal into the same phase. Next, an MPEG-2 repeat field is set to determine whether to load a value of 2 (1230) or a value of 3 (1220) to the field counter depending on whether regular interlacing is desired or a 3: 2 pull down is desired (1210). This is necessary even if latency adjustments are made to accommodate all types of frame rate conversions. After setting the field counter, the process returns (1180) to wait for the next VSYNC signal.

The invention may be included, for example, in an article of manufacture (e.g., one or more computer program products) having a computer usable medium. The medium is embedded in, for example, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture may be included as part of a computer system, or may be sold alone.

Also, in order to perform the capabilities of the present invention, at least one program storage device that realizes at least one program that is machine readable and that is executable by machine-executable instructions may be provided.

The flow charts shown herein are for illustrative purposes only. The flowcharts or steps (or operations) described herein can be modified without departing from the spirit of the invention. As an example, in some cases, the steps may be executed in a different order, or the steps may be added, deleted or changed. All such modifications are considered to be part of the invention as set forth in the appended claims.

Although the present invention has been described in detail in accordance with certain preferred embodiments thereof, many modifications and changes may be made by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and variations as fall within the true spirit and scope of the invention.

Thus, according to the present invention, a simultaneous display feature can be added to an integrated digital video system, such as a digital video decode set-top box or a digital video disk player, for example, while minimizing the additional production cost, A television system can be provided.

Claims (20)

A method of forming a multi-screen display for a non-picture-in-picture television system, Receiving and decoding a compressed digital video signal to generate a decompressed digital video signal; Receiving an uncompressed video signal; And merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system, The non-co-screen television system is capable of simultaneously displaying multiple images A method for forming a multiple screen display for an asynchronous screen television system. The method according to claim 1, Further comprising downscaling the decompressed digital video signal prior to merging the decompressed digital video signal and the decompressed video signal, Wherein the downscaled decompressed digital video signal comprises at least one of the multiple screen displays A method for forming a multiple screen display for an asynchronous screen television system. The method according to claim 1, The merging step Switching between the uncompressed digital video signal and the uncompressed analog video signal to generate at least some video frames for display by the television system, Generating A method for forming a multiple screen display for an asynchronous screen television system. The method according to claim 1, Further comprising blending at least one of the decompressed digital video signal and the uncompressed video signal with on-screen display (OSD) graphics, Wherein the multi-screen display comprises a decompressed digital video signal and the uncompressed video signal. A method for forming a multiple screen display for an asynchronous screen television system. The method according to claim 1, Further comprising implementing the method within at least one of a digital video set-top box (STB) or a digital video disc player A method for forming a multiple screen display for an asynchronous screen television system. The method according to claim 1, Wherein the compressed digital video signal is received from a first video source and the uncompressed video signal is received from a second video source A method for forming a multiple screen display for an asynchronous screen television system. A method of processing an analog video signal, Digitizing the analog video signal for input to a digital video processing system, And combining the digitized video signal with on-screen display (OSD) graphics within the digital video processing system A method for processing an analog video signal. 8. The method of claim 7, Wherein the digitizing step is performed within a digital multi-standard decoder, and wherein the digital video processing system includes an integrated digital video decode system A method for processing an analog video signal. 9. The method of claim 8, Further comprising formatting said OSD graphics and said blended digitized video signal for display by an analog television system A method for processing an analog video signal. 8. The method of claim 7, Implementing the method within at least one of a digital video set top box (STB) or a digital video disc player; Further comprising formatting said combined digitized video signal and OSD graphics for display by an analog television system A method for processing an analog video signal. A system for forming a multi-screen display for an asynchronous screen television system, A video decoder for decoding a compressed digital video signal from a first video source to generate a decompressed digital video signal; An input of the video decoder receiving an uncompressed video signal from a second video source, The video decoder being adapted to merge the uncompressed video signal with the decompressed digital video signal to generate a multi-screen display signal for the television system, The non-co-screen television system is capable of simultaneously displaying multiple images Multi - screen display forming system for non - co - screen television system. 12. The method of claim 11, Wherein the video decoder is adapted to downscale the decompressed digital video signal before merging the decompressed digital video signal and the decompressed video signal, Wherein said downscaled decompressed digital signal comprises at least one screen of said multi- Multi - screen display forming system for non - co - screen television system. 13. The method of claim 12, Wherein the uncompressed video signal comprises an uncompressed analog video signal, Wherein the system comprises: Further comprising a digital multi-standard decoder for digitizing the uncompressed analog video signal before inputting the uncompressed analog video signal to the video decoder Multi - screen display forming system for non - co - screen television system. 12. The method of claim 11, Wherein the video decoder is further adapted to generate at least some video frames in a picture-in-picture format for display by the television system, Lt; RTI ID = 0.0 > Multi - screen display forming system for non - co - screen television system. A system for forming a multi-screen display for an asynchronous screen television system, Means for receiving and decoding a compressed digital video signal to generate a decompressed digital video signal, Means for receiving an uncompressed video signal, By including means for merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system, The non-co-screen television system is capable of simultaneously displaying multiple images Multi - screen display forming system for non - co - screen television system. A system for processing an analog video signal, ㉠ Digital video processing system, A digital multi-standard decoder for digitizing the analog video signal for input to the digital video processing system, The digital video processing system being adapted to combine the digitized video signal and on-screen display (OSD) graphics to output a combined video signal Analog video signal processing system. 17. The method of claim 16, Wherein the digital video processing system comprises a video decoder, Wherein the video decoder is adapted to perform the combination of the digitized video signal and the OSD graphics Analog video signal processing system. A system for processing an analog video signal, Means for digitizing the analog video signal for input to a digital video processing system, Means for blending said digitized video signal and on-screen display (OSD) graphics within said digital video processing system Analog video signal processing system. In the article of manufacture, A computer program product comprising a computer usable medium having computer-readable program code means therein for forming a multi-screen display for a non-simultaneous screen television system, Wherein the computer readable program code means of the computer program product Computer readable program code means for causing a computer to perform decoding of a compressed digital video signal to generate a decompressed digital video signal; (2) computer readable program code means for causing a computer to receive an uncompressed video signal, (3) computer readable program code means for causing a computer to merge the decompressed digital video signal and the uncompressed video signal to generate a multi-screen display signal for the television system Products. In the article of manufacture, A computer program product comprising a computer usable medium having therein computer readable program code means for processing analog video signals, Wherein the computer readable program code means of the computer program product Computer readable program code means for causing a computer to digitize the analog video signal, (Ii) a computer readable program code means for causing the computer to combine the digitized video signal and on-screen display (OSD) graphics for presentation to a television system Products.