KR20010005282A - Median filter upsampler - Google Patents
Median filter upsampler Download PDFInfo
- Publication number
- KR20010005282A KR20010005282A KR1019990026091A KR19990026091A KR20010005282A KR 20010005282 A KR20010005282 A KR 20010005282A KR 1019990026091 A KR1019990026091 A KR 1019990026091A KR 19990026091 A KR19990026091 A KR 19990026091A KR 20010005282 A KR20010005282 A KR 20010005282A
- Authority
- KR
- South Korea
- Prior art keywords
- upsampler
- vertical
- memory
- median filter
- line
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
Abstract
Description
본 발명은 인터레이스(interlace)를 프로그레시브(progressive)로 변환시키거나 필드더블(field Double)하는데 있어서, 간단히 프레임(frame)메모리와 메디안 필터(median filter)를 이용하여 업샘플링하도록 하는 메디안 필터를 이용한 업샘플러에 관한 것이다.According to the present invention, an intermediate media filter is used to convert an interlace into progressive or field double, and to simply upsample using a frame memory and a median filter. It is about a sampler.
기존에는 업샘플러(upsampler)를 구현하는데 있어서 도 1 과 같이 라인메모리(1)를 이용하여 라인 더블로 프로그레시브를 하거나 프레임메모리(3)와 모션 디텍션(4)을 이용하여 복잡한 프로그레시브나 필드더블을 수행하였다.Conventionally, in order to implement an upsampler, as shown in FIG. 1, a line double is progressive using line memory 1 or a complex progressive or field double is performed using frame memory 3 and motion detection 4. It was.
그러나 상기된 종래기술은 복잡한 알고리즘이 구현되어져야 하므로 화질에 열화가 발생되는 문제점과 복잡한 알고리즘때문에 실제품에 적용하기에 어려움이 따르는 것이었다.However, the above-described prior art has a difficulty in applying to a real product because of a problem that deterioration in image quality and a complicated algorithm have to be implemented a complex algorithm.
본 발명은 50/60HZ(PAL/NTSC)인터레이스를 프로그레시브로 바꾸거나 100/120HZ 인터레이스로 바꾸는 업샘플러를 구현하는데 있어서 프레임메모리와 메디안 필터를 이용하여 모션 디텍션 업샘플러와 같은 효과를 내면서도 하드웨어 구성간 간단하도록 한 것이다.The present invention implements an upsampler that converts a 50 / 60HZ (PAL / NTSC) interlace into a progressive or 100 / 120HZ interlace. To keep it simple.
이러한 본 발명은 메모리를 이용하여 입력데이타를 저장하고 수직윤곽 보정을 한 후 n개의 라인을 선택하여 메디안 필터를 통과시키고, 프레임 메모리를 이용하여 데이타를 지연시킨 후 n개의 라인메모리를 이용하여 수평윤곽 보정하고 n개의 라인메모리와 멀티플렉서를 이용하여 메디안 필터를 위한 라인을 선택한 후 비교기를 이용하여 중간값을 뽑아내고 수평윤곽 보정을 하도록 하므로써 이루어 진다.The present invention stores the input data using the memory and corrects the vertical contour, and then selects n lines to pass through the median filter, delays the data using the frame memory, and then uses the horizontal contour using the n line memories. This is done by calibrating, selecting lines for the median filter using n line memories and multiplexers, and then extracting the median using a comparator and performing horizontal contour correction.
도 1 은 종래 회로도1 is a conventional circuit diagram
도 2 는 본 발명의 회로도2 is a circuit diagram of the present invention;
도 3 은 본 발명 업샘플러 회로도3 is a schematic diagram of the present invention upsampler.
도 4 는 본 발명의 100HZ 인터레이스에서의 설명도4 is an explanatory diagram in a 100HZ interlace of the invention
도 5 는 본 발명의 50HZ 프로그레시브에서의 설명도5 is an explanatory diagram in 50HZ progressive of the present invention;
[도면의 주요부분에 대한 부호의 설명][Explanation of symbols on the main parts of the drawings]
1 : 라인메모리 3 : 프레임메모리1: line memory 3: frame memory
4 : 모션 디텍션 11,12 : 필드메모리4: Motion detection 11,12: Field memory
13,14,15,16,19,20 : 라인메모리13,14,15,16,19,20: line memory
17.18 : 버티칼피킹 21 : 수평피킹17.18: Vertical picking 21: Horizontal picking
30 : 업샘플러30: upsampler
도 2 는 본 발명의 회로도로써2 is a circuit diagram of the present invention;
입력데이타는 필드메모리(11)를 거쳐 라인메모리(15)와 버티칼 피킹(18)에 인가되는 한편 필드메모리(12)를 거친 후 라인메모리(13)와 버티칼 피킹(17)에 인가된다.The input data is applied to the line memory 15 and the vertical peaking 18 via the field memory 11, and to the line memory 13 and the vertical peaking 17 after passing through the field memory 12.
라인메모리(13)(15)의 출력은 버티칼 피킹(17)(18)에 인가되는 한편 라인메모리(14)(16)를 거친후 버티칼 피킹(17)(18)에 인가된다.The outputs of the line memories 13 and 15 are applied to the vertical pickings 17 and 18 while passing through the line memories 14 and 16 and then to the vertical pickings 17 and 18.
버티칼 피킹(17)(18)의 출력은 업샘플러(30)에 인가되는 한편 라인메모리(19)(20)를 거친후 업샘플러(30)에 인가되며 업샘플러(30)의 출력은 수평 피킹(21)을 거치도록 구성한다.The outputs of the vertical pickings 17 and 18 are applied to the upsampler 30 while passing through the line memories 19 and 20 and to the upsampler 30, and the output of the upsampler 30 is horizontal picking ( 21) to go through.
도 3 은 본 발명의 업샘플러 상세 구성도로써3 is a detailed configuration diagram of the upsampler of the present invention;
콘트롤러(31)의 출력은 각각 비교기(33)(36)에 인가되고 비교기(33)의 출력은 MUX(32)(34)의 출력을 선택하게 연결되며The output of the controller 31 is applied to the comparators 33 and 36, respectively, and the output of the comparator 33 is connected to select the output of the MUX 32 and 34.
비교기(36)의 출력은 MUX(35)의 구동을 선택하게 연결된다.The output of the comparator 36 is connected to select the drive of the MUX 35.
그리고 MUX(32)(35)의 출력은 비교기(37)에서 비교되어 MUX(38)의 구동을 제어하므로써 MUX(38)에서 MUX(32)(35)의 출력중 하나의 신호가 선택되어 출력되게 구성된다.The outputs of the MUX 32 and 35 are compared in the comparator 37 to control the driving of the MUX 38 so that one signal of the output of the MUX 32 and 35 is selected and output from the MUX 38. It is composed.
도 4 는 본 발명에서의 100(120)HZ 인터레이스에서의 설명도이고,4 is an explanatory diagram of 100 (120) HZ interlace in the present invention,
도 5 는 본 발명에서의 50(60)HZ 프로그레시브에서의 설명도이다.5 is an explanatory diagram in 50 (60) HZ progressive in the present invention.
본 발명은 업샘플러(30)에서 업샘플링 후에 고주파가 열화되는 것을 방지하기 위하여 우선 버티칼 피킹(17)(18)에서 버티칼 피킹을 행하게 한다.According to the present invention, vertical picking is performed in the vertical picking 17 and 18 to prevent the high frequency from deteriorating after the upsampling in the upsampler 30.
여기서 비티칼 피킹(17)(18)에 버티칼 피킹 계수는 다음과 같다.Here, the vertical peaking coefficients in the vertical peaking 17 and 18 are as follows.
Vertical filter = (ypeak(a/4-b/2+c/4))/256+bVertical filter = (ypeak (a / 4-b / 2 + c / 4)) / 256 + b
즉 2개의 라인메모리를 이용하여 중심값에 대해서 비티칼 피킹을 하여 업샘플러 이후에도 고주파 성분을 유지시키도록 한다.In other words, two line memories are used to perform peak picking on the center value to maintain high frequency components even after the upsampler.
이후에는 업샘플러 기능(function)을 구현하는데 있어 다음 표와 같이 f1out*, f2out* 라는 새로운 개념의 필드를 만들면 된다.Then, to implement the upsampler function, create a new concept field called f1out * and f2out * as shown in the following table.
즉 필드더블이므로 새로운 필드는 A1을 그대로 이용하고 f1out*는 A1,B2를 이용하여 데이타의 계수(coefficient)를 바꿔가면서 새로운 필드를 만들되 f1out*를 만들때는 A1에 웨이트(weight)가 더 많이 가해지도록 한다.That is exactly used for a new field, so field double is A 1 and f1out * is A 1, using the B 2 going to change a coefficient (coefficient) data mandeuldoe a new field when creating a f1out * weight to A 1 (weight) is Allow more to be added.
f2out*는 A1,B2를 이용하여 데이타의 계수를 바꿔가면서 새로운 필드를 만들되 f2out*를 만들때는 B2에 웨이트가 더 많이 가해지도록 한다.f 2 out * uses A 1 and B 2 to change the coefficients of the data, creating a new field, but when f2out * is created, more weight is applied to B 2 .
이와 같이 필드별로 웨이트가 다른 것은 상관도에 따라서 달라지게 되는 것으로 결국 새로 만들어지는 필드는 입력의 어느필드와 더 많은 상관도가 있느냐는 것이다.As such, the different weights for each field depend on the degree of correlation, which means that the newly created field has more correlation with the input field.
f2out는 B2를 이용하여 여기서 나온 출력은 각각 1라인 지연시킨 후 도 2 의 업샘플러 블록에 보낸다.f2out uses B 2 to delay the output from each of the output lines to the upsampler block of FIG.
도 1 의 업샘플러(30)에서는 필드에 따라 각각 다른 3라인을 도 4도 도 5 와 같이 선택한다.In the upsampler 30 of FIG. 1, three different lines are selected as shown in FIGS. 4 and 5 according to fields.
최종적인 출력은 선택된 3라인의 값중 중간값을 비교기를 이용하여 뽑아내게 하므로써 업샘플러(30)의 출력은 다음과 같다.The final output is to extract the middle value of the selected three lines by using a comparator, so that the output of the upsampler 30 is as follows.
upsampler output = yc-(hxpeak(yb/4-yc/2+yd/4))/64-(mxpeak(ya/4-yc/2+ye/4))/64upsampler output = yc- (hxpeak (yb / 4-yc / 2 + yd / 4)) / 64- (mxpeak (ya / 4-yc / 2 + ye / 4)) / 64
이와 같은 계수를 이용하여 수평 피킹(21)에서 수평윤곽을 아래의 표와 같이 보정하므로써 간단한 회로 구성에 의거 업샘플러 구성이 가능하다.By using the above coefficients, the up-sampler can be configured based on a simple circuit configuration by correcting the horizontal contour in the horizontal picking 21 as shown in the table below.
본 발명은 프레임 메모리와 메디안 필터만을 이용하여 종래의 3D 모션 디텍션이 있는 업샘플러가 있는 회로와 같은 효과를 내면서 동시에 별도의 하드웨어 추가없이 NTSC, PAL 을 동시에 프로그레시브할 수 있고 100HZ, 120HZ 필드 더블도 할 수 있는 것이다.According to the present invention, the frame memory and the median filter can be used to achieve the same effect as the circuit with the upsampler with the conventional 3D motion detection, and can simultaneously perform NTSC and PAL without additional hardware. It can be.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026091A KR20010005282A (en) | 1999-06-30 | 1999-06-30 | Median filter upsampler |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026091A KR20010005282A (en) | 1999-06-30 | 1999-06-30 | Median filter upsampler |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010005282A true KR20010005282A (en) | 2001-01-15 |
Family
ID=19598250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990026091A KR20010005282A (en) | 1999-06-30 | 1999-06-30 | Median filter upsampler |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010005282A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7945110B2 (en) | 2006-02-15 | 2011-05-17 | Realtek Semiconductor Corp. | Methods and apparatuses for enhancing image quality |
| US8090213B2 (en) | 2006-02-14 | 2012-01-03 | Realtek Semiconductor Corp. | Image processing device and method |
| US8094237B2 (en) | 2005-10-13 | 2012-01-10 | Realtek Semiconductor Corp. | Signal separation apparatus applied in image transmission system and related method |
-
1999
- 1999-06-30 KR KR1019990026091A patent/KR20010005282A/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8094237B2 (en) | 2005-10-13 | 2012-01-10 | Realtek Semiconductor Corp. | Signal separation apparatus applied in image transmission system and related method |
| US8090213B2 (en) | 2006-02-14 | 2012-01-03 | Realtek Semiconductor Corp. | Image processing device and method |
| US7945110B2 (en) | 2006-02-15 | 2011-05-17 | Realtek Semiconductor Corp. | Methods and apparatuses for enhancing image quality |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950701793A (en) | DIGITAL VIDEO SIGNAL PROCESSOR APPARATUS | |
| CN101521785A (en) | Video signal processing apparatus and method | |
| JPH07303241A (en) | Adaptive field/frame filter for interlaced video signal | |
| KR100472436B1 (en) | Apparatus for processing external input video signal in digital television adaptively | |
| KR20110039553A (en) | Video signal processor and video signal processing method | |
| JPH0435297A (en) | Control signal diffusion device | |
| KR20010005282A (en) | Median filter upsampler | |
| JP2014103559A (en) | Image processing apparatus and image processing method | |
| JP3903703B2 (en) | Sequential scan conversion circuit | |
| RU2010147391A (en) | DEVICE FOR DISPLAYING AN IMAGE OF A PULSE TYPE AND METHOD FOR COMMUNICATING IT IN ACTION | |
| US7750974B2 (en) | System and method for static region detection in video processing | |
| JP2007155716A (en) | Display and method for displaying compressed waveform image | |
| KR100296311B1 (en) | The circuit for improving picture quality of ntsc mode standard image | |
| JP4167423B2 (en) | Video signal processing apparatus and video signal processing method | |
| JPH07319420A (en) | Pixel synchronization device | |
| JP2003032636A (en) | Main scanning conversion equipment using movement compensation and main scanning conversion method | |
| EP0600291A1 (en) | Method and apparatus for adaptive proscan conversion | |
| JP3804595B2 (en) | Video signal processing method and apparatus | |
| US20090096932A1 (en) | Image signal processor and method thereof | |
| JPH02265391A (en) | Noise reduction circuit for chrominance signal | |
| JP2002209191A (en) | Video signal converting device | |
| KR950004465B1 (en) | Horizontal dot noise eliminating comb filter using time delay devices | |
| JP2732648B2 (en) | Motion detection circuit and interpolation signal generation circuit | |
| JPH10327422A (en) | Color information interpolation method and its interpolation circuit | |
| JPH08322020A (en) | Method and apparatus for up-conversion with motion compensated |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| SUBM | Surrender of laid-open application requested |