KR20010003938A - Circuit of power amplifier and amplifying transistor - Google Patents

Abstract

PURPOSE: A current amplifier circuit and a transistor for amplifying are provided not to be sensitive for a designing characteristic and to easily perform an impedance matching. CONSTITUTION: Lines(LP1,Lp2) having an inductance are connected with a base(B) terminal and a collector terminal(C) of a transistor(TR) to pre-tune an output impedance. A resistance(LR1) is connected with the first tuning terminal(P1) to prevent an oscillation of the transistor. The lines compensate the increase of a parasitic capacitance in an input and an output terminal when amplifying a current of a RF(Radio Frequency) in the transistor. Thereby, the reduction of the impedance is compensated. The lines are closed to the collector terminal and the base terminal.

Description

Power amplifier circuit and amplification transistor {CIRCUIT OF POWER AMPLIFIER AND AMPLIFYING TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor for amplifying a power amplifier circuit, and more particularly to a power amplifier circuit and an amplifying transistor in a device using a microwave or millimeter wave.

Typically, high-frequency circuits of a wireless communication system using microwave or millimeter wave are composed of MMIC (Monolitic Microwave Intgrated Circuit) or HMIC (Hybrid Microwave Integrated Circuit). Such integrated circuits are becoming possible thanks to the development of semiconductor technology and micro process. In a wireless communication system using such a microwave or millimeter wave, the power amplifier takes a large part in the transmission unit, and when manufactured as a product, the power amplifier takes a very large part in the price.

If the amplifier is used in the circuit using high frequency, it should be manufactured to meet the characteristics of the high frequency. Especially, if the amplifier circuit is composed of integrated circuit, the characteristic change of each device becomes very sensitive, and therefore, the manufacturing should be performed in consideration of this. In general, a transistor having a large high frequency output has a very small input impedance, which has a value of about a few ohms, and the output impedance for maximum power also has a low resistance component. This makes it difficult to match the impedance of the input, output and intermediate stages of the high frequency power amplifier. 1, an integrated circuit of a power amplifier used at high frequency will be described. Before describing FIG. 1, an integrated circuit is configured to have a resistance by using lines connected between circuits. That is, the resistance of the line itself that connects the portions of one element and the portions of another element is used. This may bring different resistance using the width and thickness of the line. Therefore, in FIG. 1, the reference numeral is given to the section where the line is connected, rather than the direct connection between the elements.

1 is an exemplary diagram of a cluster matched power amplifier according to the prior art. The input terminal RF _IN is applied to the base terminal of the first transistor TR1 through the fifth line L5 and the eighth line L8 via a third capacitor C3 after a high frequency wave is amplified. . In this case, as illustrated in FIG. 1, a bipolar transistor may be used, and a FET which is a field transistor may be used. The emitter stage of the first transistor TR1 is grounded, and the input high frequency signal is first amplified and output through the collector stage. The first amplified high frequency signal through the collector terminal of the first transistor TR1 includes the ninth line L9, the eleventh line L11, the fourteenth line L14, and the eighth capacitor C8. The data is applied to the node N1 via a part connected in series with the sixteenth line L16 and the nineteenth line L19. Then, the high frequency applied to the node N1 is applied to the base end of the second transistor TR2 through the 20th line L20 and the 22nd line L22, and at the same time, the 21st line L21 and the 23rd time. It is applied to the base end of the third transistor TR3 through the line L23. Therefore, it is applied to the base end of the second transistor TR2 and the third transistor TR3. Therefore, the high frequencies amplified by the two transistors TR2 and TR3 are output through the collector terminals of the transistors TR2 and TR3. Here, the second transistor TR2 and the third transistor TR3 may also use an FET which is an electric field transistor. The high frequency signal amplified and output to the collector terminal of the second transistor TR2 is introduced into the node N2 via the 24th line L24 and the 26th line L26, and the third transistor TR3. The high frequency signal amplified and output by the collector stage of is introduced into the node N2 via the 25 th line L25 and the 27 th line L27. Accordingly, the high frequency signal amplified and introduced into the node N2 is output to the output terminal RF _OUT through the 28th line L28 connected in series, the 14th capacitor C14 and the 31st line L31.

Smith chart according to the above configuration is shown in FIG. In FIG. 2, S ₂₂ is an impedance value of a high frequency viewed from the output side of the first transistor TR1 toward the first transistor TR1, and S ₁₁ is an input side of the second transistor TR2 and the third transistor TR3. Input impedance seen from. This is illustrated by the same reference numerals in FIG. 1. As described above, the input impedance and the output impedance of the transistor in the high frequency region have a very small value. That is, as shown in FIG. 2, it can be seen that a small impedance value is located at the outer side of the a side on the Smith chart. However, in order to match the input / output impedance of the transistor, S ₁₁ and S ₂₂ should be located at the same point S ₀ . On the other hand, as shown in Figure 1, the output of the first transistor (TR1) must pass through a large number of lines to be input to the base terminal of the second transistor (TR2) or the third transistor (TR3). When subjected to the in-line position in the S ₁₁ it is moved to S ₁₁ '. Therefore, a large number of lines, resistors, and capacitors are provided at the input terminal and the output terminal of the second transistor TR2 and the third transistor TR3 to reach the position of the impedance matching point S ₀ . Since the value of S ₂₂ , which is the input impedance of the first transistor TR1, also includes a large number of lines as described above, it moves to S ₂₂ ′ and should be moved to the impedance matching point in the same manner as S ₁₁ . Moving to an impedance matching point thus requires a large number of lines, resistors and capacitors.

As described above, many lines, a large number of resistors and capacitors have been used for matching each transistor while performing high frequency amplification. Among them, interstage impedance matching requires large impedance conversion. Therefore, the matching circuit is complicated, and the size of the circuit itself is increased because many passive elements are used, and insertion loss is caused in each passive element. Another method is to reduce the number of passive devices, but this is accompanied by a reduction in bandwidth. Also, if the number of passive elements is reduced, the relative change rate of impedance is increased in circuit, which is very sensitive to amplifier characteristics.

In addition, the fabrication of power amplifiers in integrated circuits such as MMICs or HMICs in high frequency systems using microwave or millimeter waves will result in many design changes during fabrication. This change in design leads to an increase in design time, waste of manpower, and a cost increase. In addition, the use of a large number of passive elements causes a problem that the yield decreases due to the change of characteristics of the active and passive elements.

On the other hand, the low I / O impedance problem of high frequency amplifying transistors is caused by high power amplifiers with high frequency outputs of more than a few tens of watts, as well as high power amplifiers in the millimeter wave band even though the output is less than 1 watt. In other words, as the frequency increases, the impedance and power amplification gains decrease due to parasitle capacitance of the transistor input and output terminals. In order to solve this problem, a cluster matching method has been widely used in the integrated circuit in a high frequency power amplifier. This is a way to connect small transistors in parallel for the desired high frequency output. This method, a kind of power combine method, has the advantage that the power gain does not decrease significantly while increasing the high frequency power. In addition, partial matching is possible during the combination of small transistors with relatively large input / output impedance, which reduces some of the fear of matching from low impedance. However, the length of the transmission line (especially the transmission line before impedance matching) which is inevitably added before and after the transistor combine has a problem of complicating the design of the circuit after the combine.

Accordingly, an object of the present invention is to provide a simple power amplifier and a power amplifier circuit when designing and manufacturing a transmitter power amplifier in a wireless communication system using high frequency.

Another object of the present invention is to provide an amplifying power amplifier transistor for amplifying high frequencies.

Another object of the present invention is to provide a power amplifier circuit that is easy to match impedance in a wireless communication system using high frequency.

It is still another object of the present invention to provide a power amplifier circuit in which a design characteristic is less sensitive to a matching circuit in a power amplifier in a wireless communication system using high frequency.

Still another object of the present invention is to provide a power amplifier and a power amplifier circuit in which the matching circuit of the power amplifier is simple in a wireless communication system using high frequency.

It is still another object of the present invention to provide a circuit which reduces the number of components and reduces insertion loss in the design of a power amplifier circuit in a wireless communication system using high frequency.

The present invention for achieving the above object is an amplifying transistor, the first tuning stage for pre-tuning the input impedance to the base end of the transistor, the line having an inductance between the first tuning end and the base end And a second tuning stage for pre-tuning the output impedance to a collector terminal of the transistor, and a line having an inductance between the second tuning stage and the transistor.

The present invention for achieving the above object is a power amplifier circuit in a device using a microwave or millimeter wave, the first and second tuning stage connecting the lines having inductance to the pre-tuned base and collector stage respectively; A terminal having a line resistance and an input terminal for inputting a signal to be amplified through a capacitor are connected to the base terminal of the first transistor, the emitter terminal of the first transistor is grounded, and the first tuning terminal connected to the base terminal is A first voltage is applied, and the collector terminal of the first transistor is connected to the first node through a resistive line and a capacitor, and the second voltage is applied to the second tuning terminal connected to the collector terminal of the first transistor. A base end of a second transistor having the same configuration as that of the first transistor is connected to the first node, and the second transistor The emitter stage is grounded, the first tuin stage connected to the base terminal of the second transistor is grounded through a first resistor and a first capacitor, the collector stage of the second transistor is connected to a second node, and the second transistor The second tuning end connected to the collector end of the ground is connected through a second capacitor, the base end of the third transistor having the same configuration as the first transistor to the first node, and the emitter end of the third transistor The first tuning end connected to the base of the third transistor is grounded through a second resistor and a third capacitor, and the collector end of the third transistor is connected to the second node. A second tuning stage connected to the collector stage is grounded through a fourth capacitor, and the second node is connected to an output stage for outputting an amplified signal.

1 is an exemplary diagram of a cluster matched power amplifier according to the prior art;

2 is a Smith chart of a high frequency circuit according to the circuit configuration of FIG.

3 is a circuit diagram of a power amplifier constructed of bipolar transistors in accordance with a preferred embodiment of the present invention;

4 is a cluster matching power amplifier circuit diagram designed using the fre tuning transistor of FIG.

5 is a Smith chart according to the configuration of FIG. 4;

6 is a simulation graph between frequency and gain in the case of using the power amplifier according to the configuration of FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a circuit diagram of a power amplifier constructed of bipolar transistors in accordance with a preferred embodiment of the present invention. Referring first to FIG. 3A, a transistor TR is fabricated, and a line Lp2 having an inductance such as a spiral inductor or a micro strip line for pre-tuning the output impedance is connected to the collector terminal C of the transistor. And a second tuning stage P2 separate from the collector stage C. In addition, a line Lp1 having an inductance such as a spiral inductor or a micro strip line is connected to the base end of the transistor in advance, and a first tuning end P1 is provided separately from the base end B. . In addition, the first tuning stage P1 may be configured by connecting a resistor LR1 to prevent the transistor TR from oscillating. As described above, the two lines Lp1 and Lp2 having inductance compensate for the increase in parasitic capacitance at the input / output terminal during the high-frequency power amplification of the transistor TR. That is, when parasitic capacitance occurs in the input / output terminal, the high frequency is short-circuited with respect to the capacitance, and thus the input / output impedance becomes very small. Therefore, when configured as shown in FIG. 3, the impedance reduction can be compensated by artificially adding a line having an inductance for compensating parasitic capacitance in advance at high frequency. However, in the case of adding a line having an inductance in this manner, the line should be placed close to the collector end of the transistor and the base end as long as the process permits. This is because, when a line effect occurs between the collector stage and the base stage, compensation may not be performed by a line having an added inductance due to the generation of capacitance. In addition, although the bipolar transistor has been described as an example in the above description, it can be manufactured using a MOSFET, pHEMT, HBT, and a CMOS transistor.

Designing a cluster-matched power amplifier circuit using transistors fabricated in this way makes it easier to match impedance, makes the design characteristics of the matching circuit less sensitive, simplifies the matching circuit, and improves the yield of the power amplifier. do. In addition, the power amplifier may be applied to an integrated circuit of an MMIC and an HMIC of a wireless communication system using a high frequency without using a single device.

FIG. 4 is a cluster matched power amplifier circuit diagram designed using the fre tuning transistor of FIG. 3. Hereinafter, the configuration and operation of a cluster matching power amplifier circuit designed using a transistor tuned in advance according to the present invention will be described in detail with reference to FIG. 4.

The high frequency before the amplification is input to the input terminal RF _IN , and is connected to the first line by the 41st line L41, the 21st capacitor C21, the 42nd line L42, and the 44th line L44 connected in series. It is input to the base end of the transistor TR1. A 43rd line L43 is connected between the 42nd line L42 and the 44th line L44. Also, the first transistor TR1 is a pre-tuned transistor as shown in FIG. 3. Therefore, the base of the first transistor TR1 includes a line Lp11 having an inductance for tuning and a first tuning stage P11 connected to a resistor LR11, and a line Lp21 having an inductance for tuning in the collector. ) Has a second tuning stage P12 connected thereto. A voltage Vg is applied to the first tuning stage P1 of the first transistor TR1, and a resistor R11 and a capacitor C22 are connected at the same time. The second tuning stage P2 of the first transistor TR1 is connected to another voltage Vd and is grounded by a capacitor C23 at the same time. In addition, the emitter terminal of the first transistor TR1 is grounded, and the collector terminal is connected to the 45th line L45, the 46th line L46, the capacitor C24, and the 47th line L47 connected in series. It is connected to node N1. Then, the high frequency amplified by the first transistor TR1 is applied to the first node N1 through the lines L45, L46, C24, and L47.

The first node N1 is connected to the base end of the second transistor TR2 that is pretuned through the 48th line L48, and the first node N1 is also connected through the 49th line L49 in advance. It is connected to the base end of the tuned third transistor TR3. A line LP21 having an inductance connected to the base of the second transistor TR2 for tuning in advance and a first tuning stage P21 connected to a resistor LR21 for preventing oscillation of the second transistor TR2 are provided. It is grounded through resistor R21 and capacitor C25. The second tuning stage P22 of the line LP22 having the inductance connected to the collector is grounded through the capacitor C27. In addition, the emitter terminal of the second transistor TR2 is grounded, and the collector terminal is connected to the second node N2 through the 50th line L50. A first tuning stage P31 connected to a resistor LR31 connected to prevent oscillation of the third transistor TR3 through a line LP31 having an inductance connected to the base of the third transistor TR3 is a resistor. It is grounded through the R23 and the capacitor C26. The first tuning stage P32 of the line LP32 having the inductance connected to the collector is grounded through the capacitor C28. In addition, the emitter terminal of the third transistor TR3 is grounded, and the collector terminal is connected to the second node N2 through the 51st line L51.

As such, the high frequency amplified second by the second transistor TR2 and the third transistor TR3 flows into the second node N2, and the 52nd line L52, the capacitor C30, and the 54th wave. Output is via line L54. And between the 52nd line (L52) and the capacitor (C30) is grounded through the 53rd line (L53) and the capacitor (C29), at the same time the contact between the capacitor (C29) and the 53rd line (L53) The voltage of Vd is applied.

An operation according to the configuration as shown in FIG. 4 will be described with reference to FIGS. 5 to 6. FIG. 5 is a Smith chart according to the configuration of FIG. 4, and FIG. 6 is a simulation graph between frequency and gain when the power amplifier according to the configuration of FIG. 4 is used.

When configured as shown in FIG. 4 in a wireless communication system using the microwave or millimeter wave input impedance matching point in the S ₁₁ it is moved to S ₁₁ 'as shown in Fig. Therefore, it is possible to simply configure the input impedance without using a large number of resistors, a large number of capacitors and a large number of lines for matching as shown in FIG. That is, as shown in FIG. 4, three lines and one capacitor can be moved to the first node N1, and in particular, the configuration to the output terminal via the second and third transistors TR2 and TR3 is also simple. The solution can be constructed. In this case, as shown in FIG. 3, the input impedance and the output impedance are matched to the base and collector terminals by using a pretuned transistor so that the input impedance and the output impedance are changed according to the frequency variation and the surrounding environment. The fluctuation is less, and the circuit can be easily configured. In the case of an integrated circuit such as HMIC or MMIC, each transistor is connected to the outside of the package. This increases the impedance value by adding parallel inductance at the base and collector ends. Accordingly, the input reflection coefficients and the output reflection coefficients S ₁₁ and S ₂₂ of the 60 GHz band power transistor pHMET are also moved from the outside of the point a to the inside. Therefore, the outer point corresponds to 10% of the total resistance when the resistance change is about 10 ohms. However, if the resistance is moved to the inside and the total resistance is 100 ohms, if 1 ohm changes, it corresponds to 1% of the total resistance. Therefore, when the resistance change is 1 ohm, if the overall resistance is greatly increased, the effect on the whole becomes less. In a circuit configured to operate in this configuration, the gate compensation bolt tip has a width of 25 um, a length of 110 um, a MIM bypass capacitor of 70 um * 70 um, and a stabilization resistance of 15 ohms. It is determined to be 30um, and dE for the compensation for the length of the short steep width of 70um to 100um when setting the length from the bypass capacitor and the drain to 90um 6 and the gain curve S ₂₁ as input and output impedance, S _11, S Appears ₂₂ . As shown in FIG. 6, the circuit changes more stably as shown in the gain curve for each frequency of the input and output impedances S ₁₁ , S ₁₂ , and S ₂₂ .

Therefore, in the case of having such a configuration, the circuit can be conveniently configured, and detailed configuration will be performed. In addition, when a transistor is manufactured, a resistor for stabilizing the operation of the transistor is added to an input terminal or a line having an inductance parallel to the gate or the base, thereby making the operation of the transistor more stable.

By configuring the power amplifier to be tuned in advance as described above, there is an advantage that the input and output amplification degree can be stabilized when the transistor is used as a high frequency amplifier. In addition, there is an advantage that the configuration of the circuit is simplified by applying to a circuit constituting a high frequency circuit using such a pre-tuned amplifier.

Claims (8)

In the amplifying transistor, A first tuning stage for pre-tuning an input impedance to a base terminal of the transistor, a line having an inductance between the first tuning stage and the base terminal, And a second tuning stage for pre-tuning an output impedance to a collector stage of the transistor, and a line having an inductance between the second tuning stage and the transistor. The method of claim 1, And the lines having the impedance as a spiral inductor, and are positioned as close as possible to the base bomb and the collector stage during semiconductor processing to minimize parasitic capacitance. The method of claim 1, And the lines having the impedance as a micro strip line, and are positioned as close as possible to the base bomb and the collector stage during semiconductor processing to minimize parasitic capacitance. The method according to claim 1, wherein And a resistor for preventing the transistor from oscillating between the first tuning stage and the line having the inductance. In a power amplifier circuit in a circuit using microwave or millimeter wave, An input terminal for amplifying a signal to be amplified through a line and a capacitor having a line resistance at a base terminal of a first transistor having first and second tuning stages each having a line having inductance connected to a pretuned base stage and a collector stage, respectively. Connect, The emitter terminal of the first transistor is grounded, the first tuning terminal connected to the base terminal applies a first voltage, The collector terminal of the first transistor is connected to the first node through a resistive line and a capacitor, and applies a second voltage to the second tuning terminal connected to the collector terminal of the first transistor. A base end of a second transistor having the same configuration as the first transistor is connected to the first node, The emitter terminal of the second transistor is grounded, and the first tuin terminal connected to the base terminal of the second transistor is grounded through a first resistor and a first capacitor, The collector terminal of the second transistor is connected to the second node, the second tuning terminal connected to the collector terminal of the second transistor is grounded through a second capacitor, A base end of a third transistor having the same configuration as the first transistor is connected to the first node, The emitter end of the third transistor is grounded, the first tuning end connected to the base end of the third transistor is grounded through a second resistor and a third capacitor, The collector terminal of the third transistor is connected to the second node, the second tuning terminal connected to the collector terminal of the third transistor is grounded through a fourth capacitor, And the second node is connected to an output terminal for outputting an amplified signal. The method of claim 5, Wherein the pretuned first to third transistors are formed of one element, and the first and second tuning stages are connected so that the capacitance is minimized at the time of manufacture. The method according to claim 5 or 6, And grounding the first tuning stage of the first transistor through a third resistor and a fifth resistor, and grounding the second tuning stage of the first transistor through a sixth capacitor. The method according to claim 5 or 6, And a predetermined voltage is applied to the output terminal connected to the second node through a seventh capacitor and at the same time.