KR20010003443A - Method of forming metal wiring for semiconductor device - Google Patents

Method of forming metal wiring for semiconductor device Download PDF

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Publication number
KR20010003443A
KR20010003443A KR1019990023740A KR19990023740A KR20010003443A KR 20010003443 A KR20010003443 A KR 20010003443A KR 1019990023740 A KR1019990023740 A KR 1019990023740A KR 19990023740 A KR19990023740 A KR 19990023740A KR 20010003443 A KR20010003443 A KR 20010003443A
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KR
South Korea
Prior art keywords
duv
resist layer
resist film
film
exposed
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KR1019990023740A
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Korean (ko)
Inventor
최상태
이철수
김정수
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김영환
현대전자산업 주식회사
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Priority to KR1019990023740A priority Critical patent/KR20010003443A/en
Publication of KR20010003443A publication Critical patent/KR20010003443A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to simplify processing steps by forming an interconnecting contact hole by an etch process, and to improve reliability by preventing a loss of a resist layer at an interface between a deep ultraviolet(DUV)-resist layer and an I-line resist layer. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate(40). A deep ultraviolet(DUV)-resist layer(42) is applied and an exposure is performed by using a reticle for a contact hole. An I-line resist layer(43) is applied on the DUV-resist layer and an exposure is performed by using a reticle(200) for an interconnection. The DUV-resist layer and the I-line resist layer are developed to form a T-shaped groove exposing a part of the interlayer dielectric by removing a portion in which an exposure is performed. The substrate of the resultant structure is hardened to control etch selectivity of the DUV-resist layer and the I-line resist layer with the insulating layer. The DUV-resist layer exposed by the I-line resist layer is etched by using the DUV-resist layer and the I-line resist layer as a mask while the interlayer dielectric is etched until a part of the substrate is exposed to form a contact hole of an interconnection type. The DUV-resist layer and the I-line resist layer are removed. An interconnecting metal layer is formed on the interlayer dielectric to fill the contact hole. The metal layer is entirely etched until the interlayer dielectric is exposed to form a metal interconnection.

Description

반도체 소자의 금속 배선 형성방법{Method of forming metal wiring for semiconductor device}Method of forming metal wiring for semiconductor device

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히 이중 데머신(dual damascene) 공정에 의한 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices by a dual damascene process.

반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.

도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도이다. 도 1을 참조하면, 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 기판(10)일부가 노출되도록 층간절연막(11)을 식각하여 콘택홀을 형성한다. 상기 콘택홀에 매립되도록 층간절연막(11) 상에 금속막을 증착하고 패터닝하여 금속 배선(12a, 12b)을 형성한다.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device. Referring to FIG. 1, an interlayer insulating layer 11 is formed on a semiconductor substrate 10, and a contact hole is formed by etching the interlayer insulating layer 11 to expose a portion of the substrate 10. Metal wires 12a and 12b are formed by depositing and patterning a metal film on the interlayer insulating film 11 so as to be filled in the contact hole.

그러나, 상기한 바와 같이 양각 공정에 의해 배선을 형성하는데, 금속막의 열악한 식각 특성에 의해, 도 1에 도시된 바와 같이, 식각 후 금속 배선(12a, 12b) 사이에서 브리지가 발생된다. 이러한, 브리지는 소자의 고집적화에 따라 더욱더 심해져서 소자의 전기적 특성을 저하시킨다.However, as described above, the wiring is formed by an embossing process, and due to the poor etching characteristics of the metal film, as shown in FIG. 1, a bridge is generated between the metal wirings 12a and 12b after etching. Such bridges become more severe with high integration of the device, thereby degrading the electrical characteristics of the device.

따라서, 종래에는 고집적화에 따른 배선 사이의 브리지를 방지하기 위하여 데머신(damascene) 공정으로 배선을 형성하였다. 즉, 도 2는 데머신 공정에 의해 형성된 반도체 소자의 금속 배선을 나타낸 단면도로서, 도 1에서와는 달리 층간절연막(21) 내에 화학기계연마(Chemical Mechanical Polishing; CMP)로 금속막을 전면 식각하여 금속 배선(22)을 완전히 매립시켜 형성하기 때문에, 금속막의 열악한 식각특성으로 인해 발생되는 인접 배선과의 브리지 문제가 방지된다.Therefore, in the related art, wirings were formed by a damascene process to prevent bridges between wirings due to high integration. That is, FIG. 2 is a cross-sectional view illustrating a metal wiring of a semiconductor device formed by a demachine process. Unlike FIG. 1, the metal film is etched by chemical mechanical polishing (CMP) in the interlayer insulating film 21. Since 22) is completely embedded, the bridge problem with the adjacent wiring caused by the poor etching characteristics of the metal film is prevented.

그러나, 상기한 데머신 공정에 의한 금속배선을 형성하는데 있어서는, 도 1에서와는 달리 금속 배선(22)의 형태로 콘택홀을 형성해야 하기 때문에, 2번의 마스크 공정, 예컨대 2번의 포토레지스트막의 도포, 노광 및 현상공정이 요구될 뿐만 아니라 2번의 식각공정이 각각 진행되어야 한다. 이에 따라, 공정이 복잡해지고, 제조비용이 높아지는 문제가 발생한다.However, in forming the metal wiring by the above-described demachine process, since the contact hole must be formed in the form of the metal wiring 22 unlike in FIG. 1, two mask processes, for example, application and exposure of two photoresist films are performed. In addition to the development and development process, two etching processes must be performed respectively. As a result, the process becomes complicated and the production cost increases.

한편, 기출원된 특허출원 제 98-59952 호에서는, 상기한 바와 같은 복잡한 공정을 단순화시키기 위하여, 양의 포토레지스트막과 음의 포토레지스트막을 혼용하여 배선용 포토레지스트막 패턴을 형성한 후, 한번의 식각공정으로 배선용 콘택홀을 형성한 후 배선을 형성하는 방법을 제시하였다.On the other hand, in the previously published patent application No. 98-59952, in order to simplify the complicated process as described above, after forming a wiring photoresist film pattern by mixing a positive photoresist film and a negative photoresist film, After forming a contact hole for wiring by an etching process, a method of forming a wiring was proposed.

즉, 본 특허에서는 도 3에 도시된 바와 같이, 층간절연막(31)이 형성된 기판(30) 상에, 양의 포토레지스트막(32)을 도포한 후 콘택홀용 레티클로 노광하고, 그 상부에 음의 포토레지스트막(33)을 도포하고 배선용 레티클을 이용하여 노광한 후, 양의 포토레지스트막(32)과 음의 포토레지스트막(33)을 동시에 현상한다. 도 3에서, 32의 빗금친 부분은 빛에 의해 노광된 부분을 나타낸다.That is, in the present patent, as shown in FIG. 3, a positive photoresist film 32 is coated on a substrate 30 on which an interlayer insulating film 31 is formed, and then exposed with a contact hole reticle, and a negative portion is formed on the upper surface of the substrate 30. After the photoresist film 33 is coated and exposed using a wiring reticle, the positive photoresist film 32 and the negative photoresist film 33 are simultaneously developed. In FIG. 3, hatched portions 32 represent portions exposed by light.

그러나, 양의 포토레지스트막(32)과 음의 포토레지스트막(33)을 혼용하게 되면, 노광 후 진행되는 현상공정시, 양의 포토레지스트막(32)과 음의 포토레지스트막(33)의 경계부분(A)의 양의 포토레지스트막(32)이 손실되는 문제가 발생된다. 즉, 음의 포토레지스트막(33)은 빛에 의해 반응하였기 때문에 현상용액에 의해 식각이 되지 않지만, 양의 포토레지스트막(32)은 빛에 의해 반응하였기 때문에, 현상용액이 경계부분(A)으로 스며들게 되면, 노광된 양의 포토레지스트막(32)이 현상용액과 반응하여 일부 손실된다. 이러한 손실에 의해 결국, 배선의 신뢰성이 저하되는 문제가 발생된다.However, when the positive photoresist film 32 and the negative photoresist film 33 are mixed, the positive photoresist film 32 and the negative photoresist film 33 may be formed during the development process that is performed after exposure. The problem is that the positive photoresist film 32 at the boundary portion A is lost. That is, since the negative photoresist film 33 reacts with light, it is not etched by the developing solution, but since the positive photoresist film 32 reacts with light, the developing solution is bounded by the boundary (A). If soaked in, the exposed amount of photoresist film 32 reacts with the developing solution and is partially lost. This loss eventually leads to a problem that the reliability of the wiring is lowered.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 공정을 단순화시키면서 포토레지스트막의 손실로 인한 배선의 신뢰성 저하를 방지할 수 있는 반도체 소자의 배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a wiring of a semiconductor device capable of preventing the degradation of the wiring due to loss of a photoresist film while simplifying the process.

도 1은 종래의 반도체 소자의 금속 배선을 나타낸 단면도.1 is a cross-sectional view showing a metal wiring of a conventional semiconductor device.

도 2는 종래의 데머신 공정에 의한 반도체 소자의 금속 배선을 나타낸 단면도.2 is a cross-sectional view showing a metal wiring of a semiconductor device by a conventional demachine process.

도 3은 종래의 양의 포토레지스트막과 음의 포토레지스트막을 혼용한 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.3 is a cross-sectional view for explaining a method for forming metal wiring of a semiconductor device in which a conventional positive photoresist film and a negative photoresist film are mixed.

도 4a 내지 도 4i는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.4A to 4I are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

40 : 반도체 기판 41 : HDP 절연막40: semiconductor substrate 41: HDP insulating film

42 : DUV 레지스트막 43 : I- 라인 레지스트막42 DUV resist film 43 I-line resist film

44 : 콘택홀 45 : 금속막44: contact hole 45: metal film

45A : 금속배선45A: Metal Wiring

100 : 콘택홀용 레티클 200 : 금속배선용 레티클100: reticle for contact hole 200: reticle for metal wiring

상기한 본 발명의 목적을 달성하기 위하여 본 발명에 따라, 반도체 기판 상에 층간절연막을 형성하고, 층간절연막 상에 DUV-레지스트막을 도포하고 콘택홀용 레티클을 이용하여 노광한다. 그런 다음, 노광된 DUV-레지스트막 상에 I-라인 레지스트막을 도포하고 배선용 레티클을 이용하여 노광하고, 노광된 DUV-레지스트막과 I-라인 레지스트막을 현상하여 노광된 부분을 제거하여 층간절연막의 일부를 노출시키는 T자형의 홈을 형성한다. 그리고 나서, 결과물 구조의 기판을 경화하여 DUV-레지스트막 및 I-라인 레지스트막과 층간절연막과의 식각선택도를 조절하고, DUV-레지스트막과 I-라인 레지스트막을 마스크로하여 I-라인 레지스트막에 의해 노출된 DUV-레지스트막을 식각함과 동시에 층간절연막을 기판의 일부가 노출되도록 식각하여 배선형태의 콘택홀을 형성한다. 그 후, DUV-레지스트막과 I-라인 레지스트막을 제거하고, 콘택홀에 매립되도록 층간절연막 상에 배선용 금속막을 형성한 후, 금속막을 층간절연막이 노출될 때까지 전면식각하여 금속배선을 형성한다.In order to achieve the above object of the present invention, according to the present invention, an interlayer insulating film is formed on a semiconductor substrate, a DUV-resist film is applied on the interlayer insulating film, and exposed using a reticle for contact holes. Then, an I-line resist film is applied on the exposed DUV-resist film and exposed using a wiring reticle, and the exposed DUV-resist film and I-line resist film are developed to remove the exposed portions to remove a part of the interlayer insulating film. Form a T-shaped groove to expose the. Then, the substrate of the resulting structure was cured to adjust the etch selectivity of the DUV-resist film, I-line resist film and interlayer insulating film, and the I-line resist film using the DUV-resist film and I-line resist film as a mask. The exposed DUV-resist film is etched and the interlayer insulating film is etched to expose a portion of the substrate to form a contact hole in the form of a wiring. Thereafter, the DUV-resist film and the I-line resist film are removed, a wiring metal film is formed on the interlayer insulating film so as to be embedded in the contact hole, and the metal film is etched entirely until the interlayer insulating film is exposed to form metal wiring.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 4a 내지 도 4i는 본 발명의 실시예에 따른 새로운 데머신 공정에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.4A to 4I are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device by a new demachine process according to an embodiment of the present invention.

도 4a에 도시된 바와 같이, 반도체 기판(40) 상에 층간절연을 위한 산화막으로서 고밀도 플라즈마(High Density Plasma; HDP) 절연막(41)을 형성한다. 그런 다음, 도 4b에 도시된 바와 같이, HDP 절연막(41) 상에 DUV-레지스트막(Deep UV resist; 42)을 도포하고, 콘택홀 형성용 레티클(100)를 이용하여 노광한다.As shown in FIG. 4A, a high density plasma (HDP) insulating film 41 is formed on the semiconductor substrate 40 as an oxide film for interlayer insulation. Then, as shown in FIG. 4B, a deep UV resist 42 is coated on the HDP insulating film 41, and exposed using the reticle 100 for forming a contact hole.

도 4c를 참조하면, 노광된 DUV-레지스트막(42) 상에 I-라인 레지스트막(43)을 도포하고, 금속배선용 레티클(200)을 이용하여 노광한다. 이때, I-라인 레지스트막(43)은 후속 금속배선 형성시 마스크 역할만을 수행하기 때문에, 도포시의 균일도(uniformity)는 크게 중요하지 않으며 오버 노광되어도 큰 문제가 발생되지 않는다. 또한, 하부의 DUV-레지스트막(42)은 I-라인 노광기에서 파장이 다르기 때문에, I-라인 레지스트막(43)의 노광시 반응하지 않는다. 이에 따라, 이후 현상공정시 레지스트막(42, 43) 사이의 경계부분의 손실이 방지된다.Referring to FIG. 4C, an I-line resist film 43 is coated on the exposed DUV-resist film 42, and exposed using the reticle 200 for metallization. At this time, since the I-line resist film 43 only plays a role of a mask in forming subsequent metal wirings, uniformity during application is not important and does not cause a large problem even when overexposed. In addition, since the wavelength of the lower DUV-resist film 42 is different in the I-line exposure machine, it does not react when the I-line resist film 43 is exposed. This prevents the loss of the boundary between the resist films 42 and 43 during the subsequent development process.

도 4d를 참조하면, DUV-레지스트막(42)과 I-라인 레지스트막(43)을 현상하여, 노광된 부분(42A, 43A)를 제거함으로써, HDP 절연막(41)의 일부를 노출시키는 T 자형의 홈(T)을 형성한다. 즉, 한번의 현상공정으로 레지스트막(42, 43)을 동시에 현상하기 때문에, 공정수가 감소된다.Referring to Fig. 4D, the DUV-resist film 42 and the I-line resist film 43 are developed to remove the exposed portions 42A and 43A, thereby exposing a portion of the HDP insulating film 41. To form a groove (T). That is, since the resist films 42 and 43 are developed simultaneously in one developing step, the number of steps is reduced.

그리고 나서, 도 4e에 도시된 바와 같이, 결과물 구조의 기판을 전자빔(electric-beam) 경화공정으로 경화시켜, DUV-레지스트막(42) 및 I-라인 레지스트막(43)과, HDP 절연막(41)과의 식각선택도를 조절한다. 즉, 전자빔의 양과 조사시간에 따라 DUV-레지스트막(42) 및 I-라인 레지스트막(43)과 HDP 절연막(31)의 식각선택도를 조절할 수 있다. 또한, DUV-레지스트막(42)의 두께를 조절하여 이후 콘택홀의 식각깊이를 결정할 수도 있다. 또한, 하드 베이킹 공정의 시간과 온도를 조절하여 식각 선택도를 조절할 수도 있다.Then, as shown in FIG. 4E, the substrate having the resultant structure is cured by an electron beam curing process, so that the DUV-resist film 42 and the I-line resist film 43 and the HDP insulating film 41 Adjust the etching selectivity with). That is, the etching selectivity of the DUV-resist film 42, the I-line resist film 43, and the HDP insulating film 31 can be adjusted according to the amount of the electron beam and the irradiation time. In addition, the thickness of the DUV-resist layer 42 may be adjusted to determine the etching depth of the contact hole. In addition, the etching selectivity may be controlled by adjusting the time and temperature of the hard baking process.

그런 다음, I-라인 레지스트막(43)을 마스크로하여 노출된 DUV- 레지스트막(42) 및 HDP 절연막(41)을 식각한다. 이때, 식각의 초기에는, 도 4f에 도시된 바와 같이, 전자빔 경화에 따른 DUV-레지스트막(42)과 노출된 HDP 절연막(41) 사이의 식각속도의 차이에 의해, 노출된 HDP 절연막(41)이 소정두께만큼 일부 식각됨과 동시에 DUV-레지스트막(42)도 식각된다. 한편, 도 4g에 도시된 바와 같이, 식각도중에 O2개스를 첨가한 플라즈마 식각을 진행하여, HDP 절연막(41) 상부의 노출된 DUV-레지스트막(42)의 잔류물을 완전히 제거하고, 연속적으로 HDP 절연막(41)을 기판(40)이 표면이 노출될 때까지 식각하여, 배선형태의 콘택홀(44)을 형성한다. 즉, 두층의 레지스트막(42, 43)을 이용하여 한번의 식각공정으로 콘택홀(44)을 형성하기 때문에 식각공정수가 감소된다.Then, the exposed DUV-resist film 42 and the HDP insulating film 41 are etched using the I-line resist film 43 as a mask. At this time, at the beginning of etching, as shown in FIG. 4F, the exposed HDP insulating film 41 is exposed by the difference in etching speed between the DUV-resist film 42 and the exposed HDP insulating film 41 due to electron beam curing. The DUV-resist film 42 is also etched at the same time as partly etched by this predetermined thickness. Meanwhile, as shown in FIG. 4G, plasma etching with O 2 gas added during the etching process is performed to completely remove the residue of the exposed DUV-resist layer 42 on the HDP insulating layer 41, and continuously. The HDP insulating layer 41 is etched until the surface of the substrate 40 is exposed to form a contact hole 44 in the form of a wiring. That is, since the contact holes 44 are formed in one etching process using the two resist films 42 and 43, the number of etching processes is reduced.

도 4h를 참조하면, 공지된 방법으로 DUV-레지스트막(42) 및 I-라인 레지스트막(43)을 제거하고, 콘택홀(44)에 매립되도록 HDP 절연막(41) 상에 배선용 금속막(45)을 형성한다. 그리고 나서, 금속막(45)을 HDP 절연막(41)이 노출될 때까지 전면식각하여 도 4i에 도시된 바와 같이, 금속배선(45A)을 형성한다. 이때, 전면식각은 화학기계연마(Chemical Mechanical Polishing; CMP) 기술로 진행한다.Referring to FIG. 4H, the wiring metal film 45 is disposed on the HDP insulating film 41 so as to remove the DUV-resist film 42 and the I-line resist film 43 by a known method, and to fill the contact holes 44. ). Then, the metal film 45 is etched entirely until the HDP insulating film 41 is exposed to form the metal wiring 45A, as shown in FIG. 4I. At this time, the front etching is performed by chemical mechanical polishing (CMP) technology.

상기한 본 발명에 의하면, 데머신 공정에 의한 배선의 형성시, 마스크로서 사용되는 DUV-레지스트막과 I-라인 레지스트막을 한번의 현상공정으로 동시에 형성하고, 한번의 식각공정으로 배선용 콘택홀을 형성하기 때문에, 공정이 단순해지고 제조비용이 감소된다. 또한, 음과 양의 포토레지스트막을 혼용하는 것 없이, 노광 파장이 다른 DUV-레지스트막과 I-라인 레지스트막을 사용하기 때문에, 노광 후 두 층의 레지스트막 사이의 경계면에서의 레지스트막의 손실이 방지되어, 결국 배선의 신뢰성이 향상된다.According to the present invention described above, in the formation of the wiring by the demachine process, the DUV-resist film and the I-line resist film, which are used as masks, are simultaneously formed in one development process, and the wiring contact holes are formed in one etching process. This simplifies the process and reduces the manufacturing cost. In addition, since a DUV-resist film and an I-line resist film having different exposure wavelengths are used without mixing a positive and a positive photoresist film, the loss of the resist film at the interface between the two resist films after exposure is prevented. Consequently, the reliability of the wiring is improved.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (5)

반도체 기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간절연막 상에 DUV-레지스트막을 도포하고 콘택홀용 레티클을 이용하여 노광하는 단계;Applying a DUV-resist film on the interlayer insulating film and exposing using a contact hole reticle; 상기 노광된 DUV-레지스트막 상에 I-라인 레지스트막을 도포하고 배선용 레티클을 이용하여 노광하는 단계;Applying an I-line resist film on the exposed DUV-resist film and exposing using a wiring reticle; 상기 노광된 DUV-레지스트막과 상기 I-라인 레지스트막을 현상하여 상기 노광된 부분을 제거하여 상기 층간절연막의 일부를 노출시키는 T자형의 홈을 형성하는 단계;Developing the exposed DUV-resist film and the I-line resist film to remove the exposed portion to form a T-shaped groove exposing a portion of the interlayer insulating film; 상기 결과물 구조의 기판을 경화하여 상기 DUV-레지스트막 및 상기 I-라인 레지스트막과 상기 층간절연막과의 식각선택도를 조절하는 단계;Curing an etch selectivity of the DUV-resist film and the I-line resist film and the interlayer insulating film by curing the substrate having the resultant structure; 상기 DUV-레지스트막과 상기 I-라인 레지스트막을 마스크로하여 상기 I-라인 레지스트막에 의해 노출된 DUV-레지스트막을 식각함과 동시에 상기 층간절연막을 상기 기판의 일부가 노출되도록 식각하여 배선형태의 콘택홀을 형성하는 단계;Using the DUV-resist film and the I-line resist film as a mask, the DUV-resist film exposed by the I-line resist film is etched, and the interlayer insulating film is etched to expose a portion of the substrate to form a contact. Forming a hole; 상기 DUV-레지스트막과 상기 I-라인 레지스트막을 제거하는 단계;Removing the DUV-resist film and the I-line resist film; 상기 콘택홀에 매립되도록 상기 층간절연막 상에 배선용 금속막을 형성하는 단계; 및,Forming a wiring metal film on the interlayer insulating film so as to fill the contact hole; And, 상기 금속막을 상기 층간절연막이 노출될 때까지 전면식각하여 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming a metal wiring by etching the metal film on the entire surface until the interlayer insulating film is exposed. 제 1 항에 있어서, 상기 층간절연막은 HDP 절연막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.2. The method of claim 1, wherein the interlayer insulating film is formed of an HDP insulating film. 제 1 항에 있어서, 상기 경화는 전자빔을 이용하여 진행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the curing is performed using an electron beam. 제 1 항에 있어서, 상기 콘택홀을 형성하는 단계에서, 상기 DUV-레지스트막이 제거된 후 식각도중에 O2개스를 첨가한 플라즈마 식각을 진행하여 상기 DUV-레지스트막의 잔류물을 완전히 제거하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the forming of the contact hole comprises removing the DUV-resist film completely by performing plasma etching with O 2 gas added therein during the etching. A metal wiring forming method of a semiconductor device. 제 1 항에 있어서, 상기 전면식각은 화학기계연마로 진행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the front surface etching is performed by chemical mechanical polishing.
KR1019990023740A 1999-06-23 1999-06-23 Method of forming metal wiring for semiconductor device KR20010003443A (en)

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