KR20010002730A - Method and apparatus for ensuring transfer order in a packet-switch with a dual-switching plane000 - Google Patents

Abstract

PURPOSE: A method for securing a transmission sequence in a packet switch having a dual switching plane is provided to offer a cell distribution and arbitration method which secures the transmission sequence in a 2Q2P(dual input queue per input port) and has an excellent queuing delay time under a bust traffic condition at the same time. CONSTITUTION: A cyclic-in-cyclic-out(CICO) system alternately distributes asynchronous transfer mode(ATM) cells transmitted to each inputting port to dual inputting queues. The CICO system endows transmitting chances according to a transmitted order for foremost cells of the multiple inputting queues, and decides whether the foremost cells are available for transmitting to outputting ports. If so, the CICO system transmits the foremost cells to the selected outputting ports through a dual switching plane. The CICO system alternately distributes transmitted cells to two inputting queues when asynchronous transfer mode(ATM) cells are transmitted to an input terminal, and alternately services head cells of the two inputting queues while arbitrating the transmitted cells to prevent a transmission sequence from being turned in the input terminal. The transmission sequence in an exchange is secured by a CICO operation. As the transmitted cells are alternately distributed to the two inputting queues, an output-buffering switch is delayed under a grouped traffic condition. Without using a time stamp and a cell sequence restoring circuit, As operations of a transmitted cell distributor, a transmission arbitrator, and an output terminal controller are simple, the CICO system is suitable for a high-speed exchange design having a link capacity of a gigabit/second level.

Description

Method and apparatus for guaranteeing transmission order in packet switch with dual switching plane {METHOD AND APPARATUS FOR ENSURING TRANSFER ORDER IN A PACKET-SWITCH WITH A DUAL-SWITCHING PLANE000}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous transfer mode (hereinafter referred to as "ATM") cell switching scheme, and more particularly to a method of improving transmission capability by guaranteeing transmission order in a packet switch having a dual switching plane.

Recently, network link capacity has been expanded to gigabits per second (Gigabit / sec) in the local area network (hereinafter referred to as 'LAN') and wide area network (hereinafter referred to as 'WAN'), and is based on a crossbar switching fabric suitable for supporting high speed links. There is an increasing demand for scalable switch architectures in terms of input buffering switches and port-density. In other words, the existing ATM switch is designed based on the transmission rate of 155Mbps per port. Therefore, the main switch is an output buffering switch that provides optimal performance in terms of queuing delay time. However, in order to support OC-48 (2.5Gbps) link for ATM switch and 1Gbps Gigabit Ethernet link for LAN switch or Gigabit router, NV (N: switch size, V: I / O required for output buffering method) The implementation of an output buffer memory with an operating speed of link transfer rate becomes impossible with the current technology as N becomes larger. Therefore, in the design of a packet switch having a gigabit or higher port transfer rate, an input buffering method requiring a link speed buffer memory and a switching fabric has been proposed as a realistic alternative.

However, the input buffering method has a problem that the maximum throughput is limited to 58.6% due to the well-known blocking of the head-of-line (HOL). In order to overcome this problem, methods for configuring the input buffer as a non-FIFO queue or improving the switching capability of the switching fabric are proposed.

One conventional approach is to use a dual-switching plane to improve transmission capability. This scheme can be configured in two ways, as shown in Fig. 1 or 2, depending on how the dual switching plane is used. In both schemes, each input queue is a first-in-first-out queue, where only one cell can be read in one slot, and the output queue is doubled up so that two cells can be written in the same slot. 1 shows a single FIFO input queue 10 at each input port, and the head cell (HOL cell) of the FIFO input queue 10 is connected to an input plane selector 20 through which of the two switching planes 30a and 30b. Selected one and transmitted to the FIFO output queue 50 of the output port through the output terminal controller 40, two cells can be simultaneously transmitted to one output port (50). Figure 2 has two FIFO input cues 70 and an input cue selector 60 for controlling their selection at each input port, and each FIFO input cue 70 is directly connected to the corresponding switching planes 80a and 80b. The structure is different from that of the ATM switch of FIG. In the ATM switch of FIG. 2, two cells can be simultaneously transmitted from one input port, and two cells can be simultaneously transmitted to one output terminal. Here, the ATM switch of FIG. 1 will be referred to as a 1Q2P (one input queue per input port, one switching plane) switch, and the ATM switch of FIG. 2 will be referred to as a dual-input queue per input port (dual-switching plane) switch. .

In the case of a dual switching plane, since two switching paths exist in a single input / output port pair in a switch, a cell's transmission order may be changed, and a careful design is required. In the case of the 1Q2P switch structure of FIG. 1, only one FIFO queue 10 exists at each input, and only the head cell of each FIFO queue, that is, the HOL cell participates in contention, thereby ensuring a cell transmission order. However, in the 1Q2P switch of FIG. 1, two cells can be simultaneously transmitted to one output terminal, but only one cell can be transmitted from one input terminal, resulting in a low throughput and insufficient utilization of the dual switching plane. Actually, the 1Q2P switch shows 88.6% throughput when random traffic is applied. In this structure, increasing the switching planes to three and four increases the throughput to 97.6% and 99.7%, respectively.

In the 2Q2P switch structure of FIG. 2, not only two cells can be simultaneously transmitted to one output terminal but also two cells can be simultaneously transmitted in one input queue 70, thereby reducing output collision and input collision. Recently, Kolias, in his paper ("Performance Analysis of Multiplane Nonblocking ATM Switches", IEEE Globecom'98, pp.356-362, 1998), puts cells arriving at each input in a random traffic environment into one of two input queues. The maximum throughput of the 2Q2P switch proved to be 100% when randomly distributed. In other words, the 2Q2P switch structure merely duplicates the pure input buffering switch structure (two input queues per input stage, two switching planes) and has an output buffer with improved speed at each output stage. This has the advantage that the performance of an output buffering switch requiring an output buffer memory can be obtained. In addition, unlike the output buffering method, even if the switch size N is increased, each input buffer memory speed, switching speed of the switching plane, and output buffer memory speed which are required are excellent in scalability. Therefore, it is a very desirable structure when designing a high-capacity high-capacity ATM switch and an Internet Protocol router or a LAN switch having a capacity of 'gigabit / second' per port.

However, the 2Q2P switch structure has a problem of transmission order guarantee. That is, since two input queues exist at each input terminal, the IQS of each input terminal must select an input queue to distribute (store) the cell when the cell arrives. Often, a method of randomly selecting or alternately selecting one of two input queues is considered. Since the queuing delay experienced by the two input queues is different, the cell order of cells switched to the output terminal is different from the cell order arriving at the input terminal. The order may be reversed. In particular, when the transmission order must be guaranteed, such as ATM, a pure 2Q2P switch structure cannot be used, and a scheme for guaranteeing the transmission order must be added.

In the case of multiple switching paths between a pair of input / output terminals such as a 2Q2P switch, two methods are generally proposed to guarantee the transmission order. Firstly, the timestamp method that selects randomly or alternately at the input and puts a cell sequencer for restoring the transmission order at the output, and secondly, specifies the input queue to be stored for each virtual channel. Static routing or fixed path routing. The method of placing the cell order recoverer at the output stage has a problem that the implementation is very complicated and an additional delay occurs to recover the cell order. In addition, the fixed routing method can guarantee the transmission order simply by adding the input queue field to the virtual path identifier / virtual channel identifier table, but it is fixed regardless of the dynamic traffic pattern and network load change. Because the arrival cell is stored in the input queue, the resources in the switch cannot be used efficiently, and the cell loss is large in the case of a large queuing delay in the input queue and a finite buffer.

Here, a time stamp method and a fixed allocation method, which are conventional methods for guaranteeing cell transmission order in a packet switch having a plurality of switching paths, will be described in detail.

3 illustrates a timestamp method which is a cell order recovery method using a cell order recoverer. When the cell arrives at the input terminal 110, the input controller 112 attaches a timestamp recording the current time (arrival time) to the arrival cell and alternately or randomly alternates the two input queues 114, one of the two switching paths. To distribute. Since the two input queues 114 experience different queuing delays, when they arrive at the output terminal 120, the arrival times are different and thus the transmission order may be reversed. When the cell enters the output terminal 120, the cell order restorer 122 calculates the age of the arrival cell using the time stamp attached to the cell, removes the time stamp, and restores the cell and the age of the cell. It is stored in a resequencing buffer (RSQ_BUFF) 122. At this time, the age is calculated as 'current time-timestamp', which means the queuing delay time D _{in the} input queue 114. The age of the cells stored in the sequential restoration buffer (RSQ_BUFF) 122 is increased by 1 for every slot and is transmitted to the output queue 124 when the maximum delay time D _max is reached. The cell sequence restorer 122 checks the age of the cells stored in the sequence restoration buffer (RSQ_BUFF) for each slot, so that (1) the age value is the largest and (2) the age exceeds the maximum queuing delay time D _max . Is transmitted to the output queue 124. In this case, since the output queue 124 is doubled up, the cell sequence restorer 122 may transfer two cells per slot to the output queue 124. As described above, the time stamp method intentionally delays the cell arriving at the output terminal by the difference between the maximum delay time and the queuing delay time in the sequential restoration buffer RSQ_BUFF, that is, D _max -D _in time, and then transfers the cell to the output queue 124. It is the concept that the time required for all cells to reach the output queue after arriving at the input terminal is equal to D _max , thereby maintaining the transmission order. 3 shows an example of a timestamp method when D _max = 12. The first arrival cell experienced a large queuing delay of D _in = 9 _{in the} lower queue, but the first cell outputs first by deliberately delaying the second cell arriving at the output stage for 7 slots (D _max -D _in = 12-5 = 7). It can be seen that it is sent to the queue 124 and stored in the output queue in the order of arrival at the input.

The fixed routing method shown in FIG. 4 stores the cells of the virtual channel along with the virtual path identifier (VPI) value and the virtual channel identifier (VCI) value in each virtual channel at the time of call setup as illustrated in the lookup table 150. By explicitly specifying the input queue, all cells belonging to the virtual channel are switched along the same switching path in the switch, thus ensuring a natural transmission order. However, regardless of the dynamic situation of the traffic, it follows a fixed switching path and thus cannot effectively use resources in the switch and share input queues effectively. Therefore, the queuing delay is large in the input queue, and the cell loss rate is large when the buffer is finite.

However, the above two methods have the following problems. First, since the timestamp method is a method of distributing the arrival cells in two switching paths without any control at the input terminal and restoring the transmission order of the cell sequence restorer at the output stage, the cell sequence restorer is required at all output terminals. A long time stamp needs to be attached to the arrival cell at the input and the cell sequence restorer has to be placed at the output. That is, the cell order restorer must search the timestamps of all the cells in the order restoration buffer (RSQ_BUFF) every slot to find the cell with the largest queuing delay, so the link transfer rate can be extended to Gigabit / sec. If the size of the sequence restoration buffer RSQ_BUFF is increased, the implementation becomes difficult. In addition, since the cell arriving at the input stage undergoes a queuing delay of the size of D _max until the output queue is reached, a large queuing delay occurs even under a small switch load. The biggest problem is that cell loss may occur in the sequence restoration buffer RSQ_BUFF and the probability that the cell order is reversed may depend on the size of the sequence restoration buffer RSQ_BUFF and the D _max value. Therefore, to apply the timestamp method to the switch, the size of the sequential restoration buffer (RSQ_BUFF) that satisfies the allowable queuing delay, allowable cell loss rate and allowable out-of-sequence for various traffic patterns and loads The value of D _max should be set. However, analysis of the timestamp method in the 2Q2P switch structure has not been presented yet.

In the fixed routing method, all cells belonging to one virtual channel have the same switching path in the switch, that is, 'high input queue 134a-> high plane 140a' or 'low input queue 134b'-> low plane 140b. The switching order is completely guaranteed since switching is done along the same path as. However, since the switching path is fixed regardless of the dynamic situation of traffic, the dual switching planes 140a and 140b are not effectively used and the two input queues 134a and 134b are not effectively shared. In particular, when traffic is bursted, there is a high probability that cells of one burst occupy within one input terminal 130. Since the cells forming the burst are all stored in one input queue, one slot in one of these slots is used. Only the cells of the can be delivered to the output terminal loses the meaning of the duplication of the input queue 130 and the switching plane (140a, 140b). Therefore, the queuing delay is large in the input queue, and the cell loss rate is large when the buffer is finite.

In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a cell distribution and arbitration scheme that ensures transmission order in a 2Q2P switch and has excellent queuing delay characteristics in a burst traffic environment.

Fig. 1 shows the structure of a conventional ATM switch (1Q2P switch) having one input queue per input port and having a double switching plane.

Fig. 2 shows the structure of another conventional ATM switch (2Q2P switch) having two input queues per input port and having a double switching plane.

3 is a conceptual diagram illustrating a cell order guarantee method according to a conventional time stamp method.

4 is a conceptual diagram illustrating a cell order guarantee method according to a conventional fixed routing method.

5 is a conceptual diagram illustrating a management method for distribution and arbitration of an input queue according to the present invention.

6 is a conceptual diagram illustrating a tag operation of an ATM cell according to the present invention.

7 shows a burst traffic model used in the simulation for performance analysis of the present invention.

8 is a graph showing a queuing delay time characteristic according to an input load in a 1Q2P switch.

FIG. 9 is a graph showing a queuing delay time characteristic according to an input load when a time stamp method is applied to a 2Q2P switch.

FIG. 10 is a graph showing an out-of-sequence rate characteristic according to an input load in a time stamp method.

FIG. 11 is a graph illustrating a characteristic of a queuing delay time according to an input load when a static routing scheme is applied to a 2Q2P switch.

12 is a graph showing the characteristics of the queuing delay time according to the input load when the CICO method of the present invention is applied to a 2Q2P switch.

13 is a graph illustrating a comparison characteristic of a queuing delay time in an input queue according to an input load.

14 is a graph showing a comparison characteristic of the total queuing delay time according to the input load.

15 is a graph illustrating a comparison characteristic of queuing delay time at an input terminal according to burst size.

16 is a graph showing the comparison characteristics of the queuing delay time in the system according to the burst size.

FIG. 17 is a graph illustrating a difference in queuing delay performance when there is no b _i constraint and the CICO method of the present invention according to an input load.

FIG. 18 is a graph showing a difference in queuing delay performance when there is no b _i constraint and the CICO method of the present invention with respect to the burst size.

19 is a graph showing the comparison characteristics of the cell loss rate according to the input load when l = 8.

<Description of the symbols for the main parts of the drawings>

200: input queue selector 210: dual input queue

220: dual switching plane 230: output stage controller

240: output queue

In order to achieve the above object, a switching plane that provides a transmission path to the output terminal of the asynchronous transfer mode (ATM) cell that arrived at the input terminal is composed of a double, the input and output ports of the dual switching plane has at least one input port and output port In the asynchronous transfer mode (ATM) switch is provided, each input port includes a first and a second input queue connected one-to-one with each of the dual switching plane, each output port comprises a single output queue,

A first step of alternately distributing the asynchronous transmission mode (ATM) cells arriving at each input port to the two input queues,

In each transmission period, a second step of determining whether transmission to the selected output port is possible by granting transmission opportunities to both head cells of the two input queues of the selected input port in the order of arrival;

And a third step of transmitting the first cell determined to be transmittable through the dual switching plane to the selected output port to ensure that the original cell transmission order is maintained. An input queue management method of an (ATM) switch is provided.

The alternate distribution of arrival cells for the two input queues of the first step includes a first pointer a _i that alternatively points to the two input queues for each input port, and the value of the first pointer a _i . Can be achieved by alternately enabling the two input queues alternately.

The alternate transmission opportunity is given to the two leading cells of each input port of the second step by using a second pointer b _{i that} is assigned to each input port and indicates an input queue in which the first arrived cell is stored. Whenever a transmission-selected cell is generated, the value of the second pointer b _i is alternately changed.

Further, the third step uses a tag value to distinguish the transmission order between two cells to be transmitted to the same output port during the same transmission period in the same input port, the tag value is the asynchronous transmission mode cell is the switching plane It is added to the asynchronous transmission mode cell at the stage before it arrives, and is removed by the output stage controller at the stage before it is applied to the output port leaving the switching plane.

On the other hand, as another aspect of the present invention, in the switching device provided with a plurality of input queues, a plurality of output queues and multiple switching planes, multiple input queues configured in multiple and connected one-to-one to each plane of the multiple switching planes ; An input queue selector connected to a front end of the multiple input queue and sequentially distributing cells arriving at the multiple input queue to each sub input queue of the multiple input queue; Connected between the multi-input queue and the multi-switching plane, and each sub-input queue is serviced in the order of distribution within one cycle to correspond to the order of distribution to the head cell when the head cell of the sub-input queue is transmittable. A transmission arbiter attaching a tag; And an output stage controller connected between the multiple switching planes and the output queue and sorting according to the tag information when the cell arrived at the output queue is a cell transmitted from the same input queue. There is provided a switching device in which a transmission sequence characterized by the features is guaranteed.

As can be seen from the above, the core of the cell distribution and arbitration scheme proposed by the present invention is to alternately store cells arriving at each input stage in two input queues and transfer the cells alternately from the two input stages to the output stage. It does not change. By alternately distributing input queues for each virtual channel, cells with the same destination (also belonging to the same virtual channel) are distributed to two queues, so that the queuing delay is small in the input queue, and two input queues are virtually preempted. Cell loss is also excellent because it is shared like a FIFO queue. The proposed structure requires two pointers at each input stage and one comparator at the output stage. The pointers at the input stage have states of '0' and '1' and the comparator at the output stage compares '0' and '1'. The implementation is very simple. In addition, since the arrival cells are distributed to two input queues in units of cells, cells having the same destination are distributed to the two queues, so that the effect of input expansion can be obtained, and thus the queuing delay characteristic is almost the same as that of the output buffering switch.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

First, referring to FIGS. 5 and 6, an input queue management scheme that guarantees cell transmission order in a 2Q2P switch structure will be described. The core of the proposed scheme is to store the cells arriving at each input in the two input queues 210a and 210b alternately and transfer the cells from the two inputs to the outputs 230 and 240 so that the transmission order is not changed at the input. will be. In other words, the two input queues act as one FIFO queue. This method is referred to herein as the 'cyclic input-cyclic output' (CICO) method.

As shown in FIG. 5, two input cues 210, that is, an upper cue 210a and a lower cue 210b are present at each input terminal, and each input cue is directly connected to the corresponding switching planes 220a and 220b. Each input queue 210a, 210b is managed by two pointers: a _i , b _i (where i is an input terminal number having the values i = 1, ..., N) and the selected cells are transmitted to the switching plane ( A tag with a value of 'H' or 'L' is attached before being passed to 220).

The order of transmission in the switch is ensured by the operation of the input queue selector 200, the transmission arbiter (not shown) including the switching planes 220a, 220b and the output stage controller 230. An input queue selector 200 pointers a _i to store alternately, as indicated by the dotted line the destination cell in the two input queue 5 in (210a, 210b) use, and transmits arbiter using a pointer b _i two input queue ( The cells stored in 210a and 210b are also serviced in a dotted line order. The operation of these two pointers a _i and b _i prevents cells arriving late at the input from being sent to the output first. The output stage controller 230 distinguishes the transmission order between the two cells when two cells are simultaneously transmitted from one input terminal to one output terminal. Before describing the algorithm, first define pointers a _i , b _i and a tag:

<Definition of Input Pointer and Tag>

A) a _i : A pointer indicating whether to store the cell arriving at the input terminal i in the upper input queue 210a or the lower input queue 210b.

B) b _i : Pointer to the input queue with the first cell among the cells stored in input i.

C) Tag: 1-bit information attached to a cell selected for transmission to give priority to transmission between two cells when two cells are simultaneously transmitted to the same output terminal at one input terminal.

Here, a _i and b _i have a value of '0' or '1', and if this pointer value is '0', the upper input queue 210a is indicated, and if the pointer is '1', the lower input queue 210b is indicated. Initially all pointers a _i and b _i have the value '0'. The tag value has a value of 'H' and 'L' and is attached before being transferred to a switching fabric, eg, a switching plane 220, such as a crossbar switch, and the output stage controller 230 removes it.

The operation of the proposed method will be described in detail in the order of the input queue selector 210, the arbitration process, and the output stage controller 230.

First, the operation of the input terminal controller will be described. The input stage controller is composed of input queue selectors 200 corresponding to the number of input stages. The input queue selector 200 of each input stage alternately distributes the arrival cells to two input queues, that is, the upper input queue 210a and the lower input queue 210b. Each input queue selector 200 is used to store the destination cell in the input queue is a _i indicating, for example, by a _i = 0 is stored in the upper input queue (210a), and toggle a _i value, i.e., a _i = By setting it to 1 and distributing the next arrival cell to another input queue, that is, the lower input queue 210b in one cycle, it is repeatedly performed so that the arrival cells to the input terminal i are alternated to the two queues 210a and 210b in the order of arrival. Can be distributed.

Next, the mediation process is explained. When the total number of input ports of the input stage is N, arbitration for these N input ports may be performed by a round-robin method or a random-selection method or any other method. The arbitration method between input ports may be any way. If only proper arbitration is performed between the upper input queue and the lower input queue inside the input port, the transmission sequence is prevented from being mixed. The transmission arbitration to the output stage for each input port is done over two subrounds since it must be performed for the HOL cells of the two input queues.

The mediation process at input i is In the first subround, if there is a cell waiting to be transmitted at the HOL position of the input queue pointed to by pointer b _i and the corresponding destination output of that cell is not preempted by another input, the cell is selected for transmission. If the destination output is preempted by another input, the cell cannot be transmitted and must wait until the next transmission arbitration opportunity is given. If there is a cell selected for transmission, toggle the pointer b _i at the end of the first subround and set the tag value of the cell selected for transmission to 'H'. The same process is repeated for the second subround. Accordingly, although the head cells of the upper and lower input queues may both be transmitted to the output terminal through two sub-rounds during one transmission period, only one leading cell may be transmitted or some head cell depending on the circumstances of the output terminal. May not be transmitted. On the other hand, the difference between the second subround and the first subround is that 1) the pointer b _i value is changed when the cell of the input i is selected in the first subround, and 2) the tag value of the transmitted selected cell is set to 'L'. Is the point. The tag operation related to this will be described later. Only the input queue pointed to by pointer b _i is served, and after service, the pointer b _i value is toggled to give another input queue a chance to transmit, so that the cells stored at the input are served in the order of arrival.

Finally, the operation of the output stage controller 230 will be described. The output stage controller 230 stores two cells in the output queue 240 when a maximum of two cells enter the two switching planes 220a and 220b at the same time. At this time, if two cells transmitted simultaneously are cells transmitted from different input terminals, there is no problem in putting any cell into the output queue first. However, in the case of a cell transmitted from the same input terminal, it is necessary to guarantee the transmission order between the two cells. In particular, when traffic is burst, there is a high probability that the destinations of the HOL cells of two input queues 210a and 210b of the same input terminal are the same. The reason for the guarantee of the transmission order between the two leading cells is that the number of cells transmitted in each transmission period is any one of 0 to 2, so that the cell selected for transmission in the first subround was always stored in the upper input queue. This is because it cannot be regarded as a leading cell.

An example of this is shown in FIG. 6. In this case, the cell j ₁ is selected as the j th output terminal in the first subround and the pointer b _i is updated to '1', so the j j output terminal j ₂ is selected in the second subround. Will be. Tag information is used for this purpose. Due to the constant input stage arbitration operation, the tag values of two cells transmitted from the same input stage in the same slot are always set to 'H' and 'L' to be different from each other. In this case, the cell with the tag value 'H' is the cell selected in the first subround, and the cell with the tag value 'L' is the cell selected in the second subround.

Therefore, the output terminal controller 230 may distinguish the order of the two cells by using the tag value. Since the cell with the tag value 'H' always arrives first, the output arbiter 230 first stores the cell in the output queue 240. The output stage arbiter 230 determines the first arrived cell using the tag value, and then removes the tag before inserting the cells into the output queue 240.

As mentioned above, transmission order guarantee at the input terminal is performed by using two pointers a _i and b _i . When two cells are simultaneously transmitted to the same output terminal at one input terminal, the transmission order classification between two cells is performed by using the tag value. do. In the proposed method, two pointers (each storing 1 bit of information) are required at each input, and a 1 bit tag is mounted before being transmitted to the switching plane. It is suitable for high speed switch implementation because pointer operation and tag operation are very simple.

So far, as a method of operating a 2Q2P switch to guarantee the transmission order, as a representative example of the prior art, the timestamp method, the fixed routing method, and the CICO method proposed by the present invention have been described. In the following, we compare and analyze the performance of the above three methods through the simulation in a clustered traffic environment. The queuing delay time and the cell loss rate in the input queue were used as the performance evaluation factors. The assumptions used in the simulation are as follows.

A) Assumption-1: The switch size N shall be 16.

B) Assumption-2: The aggregated traffic model uses the uniform geometric burst model shown in FIG.

C) Assumption-3: The destination output of each cell in one contiguous cell group is the same.

D) Assumption-4: The destinations of each group of distributed cells are evenly distributed across the N outputs.

ㅁ) Assumption-5: In order to experiment with the performance of the fixed routing method, when generating a group of cell groups from a signal source, an arbitrary input queue of an upper input queue or a lower input queue is allocated to each group of collected cell groups.

Based on the above assumptions, we first compare and analyze the characteristics of the queuing delay time.

8, 9, 11, and 12 illustrate a queuing delay, a timestamp method, a fixed routing method, and a CICO method proposed by the present invention when the average burst size l is 8 (l = 8) according to an input load. The characteristics of the queuing delay time of the applied 2Q2P switch are shown in a graph. The queuing delay curve of the output buffering switch showing the ideal performance in terms of queuing delay is also shown for comparison.

In FIG. 8, when the input load exceeds 0.85, the queuing delay time in the input queue is not limited to a finite value because the 1Q2P switch has a limited throughput.

9 shows the queuing delay time according to the input load when the cell restoration recoverer 122 has the size of the order restoration buffer (RSQ_BUFF) is 128 and D _max is 40 and 60. FIG. It can be seen that the delay in the sequential restoration buffer RSQ_BUFF occupies most of the queuing delay in the switch when the input load is small. That is, since most of the cells are delivered from the input queue to the output stage almost immediately, the cell order recoverer 122 has to wait until the age reaches D _max in order to guarantee the cell order. As the load increases, the queuing increases in the output queue 124 and the total queuing delay is shifted up by D _max in this output queue. Therefore, the total queuing delay time is increased by about 20 slots than the case where D _max is 60 is 40. In other words, as the value of D _max increases, the total queuing delay in the switch increases by that amount.

Therefore, in order to reduce the queuing delay in the switch, the D _max value should be set small. However, if the D _max value is small, the cell order may be changed even if the cell order restorer 122 is provided. If the arrival cell has a queuing delay of more than D _max in the input queue 110, it is likely that this cell will be sent to the output queue 124 later than the cell arriving later. In other words, when a cell arrives later, it reaches the output queue 124 when the age reaches D _max in the cell order restorer 122, but the cell that arrived first does not reach the output terminal until this time, so that the cell order is reversed between the two cells. Will change. The exit rate sequence (out-of-sequence rate) in the case As shown in Figure 10 the D _max of 40 greater than that in the case where the D _max of 60. If D _max is small, there is a high probability that queuing delay is greater than D _max in the input queue, so the cell order is more likely to be reversed. Therefore, in order to reduce the sequence departure rate, the value of D _max must be large. That is, D _max must be determined within the allowable total queuing delay and the allowable sequence departure rate in the switch. To the mothamyeo cell sequence restoring method using a time stamp is haejuji ensure complete cell sequence probability change the cell order small but always present, and the switch structure, the size, the buffer (RSQ_BUFF) size for the D _max value and the order recovery according to traffic patterns There is no clear solution yet. This method of placing a cell order recoverer is not only complicated to implement, but also has a fundamental problem in setting D _max to obtain stable performance.

In the fixed routing method of FIG. 11, the queuing delay is smaller than that of the 1Q2P switch or the timestamp method, but there is still considerable queuing at the input queue, and this component leads to the total queuing delay. . In the fixed routing method, cells belonging to a contiguous cell group (burst) of one virtual channel are fixedly stored in one input queue, that is, an input queue designated at call setup, so that only one HOL cell among these cells can participate in transmission contention. . That is, when k cells of a burst belonging to one virtual channel are queued at one input terminal, at least k slots are required for all these cells to be serviced. As a result, the dual switching path is not fully utilized, which increases the queuing delay in the input queue.

On the other hand, in the CICO method according to the present invention, since cells of one burst are distributed to two input queues in the order of arrival, two cells belonging to one burst can participate in transmission contention. That is, the k cells mentioned above can all be serviced at least k / 2 slots. This reduces the queuing delay in the input queue as shown in FIG. 12 and thus also reduces the total queuing delay. As shown in FIGS. 13 and 14, the queuing delay time in the input queue according to the input load and the total queuing delay time according to the input load are the smallest when the CICO method according to the present invention is applied, and in particular, the total queuing delay time is the output buffering scheme. You can see that it is almost the same as.

15 and 16 show the queuing delay and the total queuing delay at the input stage according to the burst size l when the input load is 0.85. In each case, as the burst size increases, the queuing delay characteristic decreases. However, in the case of the fixed allocation method, when the burst size l increases from 1 to 8 and 32, the queuing delay increases rapidly in the input queue to 20.3 and 96.0, respectively, but in the CICO method, the queuing delay increases slowly to 4.29 and 19.3. can see. In the fixed allocation method, as traffic is aggregated, that is, as the burst size increases, the probability that there is only one burst in one input stage increases, so that the queuing delay in the input queue increases. However, the CICO method according to the present invention does not significantly increase the queuing delay in the input queue since two cells belonging to one burst in one input queue can still be transmitted in the same slot even if the burst size is increased. That is, it can be seen that the CICO method according to the present invention is excellent in coping with burst traffic.

Next, we look at the results of analyzing the performance degradation caused by the virtual HOL blocking phenomenon of the CICO method.

There are two reasons to block transmission of HOL cell in the proposed CICO method. The first is when lost the output contention, and the second is the output current in the case does not have to be occupied by the head cell of the other input terminal is the HOL of the input pointed to by the pointer b _i queue block transfer does not participate in the contention virtual FIFO For example, a virtual HOL blocking phenomenon may occur in a queue. Here, transmission blocking due to output contention is an unavoidable phenomenon in the 2Q2P switch regardless of the CICO method. Therefore, to find out the performance degradation caused by the virtual HOL blocking phenomenon, the CICO method stores the arrival cells in two input queues alternately, and does not consider the pointer b _i when arbitrating the transmission cell, and the corresponding output stage is the head cell of the other input stage. We compare the performance with the scheme that allows transmission if it is not preempted by. In other words, the transmission order is not guaranteed, but the transmission is blocked only by output contention, so the 2Q2P switch exhibits optimal performance.

17 and 18 illustrate the queuing delay time according to the input load when the 2Q2P switch is managed in two ways. As shown in the figure, the performance difference between the two schemes is very small, and it can be seen that there is almost no degradation in performance of the 2Q2P switch due to the transmission constraint due to the operation of the pointer b _i in the CICO method of the present invention.

Finally, analyzing the cell loss rate gives the following results.

FIG. 19 shows the cell loss rate of the input queue according to the input load of the 1Q2P switch, the fixed routing method, and the 2Q2P switch to which the CICO method of the present invention is applied when the burst size l is 8 and the input buffer sizes B _in are 10 and 20. Is shown. For the 2Q2P switch, it is assumed that the input buffer size is the sum of the two input queue sizes and the output buffer is large enough. In the fixed routing method, the cell loss rate is the largest, and the cell loss rate of the 1Q2P switch and the CICO method's 2Q2P switch is less than that of the 1Q2P switch until the input load reaches 0.8 to 0.85. You can see less. In the case of the fixed routing method, the cells are distributed to the specified input queue regardless of the dynamic queuing behavior of the switch.The result is that the two input queues cannot be shared dynamically evenly.In the case of the CICO method, the input load is always distributed evenly between the two input queues. It has the same effect as sharing one FIFO queue, so the cell loss is small.

In the above, we proposed the transmission order guarantee scheme in the 2Q2P switch, which is easy to implement and brings high performance, and compared the performance with the existing schemes through simulation. The Cyclic-In-Cyclic-Out (CICO) scheme proposed in the present invention alternately stores cells arriving at each input stage in two input queues, and transfers the cells from the two input stages to the output stage alternately so that the transmission order is not changed at the input stage. . In other words, the two input queues act as one FIFO queue. In addition, when two cells having the same destination are transmitted at the same input terminal, the transmission order is guaranteed at the output terminal by using a 1-bit tag to distinguish the transmission order between the two cells.

The proposed CICO method is simple to implement because no time stamp is required, and the cells in one burst can be distributed to two input queues alternately so that two cells can be sent to the output stage simultaneously, reducing the queuing delay time in the input queue and also sharing the buffer. It has the advantage of excellent cell loss rate.

The 2Q2P switch adopting the CICO method provides high performance and guarantees the transmission order without using a timestamp, making it easy to implement, making it suitable for the implementation of a high-speed ATM switch or IP router with a Gbps transfer rate per port.

In addition, according to the analysis of the performance of the conventional method and the method according to the present invention, the proposed CICO method shows better performance than other methods in queuing delay characteristics and the total queuing delay time is almost the same as the output buffering switch. It also outperforms fixed routing in terms of cell loss rate. That is, the proposed CICO method is not only easy in terms of implementation but also excellent in terms of queuing delay and cell loss rate.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (5)

A plurality of switching planes providing a transmission path to an output terminal of an asynchronous transfer mode (ATM) cell arriving at an input end are composed of multiple, and at least one input port and an output port are provided at each input / output end of the multiple switching plane, and each input port In the asynchronous transfer mode (ATM) switch includes a multiple input queue connected to each one of the multiple switching planes one to one, each output port includes a single output queue, A first step of alternately distributing the asynchronous transmission mode (ATM) cells arriving at each input port to the multiple input queues, In each transmission period, a second step of determining whether transmission to the selected output port is possible by granting transmission opportunities to the head cells of the multiple input queues of the selected input port according to the arrival order; And a third step of transmitting the first cell determined to be transmittable through the multiple switching planes to the selected output port, thereby ensuring that the original cell transmission order is maintained intact. Input queue management method of (ATM) switch. 2. The method of claim 1, wherein the alternate distribution of arrival cells to the multiple input queues of the first step comprises a first pointer a _i that alternatively points to the multiple input queues for each input port, and the first pointer. and (a _i ) alternatingly changing the values of (a _i ) to enable the multiple input queues alternately. 2. The method of claim 1, wherein the granting of an alternative transmission opportunity to the multiple head cells of each input port of the second step comprises: a second pointer indicating an input queue in which the first arrived cell is stored; b _i) to the input of the asynchronous transfer mode (ATM) switches whenever the transmission selected cell having a plurality of switching planes for the value of the second pointer (b _i) wherein the formed written because changes alternately using How to manage queues. The method of claim 1, wherein the third step uses a tag value to distinguish the transmission order between the first cells to be transmitted from the same input port to the same output port during the same transmission period, and the tag value is the asynchronous transmission mode. A cell of the asynchronous transfer mode (ATM) switch having multiple switching planes, wherein the cell is added to the asynchronous transfer mode cell before it reaches the switching plane, and is removed at the stage before leaving the switching plane and being applied to the output port. How to manage input queues. In a switching device having a plurality of input queues, a plurality of output queues and a plurality of switching planes, A plurality of input queues configured to be multiple and connected one-to-one to each plane of the multiple switching planes; An input queue selector connected to a front end of the multiple input queue and sequentially distributing cells arriving at the multiple input queue to each sub input queue of the multiple input queue; Connected between the multi-input queue and the multi-switching plane, and each sub-input queue is serviced in the order of distribution within one cycle to correspond to the order of distribution to the head cell when the head cell of the sub-input queue is transmittable. A transmission arbiter attaching a tag; And And an output stage controller connected between the multiple switching planes and the output queue and sorting according to the tag information when the cell arrived at the output queue is a cell transmitted from the same input queue. Switching device with guaranteed transmission order.