KR20010001448A - A fabricating method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to make a cell region have the same electrical characteristic as that of a test pattern region, by patterning an arbitrary active region in the test pattern region. CONSTITUTION: A pad oxidation layer and a nitride layer are formed on a semiconductor substrate. A photoresist layer pattern is formed on the nitride layer, protecting a portion reserved to be an active region in a cell region of the semiconductor substrate, an active region where a unit transistor is to be formed in a test pattern region and a portion reserved to be a dummy active region adjacent to both sides of the active region where the unit transistor is to be formed. The nitride layer and pad oxidation layer are etched by using the photoresist layer pattern as an etching mask. The semiconductor substrate is etched by using the photoresist layer pattern as an etching mask, to form a trench in which a cell region and a test pattern region have the same degree of integration. The photoresist layer pattern is eliminated. The first sacrificial oxidation is performed regarding the surface of the trench. A thermal oxidation layer is formed on the trench. An insulating layer is formed on the entire surface, and is eliminated by a chemical mechanical polishing(CMP) process to form an isolation layer for filling the trench. The nitride layer is eliminated by a wet etch method. The second sacrificial oxidation is performed regarding the active region of the semiconductor substrate afterward.

Description

A fabricating method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of fabricating a semiconductor device in which a trench having a cell-like shape is formed in a test pattern region in a device isolation process using a trench. .

According to the recent trend toward higher integration of semiconductor devices, finer pattern formation is required, and the fine pattern formation technique is affected by the formation of a photoresist pattern serving as a mask. The photoresist pattern may not form a fine pattern below a certain degree due to many constraints such as the precision of an exposure apparatus, the wavelength of light, and the like.

For example, the process resolution of a reduced exposure apparatus using G-ray, i-ray and excimer lasers having light wavelengths of 436, 365 and 248 nm, respectively, is about 0.6 µm, 0.3 µm and 0.2 µm in size. The extent to which / space is formed is a limit, and in the case of a contact hole, it is formed larger than this.

In addition, a memory device having a unit cell composed of a capacitor and a transistor for storing charge should process a fine pattern of 0.35 μm or less in the case of 64M DRAM or more.

In addition, in order to test the manufacturing state of the unit cell formed as described above, a region for forming a test pattern is formed in portions other than the cell region.

The test pattern is formed in the same manner as the device formed in the cell region, but since the integration degree is lower than that of the cell region, a test pattern having different electrical characteristics from the device formed in the cell region may be formed.

FIG. 1A is a plan view of a test pattern region according to a method of manufacturing a semiconductor device according to the related art, showing an active region B and an isolation region A of a portion in which a unit transistor is to be formed in the test pattern region. 1B is an etched state diagram of the line xx 'cross-section of FIG. 1A, showing that the trench profile is not vertical as shown in FIG.

In the method of manufacturing a semiconductor device according to the prior art as described above, since the density of active regions of the cell region and the test pattern region is different when defining the device isolation region, the trench profile of the cell region is vertically formed after the trench etching process. However, since the trench profile on the test pattern region is formed to be inclined a lot, the electrical characteristics of the test pattern region may be estimated by measuring the electrical characteristics of the test pattern region because of the difference between the electrical characteristics of the test region and the cell characteristics. There is a difficult problem.

SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device in which the active region is the same as the cell region by patterning an arbitrary active region in the test pattern region during the device isolation process using a trench. There is a purpose.

1A is a plan view of a test pattern region by a method of manufacturing a semiconductor device according to the prior art.

Figure 1b is an etched state diagram of the cross-section line x-x 'of Figure 1a.

2 is a plan view of a cell region and a test pattern region according to the method of manufacturing a semiconductor device according to the first embodiment of the present invention;

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4 is an etched state diagram of the section II-II ′ of FIG. 2 in the method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention.

5A is a plan view of a test pattern region according to a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;

FIG. 5B is an etched state diagram of the section x-x 'of FIG. 5A. FIG.

<Description of reference numerals for the main parts of the drawings>

11 semiconductor substrate 13 pad oxide film

15 nitride film 17 photosensitive film pattern

19: trench 21: thermal oxide film

23: device isolation insulating film 25: gate insulating film

Ⅰ: Cell area Ⅱ: Test pattern area

A: device isolation area B: active area

C: dummy active area

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming a pad oxide film and a nitride film on the semiconductor substrate;

Protecting a portion of the semiconductor substrate in the cell region of the semiconductor substrate as an active region, and defining a dummy active region adjacent to both an active region in which a unit transistor is to be formed and an active region in which the unit transistor is to be formed in a test pattern region. Forming a photoresist pattern that protects a portion to be formed;

Etching the nitride film and the pad oxide film using the photoresist pattern as an etching mask;

Etching the semiconductor substrate using the photoresist pattern as an etch mask to form trenches in which a cell region and a test pattern region have the same density, and then removing the photoresist pattern;

Firstly producing the surface of the trench;

Forming a thermal oxide film on a surface of the trench;

Forming an insulating film on the entire surface of the structure and then removing the insulating film by a chemical mechanical polishing process to fill the trench;

Removing the nitride film by a wet etching method;

And producing a second rare production of the active region of the semiconductor substrate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view of a cell region and a test pattern region according to a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which an active region B is formed on the cell region at a predetermined interval, and a test pattern region The dummy active regions C are formed on both sides of the active region B in which the unit transistors are to be formed on the substrate.

3A through 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and illustrate a method of manufacturing a semiconductor device along the cross-sections taken along lines II ′ and II-II ′ of FIG. 2. Illustrated.

First, the pad oxide film 13 and the nitride film 15 are sequentially formed on the semiconductor substrate 11. The pad oxide film 13 is formed of a thermal oxide film of 30 to 300 kPa, and the nitride film 15 is formed to a thickness of 500 to 3000 kPa. (See Figure 3a)

Next, a photoresist pattern 17 is formed on the nitride layer 15 to expose the device isolation region. In this case, the photoresist pattern 17 protects the active region of the cell region I, and the dummy active region is formed at both of the active region where the unit transistors of the test pattern region II are to be formed and the active region where the unit transistors are to be formed. It is formed to protect the intended portion. The photoresist pattern 17 is formed in a shape as shown in FIG. 2. (See Figure 3b)

Next, the nitride layer 15 and the pad oxide layer 13 are removed by a dry etching method using the photoresist pattern 17 as an etching mask, and the semiconductor substrate 11 is dry-etched to form a trench having a depth of 1000 to 5000Å. (19) is formed and the photosensitive film pattern 17 is removed. (See Figure 3c)

Next, a first rare production process is performed to thermally oxidize the surface of the trench 19 at 900 to 1200 ° C. The first rare production process is to form a thermal oxide film of 50 ~ 300Å on the surface of the trench, and then again removed by a wet etching method to remove the thickness of the sidewall of the trench 19 100 ~ 300Å by the transient etching process Compensate for the surface of the trench 19 damaged during the trench etching process.

Then, the surface of the trench 19 is thermally oxidized at 900 to 1200 占 폚 to form a thermal oxide film 21 of 50 to 300 kPa. (See FIG. 3D)

Next, an insulating film is formed on the entire surface of the structure to fill the trench 19, and the insulating film is removed by chemical mechanical polishing (CMP) to remove the insulating film 23 embedded in the trench 19. ). (See Figure 3e)

Next, when the nitride film 15 is removed by a wet etching method, the pad oxide film 13 is exposed on the active region, and the device isolation layer 23 is exposed on the device isolation region. (See Figure 3f)

Next, the structure is thermally oxidized to form a thermally oxidized film (not shown) of 50 to 500 kV, followed by a second rare production process of removing the thermal oxidized film by wet etching.

Thereafter, an oxidation process of forming a gate insulating film 25 on the surface of the structure is performed. (See Fig. 3g)

4 is an etched state diagram of a cross-section II-II 'of the test pattern region of FIG. 2, wherein the dummy active region is formed 0.1 to 1.0 μm apart from the active region where the unit transistor is to be formed.

FIG. 5A is a plan view of a test pattern region according to a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 5B is an etching state diagram of a line xx 'section of FIG. 5A, and a profile of a trench in the test pattern region is It is shown to be formed close to the vertical. In this case, at least two dummy active regions in the test pattern region are repeatedly formed at a distance of 0.1 μm to 1.0 μm from the active region in which the unit transistors are to be formed.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the test pattern region is formed by forming a dummy active region around an active region in which a unit transistor to be formed in a test pattern region is formed in a device isolation process using a trench. By having the same density as the cell region, the profile of the trench formed in the cell region and the test pattern region is vertically formed during the trench etching process, and the electrical characteristics measured in the unit transistors of the test pattern region are monitored. It is possible to evaluate the electrical characteristics and thereby improve the characteristics and yield of the semiconductor device.

Claims (10)

Forming a pad oxide film and a nitride film on the semiconductor substrate; Protecting a portion of the semiconductor substrate in the cell region of the semiconductor substrate as an active region, and defining a dummy active region adjacent to both an active region in which a unit transistor is to be formed and an active region in which the unit transistor is to be formed in a test pattern region. Forming a photoresist pattern that protects a portion to be formed; Etching the nitride film and the pad oxide film using the photoresist pattern as an etching mask; Etching the semiconductor substrate using the photoresist pattern as an etch mask to form trenches in which a cell region and a test pattern region have the same density, and then removing the photoresist pattern; Firstly producing the surface of the trench; Forming a thermal oxide film on a surface of the trench; Forming an insulating film on the entire surface of the structure and then removing the insulating film by a chemical mechanical polishing process to fill the trench; Removing the nitride film by a wet etching method; And manufacturing a second rare production process of the active region of the semiconductor substrate. The method of claim 1, The pad oxide film is a method of manufacturing a semiconductor device, characterized in that the thermal oxidation film of 30 ~ 300Å. The method of claim 1, The nitride film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 500 ~ 3000Å. The method of claim 1, The dummy active region is a semiconductor device manufacturing method, characterized in that formed from 0.1 to 1.0㎛ spaced apart from the active region in which the unit transistor is to be formed. The method of claim 1, The dummy active region is a semiconductor device manufacturing method, characterized in that formed by repeating two or more spaced apart 0.1 ~ 1.0㎛ the active region in which the unit transistor is to be formed. The method of claim 1, The trench is a method of manufacturing a semiconductor device, characterized in that formed in a depth of 1000 ~ 5000Å. The method of claim 1, The first rare production process is to form a thermal oxide film of 50 ~ 300Å on the surface of the trench, and then removed by a wet etching method, but to remove the thickness of the trench sidewalls 100 ~ 300Å by the transient etching process. A method for manufacturing a semiconductor device. The method of claim 1, The thermal oxide film is a method for manufacturing a semiconductor device, characterized in that formed to a thickness of 50 ~ 300Å. The method of claim 1, The insulating film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 3000 ~ 8000Å. The method of claim 1, In the second rare production process, the surface of the semiconductor substrate is thermally oxidized by 50 to 500 kW to form a thermal oxide film, and then the thermal oxide film is removed by a wet etching method.