KR20000074630A - Semiconductor memory device architecture - Google Patents

Abstract

PURPOSE: A structure of a semiconductor memory device is provided which can reduce layout area of the device. CONSTITUTION: A structure of a semiconductor memory device reduces the layout area of a memory IC chip. The memory device includes: a plurality of banks(111,112,121,122) arranged in row and column and stored with data; row decoder groups(141,171) which correspond to the banks respectively and are arranged facing each other between two banks(111,121) on the same column; input/output buffer and peripheral circuits(151) which correspond to two column decoder groups respectively and are arranged between two column decoder groups and on the center of the memory device; and row predecoders(161) which correspond to two row decoder groups respectively and are arranged on one side of the input/output buffer and the peripheral circuits distant from the center of the memory device. According to the structure, the layout area does not affected by the increase of the number of data and address bits.

Description

Structure of Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE ARCHITECTURE}

The present invention relates to a structure of a semiconductor memory device, and more particularly, to a structure of a semiconductor memory device capable of reducing the layout area of a memory IC chip.

Recently, in order to achieve miniaturization and high integration of a memory device, an efficient layout design of the memory device has emerged as an important problem.

1 is a diagram illustrating a layout of a conventional memory device.

Referring to FIG. 1, the memory device includes four banks 11, 12, 21, and 22 arranged in rows and columns. The banks include memory cells arranged in rows and columns, respectively. The memory cells store data of logic '1' or logic '0'. A column decoder 31 is arranged between the bank 11 and the bank 12 on the same row, and a column decoder 32 is arranged between the bank 21 and the bank 22 on another same row. do.

Row decoder groups 41 and 71 are arranged face to face between the bank 11 and the bank 21 on the same column. A plurality of decoders are included in the row decoder groups. Row decoder groups 42 and 72 are also arranged face to face between the bank 12 and the bank 22 on the other same column. An input / output buffer and a peripheral circuit 51 and a row predecoder 61 are arranged between the row decoder groups 41 and 71 facing and arranged between the banks 11 and 21 on the same column. An input / output buffer and peripheral circuit 52 and a row predecoder 62 are arranged between the row decoder groups 42 and 72 that are arranged face to face between the banks 12 and 22 on the other same column. Here, the row predecoders 61 and 62 are positioned between the input / output buffer and the peripheral circuits 51 and 52, that is, the center C side of the memory device.

The data buses 83 and 84 between the input / output buffer and the peripheral circuits 51 and 52 are connected in a straight line via the row predecoders 61 and 62, respectively. The data buses 81 and 85 between the row predecoder 61 and the row decoder groups 41 and 71 are one side of the row predecoder 61 and the row decoder groups 41 and 71. Are connected to each other at the center (C) side of the memory device. The data buses 82 and 86 between the row predecoder 62 and the row decoder groups 42 and 72 are also one side of the row predecoder 62 and the row decoder groups 42 and 72, that is, the Are connected to each other at the center (C) side of the memory device.

Thus, the data buses 81, 82, 83, 84, 85, 86 are concentrated around the center C of the memory device. In particular, when the number of data output bits DQ increases because the data buses are concentrated at the center of the memory device, the row decoder groups 41, 42, 71, and 72 are connected to the row predecoders 61 and 62. The chip size is increased due to the increase in the address bus.

For example, in a 64M (2M × 32) SDRAM (Synchronous Dynamic Access Memory) device, if the address bus inputted from the row predecoder to the row decoder group is 24-bit per bank, the address bus connected to the row predecoder is 48-bit. Therefore, since the total distance between the buses connecting the row predecoder and the row decoder group is at least 80 μm to 100 μm or more, the width of the memory IC chip is increased by about 1.0 to 1.3%.

Accordingly, it is an object of the present invention to provide a structure of a semiconductor memory device capable of reducing the layout area of a semiconductor memory device, which has been proposed to solve the above-mentioned problems.

1 shows a layout of a conventional memory device; And

2 is a diagram illustrating a layout of a memory device according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

11, 12, 21, 22, 111, 112, 121, 122: bank

31, 32, 131, 132: column decoder

41, 42, 71, 72, 141, 142, 171, 172: row decoder group

61, 62, 161, 162: row predecoder

81, 82, 85, 86, 181, 182, 185, 186: address bus

83, 84, 183, 184: data bus

According to a feature of the invention for achieving the object of the invention as described above, a semiconductor memory device comprises: a plurality of banks arranged in rows and columns and storing data. Row decoder groups respectively corresponding to the banks are arranged face to face between two banks on the same column. Input / output buffers and peripheral circuits respectively corresponding to the two oppositely arranged row decoder groups are arranged between the two oppositely arranged row decoder groups and toward the center of the semiconductor memory device. Row predecoders corresponding to the two row decoder groups facing each other are arranged at one side of the input / output buffer and peripheral circuits far from the center of the semiconductor memory device.

In a preferred embodiment, a data bus is connected in a straight line between the input / output buffer and a peripheral circuit, and an address bus is connected to one side of the row predecoder far from the center of the memory device in which a few data buses exist. It is connected between the row decoder groups.

By such a device, it is possible to implement a semiconductor memory device in which the data bus and the address bus are not significantly affected by the chip size even if the number of data and address bits is increased.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a layout of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the memory device includes four banks 111, 112, 121, and 122 arranged in rows and columns. The banks include memory cells arranged in rows and columns, respectively. The memory cells store data of logic '1' or logic '0'. A column decoder 131 is arranged between the bank 111 and the bank 112 on the same row, and a column decoder 132 is arranged between the bank 121 and the bank 122 on another same row. do.

Row decoder groups 141 and 171 are arranged to face each other between the bank 111 and the bank 121 on the same column. A plurality of decoders are included in the row decoder groups. Row decoder groups 142 and 172 are also arranged face to face between the bank 112 and the bank 122 on the same column. An input / output buffer, a peripheral circuit 151, and a row predecoder 161 are arranged between the row decoder groups 141 and 171 arranged to face each other between the banks 111 and 121 on the same column. . The input / output buffer and the peripheral circuit 52 and the row predecoder 62 are also arranged between the row decoder groups 142 and 172 arranged to face each other between the banks 112 and 122 on the same column. Here, the row predecoder 161 corresponds to the row decoder groups 141 and 171, and the row predecoder 162 corresponds to the row decoder groups 142 and 172.

In the preferred embodiment of the present invention, the input / output buffer and the peripheral circuit 151 between the row decoder groups 141 and 171 are arranged to face the center C of the memory device, and the row decoder groups The input / output buffer and peripheral circuits 152 between 142 and 172 are also arranged to be centered toward the center C of the memory device. The row predecoders 161 may be formed on the opposite side of one side of the input / output buffer and peripheral circuits 151 and 152, respectively, close to the center C of the memory device. 151, 152 are arranged in line with each other.

Data buses 183 and 184 for transferring data between the input / output buffer and peripheral circuits 151 and 152 are connected in a straight line between the input / output buffer and peripheral circuits 151 and 152. The address pre-decoded by the row predecoder 161 is input to the row decoder group 141 through an address bus 181, and is input to the row decoder group 171 through an address bus 185. The address buses 181 and 185 are connected between one side of the row predecoder 161 and the row decoder groups 141 and 171 far from the center C of the memory device, respectively. Similarly, the predecoded address in the row predecoder 162 is input to the row decoder groups 142 and 172 via address buses 182 and 186. The address buses 182 and 186 are connected between one side of the row predecoder 162 and the row decoder groups 142 and 172 far from the center C of the memory device, respectively.

According to the present invention as described above, a data bus or an address bus is not centrally arranged between the row decoder groups 141, 142, 171, and 172 and the row predecoders 161 and 162, and the By being distributed in the center and borders, increasing the number of output bits does not have a significant effect on chip size.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, even if the number of data and address processing bits of the memory device increases, the data bus and the address bus do not significantly affect the chip size.

Claims (2)

In a semiconductor memory device: A plurality of banks arranged in rows and columns and storing data; Row decoder groups, each corresponding to the banks, arranged face to face between two banks on the same column; Input / output buffers and peripheral circuits, each corresponding to the two row decoder groups arranged facing each other, arranged between the two row decoder groups facing each other and arranged toward the center of the semiconductor memory device; And a row predecoder each corresponding to the two row decoder groups arranged facing each other and arranged on one side of the input / output buffer and peripheral circuits far from the center of the semiconductor memory device. Memory device. The method of claim 1, A data bus connected in a straight line between the input / output buffer and a peripheral circuit; And an address bus coupled between one side of the row predecoder and the row decoder group away from the center of the memory device.