KR20000074469A - Data driving circuit for color plasma display panel - Google Patents

Abstract

PURPOSE: A data driving circuit of a color plasma display panel(PDP) is provided which improves the margin of the color PDP. CONSTITUTION: A data driving circuit of a color plasma display panel(PDP) improves the margin of the color PDP by separating an input high voltage to be applied to each RGB electrode so that the high voltage output can be different high voltage output to the RGB electrode of the panel. The circuit improves the yield of the panel needed in a PDP set and improves the image quality of the PDP by reducing the mis-discharge of the panel by controlling the voltage differently according to the RGB electrode. The circuit comprises: a shift register part(100) comprising a plurality of shift registers(101-104); a latch part(110) latch-storing a plurality of data being output from the shift register part by a latch enable signal; a logic part(120) outputting the plurality of data stored in the latch part by the first and the second control signal; and a level shift and high voltage switching part(130) performing level-shifting of a plurality of output voltages of the logic part using the first, the second and the third high power voltage.

Description

Data driving circuit of color plasma display panel {DATA DRIVING CIRCUIT FOR COLOR PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving circuit of a color plasma display panel, and more particularly, in a data driving circuit of a color plasma display panel (hereinafter referred to as "color PD"), the high voltage output of the driving circuit is applied to the panel. The present invention relates to a data driving circuit of a color plasma display panel which improves a margin of a color PD by separating input high voltages so as to apply different high voltage outputs to the R, G, and B electrodes.

FIG. 1 is a block diagram illustrating a data driving circuit of a conventional color plasma display panel. As shown in FIG. 1, an input / output is determined by a direction command DIR, and data is supplied by a clock signal CLK applied to a clock terminal. A shift register section 10 composed of a plurality of shift registers 11 to 14 that receive (A1 to A4) (B1 to B4) and store them sequentially or output data to a cascade; A latch unit 20 for latching and storing the output signal of the shift register unit 10 by a latch enable signal LE; A logic unit 30 which receives data stored in the latch unit 20 by an applied control signal STB (SUS) and outputs the data; It is composed of a level shift and a high voltage switching unit 40 for receiving the output voltage of the logic unit 30 by a control signal (TSC) and level shifted to a high power voltage (HV) or a ground voltage according to its level. The level shift and high voltage switching unit 40 includes: a level shifter 41 which receives the output voltage of the logic unit 30 by the control signal TSC and level shifts the output voltage; And a plurality of high voltage output buffers B1 to Bm for buffering and outputting the output signal of the level shifter 41 using the high power voltage HV. The operation process according to the prior art configured as described above will be described in detail.

First, the shift register unit 10 determines the input / output direction of the data by the direction command DIR, and then multiplies the data of multiples of 4 bits or 3 inputted from the outside by the clock signal CLK applied to the clock terminal. A1 to A4) (B1 to B4) are inputted and stored sequentially or data is output to the cascade.

In addition, the latch unit 20 receives and stores all the data stored in the shift register unit 10 by the latch enable signal LE, and the data of the latch unit 20 is stored in the logic unit 30. The control signals STB and SUS are applied to the level shifter and the high voltage switching unit 40.

Accordingly, the level shifter 41 receiving the data stored in the latch unit 20 through the combination unit 30 is applied to the high power source according to the output data value of the latch unit 20 by a control signal TSC. The level shifting is performed using the voltage HV, and the plurality of high voltage output buffers B1 to Bm that receive the plurality of output signals output from the level shifter 41 are applied to the high power voltages. HV) is used to buffer and output it.

As described above, there is no problem in driving a single color PD with a conventional PD data driver, but in driving color PD consisting of three cells of ALGB (R, G, B) by applying the same voltage, there is a difference in the characteristics of ALGBI phosphors. And as the size and configuration of the Algibi cell is different, the difference in the driving voltage of each Algibi cell, there is a problem that the yield of the PDP panel and the mis-discharge caused the PDP image quality is lowered.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, by separating the input high voltage so that the high voltage output is different high voltage output to the Aljibi electrode of the panel so as to be applied to each of the Aljibi electrode by the color PD It is an object of the present invention to provide a data driving circuit of a color plasma display panel having improved margin.

1 is a block diagram showing the configuration of a data driving circuit of a conventional color plasma display panel.

2 is a block diagram showing a configuration of a data driving circuit of the color plasma display panel of the present invention.

3 is a block diagram illustrating a configuration of a level shift and high voltage switching unit in FIG. 2;

*** Description of the symbols for the main parts of the drawings ***

100: shift register section 101 to 104: shift register

110: latch portion 120: logic portion

130: level shift and high voltage switching unit

LS1 to LS _3n : Level shifter B1 to B _3n : High voltage output buffer

According to the configuration of the present invention for achieving the above object, a plurality of shifts for determining the input and output by the direction command, sequentially receiving the data by the clock signal applied to the clock stage, or outputting the data to the cascade A shift register section composed of registers; A latch unit configured to latch and store a plurality of data output from the shift register unit by a latch enable signal; A logic unit configured to output a plurality of data stored in the latch unit by first and second control signals applied; It is composed of a level shift and a high voltage switching unit for receiving a plurality of output voltages of the logic unit by an output control signal and level shifting the first, second and third high power voltages sequentially input according to their levels. It is characterized by.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

FIG. 2 is a block diagram showing the configuration of a data driving circuit of a color plasma display panel according to the present invention. As shown in FIG. 2, the input / output is determined by the direction command DIR and then the clock signal CLK is applied to the clock stage. A shift register section 100 composed of a plurality of shift registers 101 to 104 which receive data A1 to A4 (B1 to B4) and store them sequentially or output data to a cascade; A latch unit 110 for latching and storing an output signal of the shift register unit 100 by a latch enable signal LE; A logic unit 120 for logically combining the applied control signal STB (SUS) to output data stored in the latch unit 110; The 3n output voltages of the logic unit 120 are received by a control signal TSC and the first, second, and third high power voltages HVA, HVB, and HVC sequentially input according to their levels. A level shift and a high voltage switching unit 130 are output.

As shown in FIG. 3, the level shift and high voltage switching unit 130 receives a 3n-2th output signal of the logic unit 120 by the control signal TSC and according to its level. A plurality of level shifters LS1 to LS _3n-2 for level shifting and outputting the high power voltage HVA or the ground voltage; A plurality of high voltage output buffers B1 to B _{3n-2 which} receive output signals of the plurality of level shifters LS1 to LS _3n-2 and buffer the first high power voltage HVA and output the buffered signals; A plurality of level shifters which receive the 3n-1th output signal of the logic unit 120 by the control signal TSC and level shift the second high power voltage HVB or the ground voltage according to its level; LS2 to LS _3n-1 ); A plurality of high voltage output buffers B2 to B _{3n-1 for} receiving the output signals of the plurality of level shifters LS2 to LS _3n-1 and for buffering and outputting the second high power voltage HVB; A plurality of level shifters LS3 to receive the 3nth output signal of the logic unit 120 by the control signal TSC and level shift the third high power voltage HVC or the ground voltage according to its level. LS _3n ); The present invention constitutes a plurality of high voltage output buffers B3 to B _{3n for} receiving the output signals of the plurality of level shifters LS3 to LS _3N and buffering and outputting the third high power voltage HVC. The operation process according to this will be described in detail.

First, the plurality of shift registers 101 to 104 in the shift register unit 100 determine the input / output direction of data by the direction command DIR, and then are externally input by the clock signal CLK applied to the clock stage. The data A0 to A4 (B0 to B4) in multiples of 4 bits or 3 are input and stored sequentially, or data is output to the cascade.

In addition, the latch unit 110 receives and stores all the data stored in the shift register unit 100 by the latch enable signal LE, and the data of the latch unit 110 is stored in the logic unit 120. The level shift and the high voltage switching unit 130 are transferred to the level shift unit 130 by a combination of the control signals STB and SUS that are applied.

In addition, a plurality of level shifters in the level shift and high voltage switching unit 130 receiving data applied to the 3n-2nd, 3n-1st, and 3nth of the plurality of data output from the logic unit 120, respectively ( LS1 to LS _3n-2 ), LS2 to LS _3n-1 , and LS3 to LS _3n are respectively applied to the first, second, and third high power voltages HVA (controlled by the control signal TSC). Level shift output using HVB) (HVC).

And, the plurality of high-voltage output buffer (B1~B _3n-2) receiving the output signal of said plurality of level shifters (LS1~LS _3n-2) is the output buffers in a first high-power voltage (HVA), the a plurality of high-voltage output buffer (B2~B _3n-1) receiving the output signal of the plurality of level shifters (LS2~LS _3n-1) is the second, and output buffers in high-power voltage (HVB), wherein the plurality of levels a plurality of high voltage shifter output buffer _(3n B3~B) receiving the output signal of the _(3n LS3~LS), and outputs the buffered by the third high-power voltage (HVC).

Here, the color PD of the AlgiBi cells has a difference in the characteristics of each AlgiBi phosphor, and a difference occurs in the voltage for driving each of the cells of AlgiBi during the panel making process. The first, second, and third high power voltages HVA, HVB, and HVC are applied.

As described in detail above, the present invention improves the yield of panels required for PDP sets by using a data driver capable of applying a voltage suitable for the characteristics of the ALPH, and the voltage can be adjusted separately for each AL ratio. It is effective to improve the picture quality of PD by reducing mis-discharge lamps.

Claims (3)

A shift register unit comprising a plurality of shift registers which sequentially receive data by a clock signal applied to a clock stage after determining an input / output by a direction command, or output data to a cascade; A latch unit configured to latch and store a plurality of data output from the shift register unit by a latch enable signal; A logic unit configured to output a plurality of data stored in the latch unit by first and second control signals applied; It is composed of a level shift and a high voltage switching unit for receiving a plurality of output voltages of the logic unit by an output control signal and level shifting the first, second and third high power voltages sequentially input according to their levels. And a data driving circuit of the color plasma display panel. 2. The nth level control circuit of claim 1, wherein the level shift and high voltage switching unit receives 3n-2th output signals of a logic unit by a control signal, respectively, and outputs the level shifted to a first high power supply voltage or a ground voltage according to its level. Shifter; N high-voltage output buffers that receive the output signals of the plurality of level shifters and buffer the first high-power voltages and output them; N level shifters which receive the 3n-1 < th > output signals of the logic unit respectively by the control signal and level shift the second high power voltage or the ground voltage according to its level; N high voltage output buffers for receiving the output signals of the plurality of level shifters and buffering them with a second high power voltage; N level shifters which receive the 3nth output signal of the logic part by the control signal and level shift the third high power voltage or the ground voltage according to the level of the logic signal; And n high voltage output buffers for receiving the output signals of the plurality of level shifters and buffering and outputting the third high power voltages. 2. The data driving circuit of a color plasma display panel according to claim 1, wherein the number of output channels of the level shift and high voltage switching unit is configured to be a multiple of three so as to output a voltage suitable for the Algibi phosphor characteristic.