KR20000074123A - connecting unit for reliability test of semiconductor device test equipment and method for calibrating signal skew and jitter - Google Patents

Abstract

PURPOSE: A connection unit used for a reliability test of a semiconductor device test apparatus is provided to improve reliability regarding a package level test of the semiconductor device, by simply supplying a connection unit and by providing a signal skew and a jitter signal. CONSTITUTION: A connection unit used for a reliability test comprises an insulating pad(106), a plurality of input leads(102,108,112,116), a plurality of output leads(104,110,114,118) and low resistance connection lines(105,120,122,124). The plurality of input leads are separated a predetermined interval from each other to receive signals supplied from drivers in a semiconductor device test apparatus through output pins of the apparatus. The plurality of output leads output the supplied signals to comparators of the apparatus through input pins, disposed on the insulating pad while corresponding to the plurality of input leads. The low resistance connection lines connect the corresponding input and output leads.

Description

Connecting unit for reliability test of semiconductor device test equipment and method for calibrating signal skew and jitter}

The present invention relates to a structure of a connection unit that can verify the reliability of a semiconductor device test apparatus in order to improve the reliability of a package level test of a semiconductor device, and a signal skew and jitter measuring method for a reliability test of the test apparatus.

In general, package level tests for testing various characteristics of semiconductor devices such as semiconductor memory or non-memory products in a package state include DC parameter inspection and dynamic function inspection. Here, DC parameter inspection includes open and short circuit inspection, pin leakage current inspection, and current inspection, and dynamic function inspection includes device functional inspection. Unlike the wafer level test, the package level test is performed in a packaged state, and thus, various signals are inputted and outputted through pins protruding outside the package of the semiconductor device. The reliability of the package level test of such a semiconductor device depends on the accuracy of the semiconductor device test apparatus for testing various characteristics of the semiconductor device in a packaged state. It is a matter of course that the reliability of the device test result data will be improved if the test apparatus is always in a stable state and the resolution is excellent.

Therefore, when a process is to be managed by a semiconductor manufacturing manufacturer, in addition to setting process variables to be managed, tools for measuring the measurement and quantification of physical variations of the set variables are required. In a typical package level test, a source signal for testing is output from a driver in a semiconductor device test apparatus and applied to a pin of a semiconductor device to be tested after passing through a transmission line. The signal indicating the test result output from the semiconductor device is again input to a comparator in the test apparatus via another transmission line.

When a signal is transmitted through the transmission path, the signal is exposed to an internal and external defect environment. The noise causing the level change of the signal due to the defect environment is noise. Factors that cause noise during package level testing include conductive switching by data clock patterns, relays, ground bounce, crosstalk of transmission lines, reflections from impedance mismatches, electromagnetic interference, and environmental temperature and humidity. Etc. Influenced by the above factors, the test of the semiconductor device becomes unreliable when the driver and the comparator in the test apparatus do not operate stably and fall outside the error tolerance range. In other words, when the driver and the comparator in the test apparatus, which are inevitably affected by noise, cannot operate stably, the jitter phenomenon and signal delay as shown in FIG. 1 are not satisfied without satisfying the expected signal voltage level and delay time. It can be severe.

1 is a signal waveform diagram for explaining input and output signal skew and jitter in a conventional semiconductor device test apparatus. Referring to the drawings, when the horizontal axis is represented by time (t) and the vertical axis is represented by voltage (V), waveform A is an output waveform of the driver, and waveforms B1 and Bn are obtained from different comparators. It becomes an input waveform. Here, it can be seen that the overall signal time delay tPD varies the measured value every measurement due to the influence of jitter having the change width J1. The test result signal obtained when the test apparatus is severely affected by the jitter shows a large variation in measurement time, and the result is difficult to be trusted.

Of course, a method of using expensive measurement equipment such as a signal spectrum analyzer as a test apparatus is also known, but this is not preferable in terms of mass production of semiconductor products due to a decrease in test efficiency at the package level. It is difficult to repair. Therefore, a package level test of a semiconductor device has been conventionally performed using the test device, which is relatively inexpensive. In order to maintain the reliability of test data, verification of the reliability of the test device is frequently required. In order to determine the accuracy of such a test apparatus, it is important to detect the delay variation of the input / output signal. However, the driver and the comparator in a typical tester apparatus are disconnected in circuit, so that it is difficult to detect the delay variation. In addition, the real-time measurement of the test apparatus is difficult due to the structure and function of the test apparatus, and the signal measurement in the state in which the semiconductor device to be connected is connected is difficult to detect an abnormality of the tester itself.

As described above, in the related art, it is difficult to verify the accuracy of the semiconductor device test apparatus, and thus there are disadvantages in that the reliability of the test apparatus is lowered and the reliability of the package level test is lowered.

Accordingly, an object of the present invention is to provide a connection unit applied to the reliability test of the semiconductor device test apparatus in order to improve the reliability of the package level test of the semiconductor device.

Another object of the present invention is to provide a signal skew and jitter measuring method for a reliability test of a semiconductor device test apparatus.

According to the present invention for achieving the above objects and other objects, the structure of the connection unit applied to the reliability test of the semiconductor device test apparatus, the insulating pad; A plurality of input leads arranged at predetermined intervals on the insulating pad to receive signals from drivers in the semiconductor device test device, respectively, through the output pins of the device; A plurality of output leads disposed on the insulation pads corresponding to the plurality of input leads and outputting the provided signals to the comparators of the semiconductor device test device through the input pins of the device, respectively; And a low resistance connecting line for connecting the input / output leads corresponding to each other.

In addition, the signal skew and jitter measuring method for the reliability test of the semiconductor device test device, by connecting a connection unit that performs a function of shorting the comparison period with the driver in the semiconductor device test device, and measures the overall signal time delay by time Inputs of a plurality of comparators are also characterized by determining the range of signal skew and jitter by performing comparative analysis.

1 is a signal waveform diagram for explaining input and output signal skew and jitter in a conventional semiconductor device test apparatus.

Figure 2 is a schematic diagram showing a part of the structure of the conventional semiconductor device test apparatus and an arrangement structure showing the configuration of the connection unit according to an embodiment of the present invention together

3A is an equivalent circuit diagram when the connection unit of FIG. 2 is connected to a test apparatus.

3B is a waveform timing diagram appearing on each line of FIG. 3A.

4, 5, and 6 are diagrams for explaining the method and results for measuring signal skew and jitter using the connection unit.

In order to improve the reliability of the package level test of the semiconductor device according to the present invention, a connection unit used in the reliability test of the semiconductor device test apparatus, and a preferred embodiment of a signal skew and jitter measuring method for the reliability test is attached. This is explained in detail with reference to.

2 shows a schematic configuration showing a part of a conventional semiconductor device test apparatus and a structure showing a configuration of a connection unit according to an embodiment of the present invention. Referring to FIG. 2, the semiconductor device test apparatus 10 includes a driver 52 for outputting a source signal, a comparator 62 receiving a given signal, a board 60, a socket 57 for receiving pins, and a test pin. 55,56, and transmission lines 53,59. The connection unit 100 according to an embodiment of the present invention receives signals from the insulating pads 106 and the drivers 52 in the semiconductor device test apparatus 10 through the output pins 55 of the device, respectively. In order to correspond to the plurality of input leads (102, 108, 112, 116), the plurality of input leads (102, 108, 112, 116) arranged at predetermined intervals on the insulating pad 106, disposed on the insulating pad 106 and the provided signals are input pins A plurality of output leads 104, 110, 114, and 118, respectively outputting to the comparators 62 of the semiconductor device test apparatus 10 through the plurality of output lines, and a plurality of low resistance connection lines for connecting the input / output leads corresponding to each other ( 105,120,122,124. The molding protection layer 106 ′ may further include the plurality of input / output leads 102, 108, 112, 116, 104, 110, 114, and 118 and the low resistance connection lines 105, 120, 122, and 124. The structure of the connection unit 100 is preferably formed to correspond to the size of the package of the semiconductor device to be tested and the number of external pins, and the plurality of low resistance connection lines 105, 120, 122, 124 of the same length for data matching It is better to use gold-plated wire. Input and output leads that do not correspond to each other are not to be shorted, and the same leads are used. As a result, the connection unit 100 performs a function of directly shorting a path between the driver 52 and the comparator 62 of the test apparatus.

How to test the operation reliability of the test apparatus with the connection unit 100 will be described below. Referring to FIG. 3A, which shows an equivalent circuit when the connection unit 100 of FIG. 2 is connected to the test apparatus 10, the node A corresponds to the driver output node A of FIG. 2 and the node B is the comparator of FIG. 2. Corresponds to input node B. In the case where impedance matching is performed at, for example, 50 mV by the connection of the connection unit 10, the waveform of the node A appears as the waveform A of FIG. 3b according to the change of time. And, the waveform of the node B appears as waveform B of FIG. 3B with the change of time. Here, FIG. 3B is a waveform timing diagram which appears in each line of FIG. 3A. As a result, in FIG. 3B, the delay between the time t0 and the time t1 becomes the overall signal time delay tPD, and the time point at which the comparator 62 of the test apparatus 10 receives the signal becomes the time t1. Here, the reason why the level of the waveform A becomes 1/2 Vs from the time t0 until after the time t1 elapses is because the impedance is matched, and the level of the waveform B becomes Vs constitutes the input terminal of the comparator. This is because the operational amplifier has an infinite input impedance. Here, the impedance is matched to 50 kHz because the internal resistance R of the driver 52 is 50 kHz. If the case is different, the line resistance may be adjusted accordingly. Therefore, by connecting the connection unit 100 to the test apparatus 10, the overall signal time delay (tPD) is measured by time, and the comparison of the inputs of a plurality of comparators can also know the range of signal skew and jitter The accuracy of the test device is verified.

Hereinafter, the simulation results will be described with reference to FIGS. 4, 5 and 6. A method outline for measuring signal skew and jitter using the connection unit 100 as shown in FIG. 2 may be described with reference to FIG. 4. Referring to the drawings, the frequency rate is 15 nanoseconds (nS), the signal waveform is a square wave having a range of 5 nanoseconds to 10 nanoseconds, the strobing time is 3 to 8 nanoseconds, and the level of the signal voltage is 0 to 3 volts. The methodology and result data are shown for the case where the reference level of the comparator measurement level is 1.5 volts and the measurement pattern is read / checked every 100 cycles. Therefore, section T1 in FIG. 4 represents a strobing section. FIG. 5 illustrates a comparator pass / fail dot diagram, and illustrates a time point at which a signal provided from the driver 52 passes through the connection unit 100 and reaches the comparator 62. Here, the symbol K denotes the signal time delay tPD. 6 is a data output list showing the above measurement results as quantified numerical values. Here, the unit is nanoseconds, the data shown in the vertical column is for multiple comparators in the test apparatus, and the data shown in the horizontal column is for each trial in a given range.

Therefore, if the result data obtained in FIG. 6 is analyzed, the accuracy of each pair of drivers and comparators in the test apparatus can be determined to determine the reliability of the entire test apparatus.

As described above, the present invention has been described by way of example only with reference to the drawings, but is not limited thereto and various changes and modifications by those skilled in the art to which the present invention pertains without departing from the technical spirit of the invention. Of course this is possible.

As described above, according to the present invention, a package level of a semiconductor device is provided by simply providing a connection unit used for a reliability test of a semiconductor device test device and providing a signal skew and jitter measuring method for the reliability test of the semiconductor device test device. The reliability of the test is improved. In addition, since the test efficiency of the semiconductor device can be improved, cost reduction of mass-produced semiconductor products is expected.

Claims (3)

In the connection unit applied to the reliability test of the semiconductor device test apparatus: Insulating pads; A plurality of input leads arranged at predetermined intervals on the insulating pad to receive signals from drivers in the semiconductor device test device, respectively, through the output pins of the device; A plurality of output leads disposed on the insulating pads corresponding to the plurality of input leads and outputting the provided signals to the comparators of the semiconductor device test device through the input pins of the device, respectively; And And a low resistance connecting line for connecting the input / output leads corresponding to each other. The method of claim 1; The connection unit further comprises a molding protective layer for covering the plurality of input and output leads and the low resistance connection line. A signal skew and jitter measuring method for a reliability test of a semiconductor device test apparatus; By connecting the driver in the semiconductor device test apparatus with a connection unit that shortens the comparison period, the overall signal time delay is measured by time and the inputs of the plurality of comparators are also compared and analyzed to determine the range of signal skew and jitter. Determining.