KR20000066709A - Central process unit having multiple value by suppressing chaos - Google Patents

Abstract

PURPOSE: A chaos restraint multi-value CPU(Central Processing Unit) is provided to implement cells acquiring and using multi-value so that it can enhance a calculation power of a digital computer with smaller numbers of transistors. CONSTITUTION: A chaos restraint multi-value CPU comprises a plurality of chaos restraint multi-value cells(1,2,3,..m), a plurality of interfaces and a common bus(S). Each cell is a loop comprising a nonlinear AD converter, a nonlinear DA converter, and one dimensional chaos generation mapping circuit. The nonlinear AD converter dependently connected to the nonlinear DA converter and the DA converter perform a nonlinear quantizer. The output of the AD converter is a multi-value output of the multi-value cell. The chaos restraint multi-value cells(1,2,3,..m) are in parallel connected to the common bus via the interfaces. A nonlinear function generates a chaos multi-value when an output of the one dimensional mapping circuit is fed back to an input.

Description

CENTRAL PROCESS UNIT HAVING MULTIPLE VALUE BY SUPPRESSING CHAOS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (CPU) for acquiring multiple values (digital numbers) as a computational cell by introducing only one analog element into a digital circuit to improve the computing power of a digital computer.

The chaotic generation one-dimensional mapping circuit is an example of an analog element to be applied in the present invention. One-dimensional mapping circuits are realized by combining a function of increasing output for an input such as a CMOS source follower and a decreasing function of decreasing output for an input such as a CMOS inverter.

On the extension of the digital computer, there are directions to expect the development of next-generation computers and to look at computers based on completely new ideas, namely neuro computers, fuzzy computers and soft computers. The present invention belongs to the former.

Even if the development of digital computers has reached its limit, mankind cannot already give up its vast software assets on von Neumann sequential computers.

General purpose 32-bit CPUs, such as Intel's Pentium processor, are binary 32-bit machines. The device counts combinations up to 2 ≒ 4.3 × 10 at a time. Binary numbers are so small a division that you have to spend a lot of time rounding to perform numerical operations on them.

Accordingly, the present invention has been made to solve such a problem, and provides a central processing unit for acquiring multi-valued (binary) numbers as arithmetic cells by introducing only one analog element into a digital circuit to improve the computing power of a digital computer. The purpose is.

The present invention technically realizes that by introducing only one analog element into a digital circuit, it is possible to reduce the number of transistors of a central processing unit (CPU) that acquires multiple values (binary numbers) and serves as arithmetic cells.

Intel's Pentium processor, a representative 32-bit machine that supports today's computer technology, integrates 8 million MOS transistors on a single chip and consumes only 30 watts of power. This is called the limit of the integrated circuit.

Therefore, it is necessary to reduce the number of transistors per function. When the same function, for example, the function of calculating two combinations is realized in an integrated circuit, it is desirable to realize even a small number of transistors.

In some respects, it is pointed out that spending 8 million transistors to calculate only two combinations is a waste of industrial technology. In this regard, the present invention is meaningful.

1 is a conceptual diagram of a chaotic suppression multi-valued central processing unit.

Explanation of symbols on the main parts of the drawings

1, 2, 3, ... m ----- Chaos inhibiting multivalued cells

1 ¹ , 2 ¹ , 3 ¹ ... m ¹ ----- Connection to common bus 1

S ----- Common Bus

Hereinafter, an embodiment of the present invention will be described in detail.

One embodiment for solving the problem of the present invention is to increase the data processing division from binary (binary) to 8-bit 256 (256).

As a method of realizing multi-values (cells) as cells of an integrated circuit, a loop circuit composed of a chaotic generation one-dimensional mapping circuit and a nonlinear quantizer is adopted.

Nonlinear quantizers are the cascade of nonlinear analog-to-digital converters and nonlinear digital-to-analog converters.

The output of the analog / digital converter is the multivalued output of the multivalued cell. For example, an output of a nonlinear analog-to-digital converter with 8 bits of resolution would ideally have 2 = 256 quantum. When all quantum states are filled only once, 256 values can be obtained.

The quantum size of a nonlinear analog / digital converter is not as uniform as the quantum size of a linear analog / digital converter.

8-bit 256 digits is one-quarter of that given that the bus width of a general-purpose digital computer is 32 bits, which is good for introducing 256-bit 8-bit binary code into general-purpose computer memory. 6-bit 64- and 4-bit hexadecimal numbers can also be obtained, but the block size of the digital code to be split is as large as possible to handle operations using large radix.

A cell that acquires 8-bit 256 digits is a loop of one-dimensional mapping circuit, nonlinear 8-bit analog / digital converter, and nonlinear 8-bit digital / analog converter. Here, 8 bits is just an example.

The one-dimensional mapping circuit is an analog circuit in which input and output are commonly derived by connecting a CMOS source follower with increasing function and a CMOS inverter with decreasing function in parallel.

The CMOS inverter may be divided and an external bias may be applied to one side to adjust the nonlinear function.

Non-linear 8-bit analog-to-digital converters are analog-to-digital converters with a non-linear tendency, each of which tends to linearize the input / output transmission characteristics of the one-dimensional mapping circuit. As another method, the quantum size is divided so that the distribution of the internal states constituting the time series generated by the one-dimensional imaging circuit becomes uniform as a result.

The propensity of nonlinear analog-to-digital converters is the same as that of nonlinear digital-to-analog converters.

Analog-to-digital converters can be configured as sequential comparisons or sequential conversions. The propensity may be given as a resistance value, or may be given as a channel conductance of a MOS transistor constituting a CMOS inverter. The same is true for digital-to-analog converters.

The digital output of an 8-bit 256-degree acquisition cell is a nonlinear analog-to-digital converter output, and can be converted to 8-bit binary code by attaching a general-purpose logic circuit such as a decoder. You may add a transistor etc. to the input / output of a cell.

The nonlinear function is adjusted so that chaos occurs when the output of the one-dimensional mapping circuit of the multi-value acquisition cell is returned to the input. Therefore, it can be said that multi-value acquisition cells incorporating nonlinear quantizers suppress chaos and derive chaos order.

(Example)

1 illustrates a common burr in parallel with m-valued multivalued cells.

It is a conceptual diagram which shows the Example of the multi-value acquisition central processing unit connected via switch S. If the chaotic suppressed multivalue cells 1,2, ... m are 8-bit 256 hexadecimal cells and m = 256, the integer value that can be calculated at one time is (256) = 3.2 × 10. Compared to the general purpose 32-bit CPU calculating a combination of 2 = 4.3 × 10, it can be seen that the computational power is dramatically improved.

The characteristic of adopting a large base number, in the present embodiment, 256 digits, is that the arithmetic operation can be terminated with only one rounding.

The characteristics of the present embodiment will be described with reference to the main plate as an example. The general purpose 32-bit CPU is an abacus with 32 eggs moving up and down. The upper and lower sides correspond to "0" and "1" in binary. If you carry out the four or four arithmetic arithmetic operations, you will always be chased.

Decimal abacus used in Japan, China, etc. can be calculated up to 10 because 1 egg of 5 and 4 eggs of 1 are vertical and 24 digits in width. Compared to the binary abacus, the number of rounding treatments is relaxed, so that a large base can be calculated.

In the 256-decimal abacus of the embodiment of the present invention, there is an egg which can define the state of 256 in one vertical axis, and m = 256 digits in the horizontal. For calculations below 256 in each digit, no rounding takes place. In most cases, you need to perform the calculations for each digit in parallel, then sort them once to handle the rounding.

The application of the present invention would be ideal if, for example, a calculator could be used to calculate real numbers. Here, real numbers are represented by an infinite sequence of numbers. Infinity can't be realized by machines. A multi-valued CPU device with m-valued multi-valued cells arranged in parallel can calculate (n) at once. When n = 256 and m = 256 in the embodiment of the present invention, (256) = 3.2 × 10. Compared to 2 = 4.3 × 10, a general purpose 32-bit CPU can calculate a huge number.

Katakana and Hiragana, such as the alphabet and Aiueo, represent each character with 8 bits. Chaos suppression multi-value cells in 8-bit 256 digits not only improve the CPU's computational power, but also mean that information can be processed character by character. A multivalued CPU with m = 256 can process up to 256 characters at once.

Claims (1)

A chaotic suppression multivalued central processing unit, wherein a plurality of chaotic suppression multivalue cells comprising a chaos generating one-dimensional mapping circuit, a loop of a nonlinear analog / digital converter, and a nonlinear digital / analog converter are connected in parallel.