KR20000066448A - Tutbo Interleaver designing Method using PN Sequence - Google Patents

Abstract

PURPOSE: A design method and apparatus for turbo interleaver by using the random characteristics of a PN sequence is provided to maximize the performance with minimum memory. CONSTITUTION: Turbo codes are binary error-correcting codes built from the parallel concatenation of two recursive systematic convolutional codes and are used as a feedback decoder. A design method for a turbo interleaver in a cellular communication system using turbo codes comprises the steps of: assigning PN sequence code into the column bits and bit reversing of the row bits of the interleaver; assigning the initial index to the current column and generating the PN sequence corresponding to the current column length; and initializing the next column within the range of current PN sequence generation. The apparatus for the turbo interleaver comprises a counter(110), a bit reverse part(120), a linear feedback shift register(130), and a column initial index(100).

Description

Turbo Interleaver designing method using PN Sequence

The present invention relates to a next generation mobile communication, and more particularly, to a method of designing a turbo interleaver using random characteristics of a PN sequence in a next generation mobile communication system using a turbo code.

In general, turbo code has been intensively studied by many people who have recognized breakthrough performance since it was published by Berrou in 1993.

Turbo code performance using random interleavers with sizes of tens of thousands is known to be close to the Shannon limit. That is, it is known that the bit error rate (BER) is close to 10 ⁻⁵ at about 0.7 Hz for a 1/2 turbo code.

However, turbo codes using very large random interleavers have very high data rates and long delays, making them unsuitable for applications other than deep space communication.

As a result, efforts have been made to obtain the performance that can be obtained by using a conventionally complex channel code with a turbo code using an interleaver of several hundreds of sizes. The use of an interleaver enables voice transmission using turbo codes under mobile communication environments.

1 is a diagram illustrating a frame structure of a general turbo code.

The frame structure of the turbo code shown in FIG. 1 shows an example of a frame standard for a voice service of 8 kbps, and it is necessary to determine such a frame standard before designing the frame structure of the turbo code.

The illustrated frame is in 10 ms units and the actual data rate is 9.6 kbps.

Cyclic Redundancy Check (CRC) (4) is used for automatic retransmission request (ARQ) when transmitting information data (2) requiring a bit error rate (BER) of 10 ^-6 to a voice band. Inserted for use in error checking.

2 is a block diagram showing the structure of a typical turbo code coder.

There is an interleaver 10 having the same size as the input frame size (N bits) in the turbo code encoder, and two simple cyclic convolutional codes (20, 30) are connected in parallel to the turbo code encoder. Thus, a parity symbol is formed by using an input composed of N-bit frames.

Here, the interleaver 10 changes the order of the frames input to the second cyclic convolution encoder 30 and has the same size (N bits) as the size of the input frame.

Accordingly, the outputs y _1k and y _2k of the turbo code encoder are dual parity information due to not only the output y _1k of the first cyclic convolutional encoder 20 but also the output y _2k modified through the interleaver 10. Will have.

The structure of the turbo code encoder shown in FIG. 2 shows an example of alternately transmitting the outputs y _1k and y _2k of the respective cyclic convolutional encoders 20 and 30 so as to reduce the transmission rate to 1/2.

3 is a block diagram showing the structure of a typical turbo code decoder.

In general, a turbo code decoding technique includes a maximum post-Maximum a posteriori (hereinafter abbreviated as MAP) decoder (50, 70) or a soft-output Viterbi Algorithm (hereinafter referred to as SOVA) decoder. Original information) is restored.

Here, the SOVA decoder has a relatively low hardware complexity compared to the MAP decoder, but is poor in performance. For example, when the bit error rate (BER) is 10 ^-4 and the memory is 4, the MAP decoder performs about 0.7 dB better than the SOVA decoder.

3 is an example of a turbo code decoder using the MAP decoders 50 and 70 and has a structure in which iterative decoding is performed using the MAP decoders 50 and 70. The MAP decoders 50 and 70 perform repeated decoding. Exchange of additional information bits Z _k .

Here, the additional information bit (Z _k ) initially has a value of "0", but is replaced with a more accurate value as the decoding is repeated, so that the bit error rate (BER) is gradually improved as the number of repeated decoding increases. There is this.

By the way, the turbo code decoder itself includes the interleaver 60 and the deinterleaver 80, 90, so that the complexity is high.

The performance of the conventional turbo code encoder and decoder described so far varies depending on the size of the generated polynomial, the interleaving algorithm and the interleaver.

For example, MAP decoders 50 and 70 that output log-likelihood ratios require a lot of computation and memory, so use the E function as the generated polynomial to reduce computation and memory usage. Done. The E function is a generator polynomial used to find construct codes that perform well at a given constraint length.

Interleaving algorithms include block interleaving, diagonal interleaving, and random interleaving. Block interleaving and diagonal interleaving are relatively simple interleaving algorithms, and random interleaving provides the best performance for turbo code. The algorithm to represent.

However, when the input frame size is small, if the random interleaving algorithm is applied to the turbo code, it is not always possible to obtain good performance.

Therefore, the size of the interleaver should also be considered. In general, the larger the size of the interleaver at the same iterative decoding number, the better the bit error rate (BER) performance is. However, the complexity of the turbo code encoder or decoder should be taken into consideration, and considering the efficiency of the turbo code decoder as an example, the most suitable size of the interleaver is about 2048.

As such, the interleaver acts as an important factor in determining the performance of the turbo code encoder or decoder.

Therefore, when designing the turbo interleaver, it is necessary to consider bit error rate (BER), calculation amount, required memory, 'on the fly' function and 'reverse order' function.

In other words, since the MAP decoder or SOVA decoder used in the turbo code decoder requires a large amount of calculation, the MAP decoder or SOVA decoder should be designed in a direction that minimizes the calculation amount of the interleaving algorithm.

In addition, when a turbo code is encoded in a block of a large size, it has a relative gain with respect to the convolutional code. Therefore, encoding and decoding are performed in a block of a larger size. When specifying an interleaving address for such a block, It should be designed to use the least memory.

For reference, the 'On the fly' function outputs the address of the turbo interleaver in a predetermined clock unit so that encoding or decoding is performed within a predetermined clock. The 'reverse order' function is decoded by the MAP algorithm in the turbo code decoder. This is a function that allows calculation of state metric, which is calculated recursively when done, without requiring additional buffers.

Interleavers that meet the design requirements of these turbo interleavers include GF interleavers from Hughes Network Systems (HNC), LCS interleavers from Qualcomm, PN interleavers from Motorola, and MIL from NTT Docomo. Interleaver etc. are mentioned.

Each of these interleavers has relative advantages and disadvantages in terms of functionality. Table 1 shows the relative characteristics of the interleavers listed above.

Performance Calculation Memory 'on the fly' 'reverse order' HNS usually usually Inferior support support LCS Great usually usually support support Motorola usually usually Great support support MIL Great Inferior Inferior ? ?

In the design of the above-mentioned turbo interleavers, the above-mentioned relative features are combined. Therefore, the development of a turbo interleaver that provides better performance and function with minimum computation and memory in the future is required considering the relatively inferior aspect compared to other products. do.

Disclosure of Invention An object of the present invention is to provide a design method of a turbo interleaver capable of exhibiting maximum performance with minimum memory usage by using random characteristics of a PEN sequence.

A feature of the turbo interleaver design method using the PEN sequence according to the present invention for achieving the above object is that when designing one or more interleavers used in the turbo code decoder, the PEN sequence is randomly selected for each column. The interleaver of a predetermined size is designed in consideration of a generation polynomial for generating, an initial index of the generated PEN sequence, and an index increment for each column.

In addition, a feature of the turbo interleaver design method using the PEN sequence according to the present invention is a decoder using a turbo code, and having one or more interleavers, in which the bit is inverted for the row bits of the interleaver, Assigning a Pien sequence to the ten bits; Adding an initial index to the Pien sequence of the current column, and then generating a Pien sequence of the corresponding length; And generating an initialization of the next sequence of the next column of the corresponding length within the generation range of the current sequence of the current column.

Preferably, after the initialization step of the next generation of the next PIEN sequence, the next PIEN sequence of a predetermined length is generated sequentially, the initializing step of the next PIEN sequence generation, the initial index of the next column imposes a constant index increment on the initial index of the current column Is performed as is generated.

Here, the index increment necessary to generate the initial index of the next column is stored within the range of occurrences of the Pien sequence of the current column.

1 is a diagram illustrating a frame structure of a general turbo code.

2 is a block diagram showing the structure of a typical turbo code coder.

3 is a block diagram showing the structure of a typical turbo code decoder.

Figure 4 is a block diagram showing the structure of a turbo interleaver according to the present invention.

5 and 6 are graphs showing a performance comparison when using the turbo interleaver according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: column initial index

110: counter 120: bit reverse

130: Linear Feedback Shift Register (LFSR)

Hereinafter, a preferred embodiment of a turbo interleaver design method using a PEN sequence according to the present invention will be described with reference to the accompanying drawings.

Compared to the aforementioned Motorola PN interleaver, the present invention proposes a design method of a turbo interleaver that can exhibit better performance while maintaining memory use using a PEN sequence.

4 is a block diagram showing the structure of a turbo interleaver according to the present invention.

Referring to FIG. 4, the turbo interleaver of the present invention has a size of M * N. The size of the row M has a shape of 2 ^m and the size of the column N has a shape of 2 ⁿ −1.

When the sequential clock is input to the turbo interleaver from the initial clock 0 through the counter 110, these inputs are divided into upper bits of m bits and lower bits of n bits.

The upper m bits are bit reversed in the bit inversion 120, and the Linear Feedback Shift Register (hereinafter abbreviated as LFSR) 130 is n bits through the register transition for a 2 ^m period. To generate the Pien sequence.

The generated PEN sequence has an initial value in the generation polynomial, which is performed at the first time of the interleaving address generation for the block in which the decoding is performed.

In addition, when the flip-flop of the LFSR 130 is viewed as a binary value, the PIEN sequence has a range from 1 to 2 ⁿ -1, so that the interleaving address is designated from '0' so that the LFSR 130 can be assigned. '-1' is added to the Pien sequence outputted as to generate an n-bit Pien sequence.

This n-bit PN sequence is summed with the m bits bit-reversed in the bit inversion unit 120, and the sum value is designated as the total interleaving address value for the block to be decoded.

At this time, since the upper m bits are in the form of 2 ^m , they do not coincide with the form (2 ⁿ -1) of the Pien sequence.

This indicates that the period characteristics of the row and column do not match, and to compensate for this, a part of the bit reversing m bit value is subtracted.

The following describes the generation procedure of the Pien sequence that is summed with the bit inverted m bits.

This procedure is performed by the Column Initial Index 100 and the LFSR 130, and is intended to represent random occurrence characteristics.

First, a Pien sequence with a period characteristic of 2 ⁿ -1 The initial index of the first column is n _initial .

According to the present invention, the column initial index unit 100 assigns an initial index to each column except the first column by adding a predetermined increment to the initial index of the immediately preceding column.

Thus, the Pien sequence shifted by the initial index n _initial of the first column And the index increment If it is, the Pien sequence of the k + 1st column is as follows.

Since the PEN sequence has a characteristic of being sequentially generated, the index increment is stored in each column range so that the initial index of the next column PEN sequence of the current PEN sequence is known.

That is, an index increment defined as 2 ^m or less If is, the Pien sequence in the k + 2th column The initial index of Will exist in.

For example, the Pien sequence N = 3, index increment In Table 2, the array of PY sequence generation of each column when the index of the PY sequence of the first column is {2 5 0 7 1 3 6} is illustrated.

Row column One 2 3 4 5 6 7 8 One 2 (010) 0 (000) 1 (001) 6 (110) 2 (010) 0 (000) 1 (001) 6 (110) 2 5 (101) 7 (111) 3 (011) 4 (100) 5 (101) 7 (111) 3 (011) 4 (100) 3 0 (000) 1 (001) 6 (110) 2 (010) 0 (000) 1 (001) 6 (110) 2 (010) 4 7 (111) 3 (011) 4 (100) 5 (101) 7 (111) 3 (011) 4 (100) 5 (101) 5 1 (001) 6 (110) 2 (010) 0 (000) 1 (001) 6 (110) 2 (010) 0 (000) 6 3 (011) 4 (100) 5 (101) 7 (111) 3 (011) 4 (100) 5 (101) 7 (111) 7 6 (110) 2 (010) 0 (000) 1 (001) 6 (110) 2 (010) 0 (000) 1 (001)

The n-bit PN sequence generated in this manner is summed with the m-bit inverted bit. An interleaving address having a size of?

More specifically, first, {0 (000), 1 (001), 2 (010), 3 (011), 4 (100), 5 (101), 6 (110), and 7 (111)} By applying a bit reverse to each row of the turbo interleaver and simultaneously giving an initial index to give each column a Pien sequence, {2 (010), 5 (101), 0 (000), 7 (111), 1 (001), 3 (011), 6 (110), 4 (100)} generate the Pien sequence of the first column.

The index increment is then imposed on the first column's pieen sequence to generate the second column's pieen sequence.

Therefore, since the initial index of the second column in the occurrence range of the first column can be known, the Pien sequence of the second column starts to be generated during the generation of the first column.

As a result, in the present invention, the index increment is stored in each column, so that the initial index of the next column Pien sequence can be known within the generation range of the Pien sequence of the current column, thereby minimizing the memory used for interleaving.

If in turbo code decoder or In the case of using the turbo interleaver having the size of, the interleaving address is obtained by puncturing.

However, puncturing does not occur at two consecutive interleaving addresses through bit reversing of m bits, so that the interleaving address is output based on two clocks so that decoding is performed within a predetermined clock. the fly 'function.

In particular, in the design of the turbo interleaver according to the present invention, it is made in view of reducing the error occurrence of weight-2, and the error occurrence of weight-2 or the hamming distance of weight-2 in a given turbo interleaver size. It can be searched in terms of minimizing hamming distance.

Table 3 below shows the results of searching the generated polynomial, the initial index, and the index increment for each turbo interleaver according to the present invention.

40 80 160 320 640 1280 2560 3840 5120 Occurrence polynomial 13 23 23 67 67 155 103 103 211 Initial index 2 8 One One 0 One One 10 6 Index increment 4 11 0 2 2 29 0 0 29 Array configuration 8 * 7 8 * 15 16 * 15 16 * 31 32 * 31 32 * 63 64 * 63 64 * 63 64 * 127

5 and 6 are graphs showing performance comparison when using the turbo interleaver according to the present invention.

When the size of the turbo interleaver is 640, FIG. 5 shows a performance comparison in an Additive White Gaussian Noise (AWGN) environment, and FIG. 6 shows a non-correlative Rayleigh Fading channel environment. Performance comparison at

As described above, according to the turbo interleaver design method using the PEN sequence of the present invention, since the turbo interleaver is configured using the PEN sequence, there is an effect that the minimum memory is used.

It also has the best interleaving performance despite minimal memory usage.

Claims (3)

In a decoder using a turbo code and having one or more interleavers, Bitwise inverting the row bits of the interleaver and assigning a PN sequence to the column bits of the interleaver; Adding an initial index to the Pien sequence of the current column, and then generating a Pien sequence of the corresponding length; And generating an initialization of the next sequence of the next column of the corresponding length within the generation range of the current sequence of the current column. In a decoder using a turbo code and having one or more interleavers, Bitwise inverting the row bits of the interleaver and assigning a PN sequence to the column bits of the interleaver; Adding an initial index to the Pien sequence of the current column, and then generating a Pien sequence of the corresponding length; And generating an initial index of a next column after a predetermined index increment is applied to the current sequence of the current column. In designing one or more interleavers used in the turbo code decoder, a generation polynomial for randomly generating the Pien sequence for each column, an initial index of the generated Pien sequence, and an index increment for each column Turbo interleaver design method using a Pien sequence, characterized in that the interleaver of a predetermined size is designed in consideration of.