KR20000066066A - Method for determining the number of processing element in moving picture estimating algorithm - Google Patents

Abstract

PURPOSE: A method for determining processing element number in a moving pictures estimation algorithm is provided to find optimal processing element number corresponding to a size of a basic block and a searching point. CONSTITUTION: A method for determining processing element number in a moving pictures estimation algorithm includes minimal processing element number(NPE1) corresponding to a specification of a system and an application(305). A size of the minimal basic block size and the size of the minimal searching points are compared(314). The size which is determined to be smaller at the second step is determined to be a block to be divided, and the block is divided sequentially(315,316). A division processing element number(NPE2) corresponding to the number of pixels included in the block to be divided is calculated. When the NPE2 is same to the NPE1, the NPE2 is determined to be the optimal processing element number. Otherwise, an integer closest to the NPE1 is determined to be the optimal processing element number.

Description

Method for determining the number of processing element in moving picture estimating algorithm

The present invention relates to a method for designing a motion estimation algorithm in a video signal processing apparatus, and more particularly, to a method for optimizing the number of processing elements for performing a set of operations for video motion estimation.

With the development of digital image signal processing technology, the application area of image compression technology is rapidly expanding into the fields of home appliances, computers, etc., rather than staying in communication media.

One of the representative standards of digital image signal processing technology is a moving picture compression algorithm using MPEG (Moving Picture Experts Group).

1 is a block diagram of an MPEG encoder to which a general video compression algorithm is applied.

In brief, the video signal is input to the information source encoder 11 to perform DCT, quantization and motion estimation to compress the amount of information. Then, the video signal multiplexing encoder 12 generates standard data which has been subjected to hierarchical coding and variable length coding, and makes the amount of data transmitted by the transmission buffer 13 constant. The encoding control unit 14 judges the buffer capacity input from the transmission buffer 13, and serves to instruct the information source encoder 11 and the video signal multiplexing encoder 12 to increase or decrease the amount of information generation.

In such a moving picture compression algorithm of an encoder, a motion estimation part for moving picture coding requires the most computation amount. The motion estimator constituting the source coder 11 often accounts for up to 50% of the chip's total processing power. Therefore, it is difficult to process the motion estimator in software along with other system modules on the risk processor. Therefore, most of the motion estimator is implemented in hardware.

In making the motion estimator independent hardware chip, if the hardware structure is changed to improve the operation speed, the chip size becomes so large that it becomes almost impossible to make the video codec system on the chip (SOC).

On the other hand, focusing on reducing hardware size slows down the operation speed, making real-time operation difficult. Therefore, there is a need for an appropriate compromise between these operating speeds and the size of hardware.

Looking at the hardware structure of the motion estimator, the partial hardware modules may vary according to the type of algorithm used, and the size of the hardware varies according to the modules.

However, in most motion estimation algorithms, a mean of absolute difference (MAD) is used as a matching algorithm for calculating a sum of motion differences between a previous frame and a current frame. To calculate the absolute difference average, a set of operations (addition, absolute value, subtraction) is required. The module for this is a processing element (PE). The size and number of these processing elements have a big impact on the size and performance of the motion estimator.

When implementing a motion estimator, a basic array is a compression array consisting of an array of processing elements for calculating the absolute difference average.

According to the related art, as shown in FIG. 2, the number of processing elements, which is a part for the actual calculation in the basic searcher, is determined by the size of the search point or the size of the macro block. Empirically selected according to the requirements of the appropriate selection.

If the best-known front search algorithm among block matching algorithms is the size of the macro block is 16x16 and the search areas for the search are 32x32, then 256 processing elements can be simply used for the best performance. In this case, however, these processing elements take up too much chip area. If the motion estimator is intended for low bit data transfers, such as H.263, it will introduce unnecessary losses in the silicon area, which is directly related to the chip price.

As such, in determining the number of processing elements according to the related art, according to the designer's experience without an objective calculation method, there is a problem that a large loss in the size and performance of the motion estimator may occur in some cases.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for determining the number of processing elements in a video estimation algorithm for determining an optimal number of processing elements corresponding to the size of a basic block and a search point in order to solve the above problems.

1 is a block diagram of a general MPEG encoder.

2 is a flowchart of a method for determining the number of processing elements according to the related art.

3 is a flowchart of a method for determining the number of processing elements in a video estimation algorithm according to the present invention.

In order to achieve the above technical problem, the method for determining the number of processing elements in the video estimation algorithm according to the present invention is a method for determining the optimal number of processing elements constituting the motion estimator, which (a) corresponds to the system and application specification. Obtaining the number of feasible minimum processing elements (N _PE1 ), (b) comparing the size of the minimum basic block and the size of the minimum search point, (c) comparing the small size as a result of the step (b) Determining to have a division target block and sequentially dividing the same; and (d) calculating a number of division processing elements N _PE2 corresponding to the number of pixels included in the blocks sequentially divided in the step (c). and step (e) the N _PE1 and _PE2 compared to the N, N _PE2 optimum processing this value if the value such as N _PE1 from El Determining a number (N _PEO) in the cement, otherwise characterized in that the N _PE2 having a value greater than N _PE1 includes the step of determining the nearest integer value for N to N _{PE1 PEO.}

Therefore, a compression array method is widely used, which simultaneously processes a certain amount of pixels using a pipeline method, and repeatedly uses the same number of processing elements repeatedly. This method reduces the performance of the motion estimator from a speed standpoint, but can significantly reduce the chip size because it reduces the number of processing elements. In this case, the designer uses the size of the search block or the search area used to determine the number of processing elements. As a method of determining the number of processing elements, in the case of front search, macro blocks are mainly divided. This is because, in general, the size of the macro block is smaller than that of the search area, so it is advantageous to divide it. On the other hand, in the hierarchical search method in which the search area and the macro blocks are divided into appropriate sizes and use blocks of different sizes for each layer, it is most advantageous to determine the number of processing elements based on the smaller one among the divided search areas and macro blocks. It is used as a method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The algorithm for determining the optimal number of processing elements according to the present invention is largely optimized in consideration of the first process (step 301 to step 305) of calculating the minimum number of processing elements and the size of the basic block and the size of the search point. It can be roughly divided into the second process (step 306 to step 316) of calculating the number of processing elements of the?

First, the flow of calculating the minimum number of processing elements by the first process will be described.

First, an application is determined as a design initial decision. In the present invention, as an example, the application is determined to be H.263.

Next, system specifications such as system clock, video shooting, frames per second, etc. are determined. The system required specifications of CIF (352 * 288 pixels) * 30 frames / second, and the range of the search region of the previous frame was -16 to 16, and the size of the search block in the current frame was 16 * 16. (Step 302)

Then, in the case where the algorithm based on the full survey method is selected, the calculation amount N _OP is obtained as follows (step 303).

N _OP = {(352 × 288) / 16 ² } × (2 × 16) ² × 16 ² × 30 = 3114.68 (MOPS)

If the clock frequency (F _C ) to be used is determined as 30 MHz, the minimum number of processing elements (N _PE ) is calculated according to Equation 1 (step 304).

Therefore, the number N _PE1 of the minimum processing elements that can be realized in the case of employing the full-surface irradiation method is determined to be an integer value 104 (step 305).

If the case is applied to the motion vector survey method using the hierarchical search method using the correlation instead of the front survey method is as follows.

For example, the hierarchical search method is a method of investigating hierarchical search block matching algorithms with 3 candidates and spatial correlation (HSBMA3S) among recently published algorithms.

The HSBMA3S survey method can reduce the number of calculations, but requires more complex circuits than the full survey method.

In addition, a compression array method that processes a certain amount of pixels simultaneously using a pipeline method and repeatedly uses the same number of processing elements repeatedly is widely used. This method reduces the performance of the motion estimator from a speed standpoint, but can significantly reduce the chip size because it reduces the number of processing elements. In this case, the designer uses the size of the search block or the search area used to determine the number of processing elements. As a method of determining the number of processing elements, in the case of front search, macro blocks are mainly divided. This is because, in general, the size of the macro block is smaller than that of the search area, so it is advantageous to divide it. On the other hand, in the hierarchical search method in which the search area and macro blocks are divided into appropriate sizes and use different size blocks for each layer, the method of determining the number of processing elements based on the smaller one among the divided search areas and macro blocks is used. do.

In the case of selecting an algorithm based on the HSBMA3S research method, which is one of the hierarchical search methods, the calculation amount N _OP is obtained as follows (step 303).

N _OP = {(9 ² × 4 ² ) + (3 × 5 ² × 8 ² ) + (5 ² × 16 ² )} × {(352 × 288) / 16 ² }

= 148.45MOPS

The minimum number of elements N _PE is calculated using Equation 1 as follows.

N _PE = 148.45M / 30M = 4.95

Therefore, in the case of selecting the algorithm by the HSBMA3S research method, the number of feasible minimum processing elements N _PE1 is determined as 5, which is the minimum integer value greater than or equal to 4.95 (step 305).

Next, a second process of obtaining the optimal number of processing elements in the case of selecting an algorithm based on the HSBMA3S irradiation method will be described.

Assume that the MEB algorithm based on the HSBMA3S survey method is selected as the motion vector survey method, which is an initial design setting, and the H.263 pipeline structure is selected as the hardware (steps 306 to 307).

In the HSBMA3S irradiation method, when the macroblock used in the top layer is 4x4 blocks (16 pixels), and the size of the minimum search point is determined to be 16x16 blocks (steps 308 to 309), the basic block and the search points After comparing the sizes, it is determined that the one having the small size is a division target block. Therefore, in the present invention, since the size of the basic block is smaller than the size of the search point, it is determined that the basic block is a division target block (steps 310 to 311).

After that, since the number of pixels of the 4x4 macroblock that has been determined to be divided is even, the pixels are divided by 1/2 by the dividing method, and the number of pixels in the divided unit blocks is calculated to correspond to the number of pixels. Calculate the number of split processing elements N _PE2 . Accordingly, the number N _{PE2 of the} first divided processing elements is 8, which is half of 16 pixels. (Steps 312 to 313)

Then, the number of the smallest possible processing elements N _PE1 determined in step 305 and the size of the split processing element number N _PE2 calculated in step 313 are compared (step 314).

As a result of the comparison of step 314, the number of processing elements (N _PE2 ) calculated after the first division is greater than 5, which is the minimum number of processing elements (N _PE1 ) that can be realized by eight, so that the number of processing elements (N) calculated after the first division _PE2 ) is stored in a memory that stores the optimal processing element number N _PE0 , and then returns to step 312 to divide the primary partitioned block once again. That is, the first divided eight pixels are divided into two parts, and each pixel is divided into blocks capable of processing four pixels.

Then, if the division processing element number N _PE2 is obtained in step 313, it is determined as 4 since the secondary partitioned block is composed of 4 pixels.

Thereafter, in step 314, the number of second-segmented processing elements (N _PE2 ) 4 is compared with the number of feasible minimum processing elements (N _PE1 ) 5.

As a result of the comparison in step 314, since the number of second-segmented processing elements N _PE2 is smaller than the minimum number of feasible processing elements N _PE1 , the number of optimal processing elements N stored in the memory before the current division by step 316 (N Output 8, _PE0 ).

However, since the optimal number of processing elements (N _PE0 ) 8 determined in the uppermost layer corresponds to a relatively large value compared to the maximum number of feasible minimum processing elements 5, there is almost 40% or more overhead.

Accordingly, steps 308 to 316 are applied to the middle layer and the lower layer, and the optimum number of processing elements is repeatedly obtained in the same manner as described above.

The search areas used in the middle and lower layers are -2 to 2.

In this case, since the search point is smaller than the size of the basic block as a result of the comparison in step 310, in step 311, the division target block is determined as an area of the search point.

In step 312, a 5 x 5 initial search point region is divided. In this case, since the number of pixels in the area is odd, the division by the dividing method is not possible. In this case, it is divided into rows. Accordingly, since the number of pixels in one row is five, the division processing element number N _PE2 is determined to be 5 in step 314.

By step 314, the size of the calculated number of split processing elements N _PE2 is compared with the number of feasible minimum processing elements N _PE1 . In this case, since the minimum number of possible processing elements (N _PE1 ) and the calculated number of split processing elements (N _PE2 ) are equal to 5, the optimal number of processing elements (N _PE0 ) already stored in the memory in step 315 is 8. Replace with 5 to save.

Thus, the finally determined optimal number of processing elements N _PE0 is 5, which corresponds to the number of processing elements with almost no overhead in this case.

Of course, the processing elements used above are executed concurrently by the number of processing elements using the pipeline. For example, if you want to perform all the calculations on the pixels of 25 search points using 5 processing elements, you can use 5 processing elements five times.

In conclusion, the designer can design the motion estimator with the optimal number of processing elements by selecting five processing elements.

In the above embodiment, for convenience of description, a method of obtaining an optimal number of processing elements in the case of selecting an algorithm based on the HSBMA3S research method is presented. It is natural that the above method can be applied in the front irradiation method to obtain an optimal number of processing elements.

Then, how the number of processing elements (PE) in the case of applying the present invention affects the overall motion estimator area.

In general, the number of gates used in one processing element considering the chip area is about 256. This gate count is obtained by synthesizing the general-purpose processing elements in the VHDL hardware language and synthesizing them with the Synopsis tool. In the present invention, when the front irradiation method is adopted, 32 optimal processing elements can be obtained using at least 26 processing elements obtained by the formula introduced to process QCIF (176 × 144) 30 frames / sec.

Accordingly, when the chip area is not taken into account, the gate number N _G1 is

N _G1 = 256 gates × 256 PE = 65536 gates

The gate number (N _GO ) in the case of obtaining the optimum PE by applying the present invention is

N _GO = 256 gates × 32 PE = 8192 gates

Becomes

Therefore, when the chip area is not considered, 256 PEs are used, and the total number of gates of PE used for this is more than five times the number of gates for the motion estimator except the PE. Therefore, the specification of the application, the motion estimator used, has almost 4.2 times the overhead of considering this.

As described above, according to the present invention, by finding the optimal number of processing elements corresponding to the size of the basic block and the search point according to the type of application, not only can the overhead be reduced but the number of gates required is greatly reduced, thereby reducing the chip area. There is an effect that can be reduced.

Claims (4)

A method of determining the optimal number of processing elements that make up a motion estimator, (a) _obtaining a number of feasible minimum processing elements N _PE1 corresponding to system and application specifications; (b) comparing the size of the minimum basic block and the size of the minimum search point; (c) determining that the block to be divided has a small size as a result of the comparison in step (b), and dividing the blocks sequentially; (d) calculating the number of division processing elements (N _PE2 ) corresponding to the number of pixels included in the blocks sequentially divided in step (c); And (e) comparing the N _PE1 and the N _PE2 , and if there is a value equal to N _PE1 among N _PE2 , this value is determined as the number of optimal processing elements (N _PEO ), otherwise N having a value larger than N _{PE1. And} determining an integer value closest to N _PE1 among _PE2 as N _PEO . The method of claim 1, wherein in step (a), the number of feasible minimum processing elements (N _PE1 ) is represented by Equation 1. [Equation 1] N _PE1 ≒ N _OP / F _C (N _OP is the total calculation amount per second, F _C is the clock frequency) A method for determining the number of processing elements in a video estimation algorithm characterized in that the operation. The method of claim 1, wherein the steps (b) to (d) are executed sequentially from the highest layer to the lowest layer. 2. The method of claim 1, wherein the division in the step (c) is performed by dividing by a dividing method when the number of pixels included in the block is an even number, and dividing by a row unit when the odd number is odd. A method for determining the number of processing elements in a video estimation algorithm.