KR20000065976A - Apparatus for interworking in frame relay-atm - Google Patents

Abstract

PURPOSE: An interlocking device of a frame relay and an asynchronous transfer mode is provided to divide and process loads generated due to interlocking between a frame relay and an asynchronous transfer mode using two different processors. CONSTITUTION: A main processor(310) transfers the data with an external IPC DRAM(312) and an internal IPC DRAM(330) through a main processor local bus. A sub processor(320) transfers the data with the internal IPC DRAM(330) through a sub processor local bus. A frame relay packet transmitted through a T1/E1 link is received to an HDLC(High-level Data Link Controller)(316) through a matching part(318). The frame relay packet outputted from the HDLC(316) is transmitted to the T1/L1 link through the matching part(318). An ATM cell transferred through an ATM link is received to an SAR(Segmentation And Reassembly) controller(324). The ATM cell outputted from the SAR controller(324) is transmitted to the ATM link.

Description

Frame relay and asynchronous transmission mode interlocking device {APPARATUS FOR INTERWORKING IN FRAME RELAY-ATM}

The present invention relates to an interlock device of a frame relay and an asynchronous transmission mode, and more particularly, to an interlock device in which two processors share a load according to the interworking of the frame relay and the asynchronous transmission mode.

Recently, with the rapid development of technology in all fields such as semiconductor, computer, transmission, and exchange, communication network is becoming more and more high speed, diversification and wide area, and the communication service using the communication network is simple data communication, data and graphic. It is being subdivided into multimedia communication services such as video, video, and so on.

In addition, the transmission speed of the data communication network for providing the communication service is being accelerated to several hundred Mbps in the low-speed communication of several kbps, and the service providing range is widening from the urban area to the global area.

Therefore, in response to the above-mentioned trend, research and development for high-speed data communication are being carried out worldwide. Representative examples of the high-speed data communication technology include frame relay, metropolitan area network (MAN), switched multi-megabit data service (SMDS), and asynchronous transmission mode (ATM). Asynchronous Transfer Mode).

In general, frame relay is capable of high-speed transmission by minimizing functions such as error control and flow control on the network side in order to meet high-speed massive traffic connection demands such as interconnection between local area networks (LANs). It's a technology that let you do that.

On the other hand, ATM is intended for use in a huge public network, a technology that cuts an information signal into equally sized to form an ATM cell and deliver it through a virtual channel.

However, as a huge investment and time is required to build an ATM network, high-speed data communication by frame relay will be performed in the short term, and will gradually change to ATM in the long term.

In this regard, frame relay and ATM may coexist in the evolution of the high-speed data communication industry, and in this case, frame relay and ATM using different protocols are not compatible. Done.

Therefore, there is a need to implement a frame relay and an ATM compatible with different protocols. The technique proposed by the above needs is an interworking apparatus of a frame relay and an ATM. More specifically, the frame relay interworking device in the ATM exchanger is a device that processes frame relay protocol data and ATM cell data and converts them into relative protocol data.

The structure of the interworking device between the frame relay and the ATM, which is conventionally implemented by the above, is as shown in FIGS. 1 and 2.

1 is a diagram illustrating an example of a frame relay and an ATM interworking apparatus using a bus control logic, and FIG. 2 is a frame relay system employing a Peripheral Component Interconnect Bus (PCI bus). A diagram illustrating an example of implementing an ATM interworking device. 1 and 2 illustrate the path of user packet data along with the main components of a conventional interworking device between a frame relay and an ATM.

However, in the case of the companion device having the configuration shown in FIG. 1, a high-level data link controller (HDLC) 114 and a cell division / assembly (SAR); Segmentation and Reassembly) There is a problem in that a complicated bus adjustment logic between the control unit 118 is required, and as a general bus is used, user packet forwarding performance is low, thereby lowering processing speed. In addition, as one processor controls the HDLC control unit 114 and the SAR control unit 118, the processing load increases, and thus many links cannot be accommodated. For example, about 2 T1 / E1 low speed links can be processed.

On the contrary, the interworking device having the configuration shown in FIG. 2 is an improved form compared to the interlocking device having the structure shown in FIG. Can be.

However, since the control of the HDLC control unit 114 and the SAR control unit 118 in one processor is the same as the interlocking device of the structure shown in FIG. 1, the same problem that many links cannot be accommodated due to an increase in the processing load of the processor. Will have For example, four T1 / E1 low-speed links can be processed.

As described above, in the frame relay-ATM interworking apparatus, an interworking function between the frame relay data processing, the ATM cell data processing, and the protocol data according to the two data processings should be performed.

However, when the above-described function is performed by one processor, the processing load of the processor is high, so that it is difficult to accommodate a high speed link, and a low link such as T1 / E1 may also be difficult to accommodate.

Accordingly, an object of the present invention is to provide an interworking apparatus between a frame relay and an asynchronous transmission mode for solving the above problems.

Another object of the present invention is to provide an interlocking apparatus for sharing and processing loads generated by interworking between a frame relay and an asynchronous transmission mode by using two different processors.

According to a first aspect of the present invention for achieving the above object, a main processor converts frame relay header information provided from a high level data link controller to AMT cell header information and outputs the information to a main processor local bus. It provides frame relay header information provided through the main processor local bus to the high level data link controller.

The subprocessor converts the ATM cell header information provided from the cell division / assembly control unit to frame relay header information and outputs the AMT cell header information to the subprocessor local bus, and divides the AMT cell header information provided through the subprocessor local bus to the cell division. / As an assembly control unit,

An internal access bus interface configured to add communication memory between internal processors to mutually transfer frame relay header information and AMT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor; The interworking device of the frame relay and asynchronous transmission mode is implemented.

According to a second aspect of the present invention for achieving the above object, a main processor outputs frame relay header information provided from a high level data link controller to a main processor local bus, and is provided through the main processor local bus. Converts AMT header information to frame relay header information to provide the high level data link controller,

The subprocessor outputs the AMT cell header information provided from the cell division / assembly control unit to the subprocessor local bus, and converts the frame relay header information provided through the subprocessor local bus into AMT header information to divide the cell. To the assembly control unit,

An internal access bus interface configured to add communication memory between internal processors to mutually transfer frame relay header information and AMT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor; The interworking device of the frame relay and asynchronous transmission mode is implemented.

1 is a view showing an example of a configuration according to an interlock device of a frame relay and an asynchronous transmission mode using a conventional bus adjustment logic.

2 is a diagram showing an example of a configuration according to an interlock device of a frame relay and an asynchronous transmission mode employing a conventional internal access bus.

3 is a diagram illustrating a configuration according to an interlock device of a frame relay and an asynchronous transmission mode according to an embodiment of the present invention.

4 is a view showing an example in a typical configuration of a frame used in the frame relay method.

5 shows an example of a typical configuration of a cell used in an asynchronous transmission mode.

Hereinafter, described in detail with reference to the accompanying drawings according to an embodiment of the present invention.

First, the configuration according to the interlock device of the frame relay and the asynchronous transmission mode as an embodiment of the present invention is as shown in FIG.

Referring to Figure 3, the configuration of the interworking device according to the present invention is implemented in one processor in Figure 2 showing the configuration of the frame relay and the interworking device of the ATM by using the PCI bus and the main processor 310 and An internal processor communication memory (hereinafter referred to as “internal IPC memory”) 330 configured as two processors divided into subprocessors 320 and shared by the main processor 310 and the subprocessor 320. Added.

The IPC memory 330 uses dual port RAM (DPRAM) accessible by both the main processor 310 and the subprocessor 320. In addition, a control program for allowing the main processor 310 and the subprocessor 320 to operate in conjunction is added.

That is, the present invention is divided into a function provided by an interlocking device, and classified into a high-level data link controller (HDLC) processing function, a SAR processing function, and an interworking function. The main processor 310 is responsible for the interworking function between the HDLC processing function and the frame relay-ATM, and the subprocessor 320 is responsible for the SAR processing function and the ATM-frame relay interworking function. On the other hand, the control information with the upper processor block (not shown) is processed by the main processor 310 through the communication memory between the external processors (hereinafter referred to as "external IPC memory") 312, and the necessary information is processed. The IPC communication is performed in a manner of transferring to the subprocessor 320 through the internal IPC memory 330.

The main processor 310 transmits data with the external IPC memory 312 and the internal IPC memory 330 through a main processor local bus, and the subprocessor 320 sends the internal IPC memory through a subprocessor local bus. Send data with 330.

Referring to the configuration according to the present invention in more detail, the frame relay packet transmitted through the T1 / E1 link via the matching unit 318 high-level Data Link Controller (hereinafter referred to as "HDLC control unit"). Frame relay packet received from the HDLC control unit 316 is transmitted to the T1 / E1 link via the matching unit 318.

After receiving the frame packet, the HDLC controller 316 performs an error check on the received frame packet, separates user data from the frame packet, outputs it to the PCI bus, and generates an interrupt for notifying the reception of the frame packet. Also, the HDLC control unit 316 for transmitting the frame packet receives the frame packet to be output to the T1 / E1 link through the matching unit 318 through the PCI bus and performs a predetermined process according to the transmission. In this case, the user data is different depending on the service method of the frame relay. That is, when the frame relay service method is a network interworking method, the concept includes user information and a header. When the frame relay service method is a network interworking method, it means only pure user information. On the other hand, the HDLC control unit 316 has a PCI interface (marked with a hatch on the drawing) for the interface with the PCI bus.

The ATM cell transmitted over the ATM link (ATM switch side) is received by the SAR control unit 324, and the ATM cell output from the SAR control unit 324 is transmitted to the ATM link. The SAR control unit 324 performs an error check on the ATM cell received through the ATM link, recombines the received ATM cells, configures the user data, and outputs the user data received from the PCI bus. The ATM cell is divided into predetermined bytes to output an ATM link. Meanwhile, the SAR control unit 324 has a PCI interface (marked with a hatch on the drawing) for interfacing with the PCI bus.

The packet memory 328 is located on a PCI bus so that user frame data with the HDLC control unit 316 or an ATM cell path with the SAR control unit 324 and control information paths of the main processor 310 and the subprocessors 320 may be provided. It is separated from the data path and allows user data to be transferred within a PCI bus capable of high speed processing. To this end, logic for performing a bridge function between the PCI bus and the packet memory 328 is required, which is illustrated as a PCI memory bridge 326 in the drawing.

Meanwhile, the main processor local bus corresponding to the data transmission path of the main processor 310 described above and the subprocessor local bus corresponding to the data transmission path of the subprocessor 320 may each pass through the PCI bus bridges 314 and 322. Transfer data with the bus. In this case, the PSI bus bridges 314 and 322 each have a PCI interface (indicated by a hatch on the drawing) for interfacing with the PCI bus.

The main processor 310 performs HDLC processing on a frame packet received from the frame relay side and a series of controls for converting an ATM cell into a frame relay packet.

In more detail, when an interrupt is received by receiving a frame packet, the start address and the user of the packet memory 328 in which the user information of the received frame packet is stored together with the header information of the received frame packet in response to the interrupt. Request information size information. The header information of the frame packet is provided from the HDLC control unit 316, and the start address and size information are provided from the packet memory 328. The start address and size information refer to a start address of the packet memory 328 in which user frame data of a frame packet is recorded and a size of the user frame data. Meanwhile, the header information, the start address, and the size information of the provided frame packet are recorded in the internal IPC memory 330 by the main processor 310 through the main processor local bus.

In addition, when the ATM cell header information, the start address, and the size information are provided from the internal IPC memory 330 through the main processor local bus, the main processor 310 converts it into frame relay header information. The converted frame relay header information is provided to the HDLC controller 316 via the main processor local bus, the PCI bus bridge 314, and the PCI bus. Meanwhile, the packet memory 328 may be accessed by the start address and size information indicating the address and size of the packet memory in which user data is stored by the ATM cell so that the corresponding user data may be provided to the HDLC controller 316. do.

The subprocessor 320 performs SAR processing on the ATM cell received from the ATM side and a series of controls for converting the frame relay packet into the ATM cell.

In more detail, when an interrupt is received from the SAR control unit 324 by reception of an ATM cell, the packet memory in which user data of the received ATM cell is stored together with header information of the received ATM cell in response to the interrupt ( 328) the start address and size information of the user information. Header information of the ATM cell is provided from the SAR control unit 324, and the start address and size information are provided from the packet memory 328. The start address and the size information refer to the start address of the packet memory 328 in which user data of an ATM cell is recorded and the size of the user data (typically 48 bytes in the case of an ATM cell). Meanwhile, header information, start address, and size information of the provided ATM cell are recorded in the internal IPC memory 330 by the subprocessor 320 through a subprocessor local bus.

In addition, when the header information, the start address, and the size information of the frame relay packet are provided from the internal IPC memory 330 through the subprocessor local bus, the main processor 310 converts the information into ATM cell header information. The converted ATM cell header information is provided to the SAR controller 324 via the subprocessor local bus, the PCI bus bridge 322, and the PCI bus. Meanwhile, the packet memory 328 is accessed by the start address and size information indicating the address and size of the packet memory in which the user frame data is stored by the frame relay packet, and the corresponding user frame data is provided to the SAR controller 324. To be possible.

As described above, the configuration according to the embodiment of the present invention divides the processor of the interlocking apparatus employing the conventional internal connection bus into the main processor 310 and the subprocessor 320, and the main processor 310 and the subprocessor. It can be seen that the configuration is added to the internal IPC memory 330 so that data between the 320 can be shared.

Meanwhile, an example of a frame relay packet configuration is as shown in FIG. 4, and an example of an ATM cell configuration is as shown in FIG. 5.

Referring to FIG. 4, the header information constituting the header among the frame packets composed of the header and the information area (user frame data), etc., includes DLCI (Data Link Connection Identifier), EA (Extended Address), and Forward Explicit (FECN). Congestion Notification (BECD), Backward Explicit Congestion Notification (BECD), Disc Eligibility (DE), and Command / Response (C / R). The header having the above configuration shows an example of the configuration according to the 2-octet address assignment.

The DLCI is used for an addressing function, and the EA is used for extending an addressing interval. In addition, FECN / BECN, DE are used for congestion control, and C / R is not used in the network but in user equipment. In addition, FCS follows ITU-T 16-CRC and is used to check whether an error occurs in a frame.

Next, the header information constituting the header of the ATM cell including the 5-byte header and the 48-byte payload space including the user information will be described with reference to FIG. 5.

The main function of the cell header is to identify cells belonging to the same virtual channel among ATM cells present in the symmetrical time division multiplexing (ATDM) information flow. This is a function indicated by the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) shown in FIG. In this case, the virtual path refers to a bundle of virtual channels sharing a certain path, the cell header distinguishes other payload types (PTs), and indicates a cell loss priority (CLP). It provides Header Error Control (HEC). Meanwhile, the cell header has two types of header structures, the first of which is a header structure of a UNI (User Network Interface), and the second of which is a header structure of a network node interface (NNI). The UNI also provides a generic flow control (GFC) function to the cell header.

Hereinafter, an operation according to an exemplary embodiment of the present invention will be described in detail with reference to the configuration as described above.

First, an operation of converting a frame relay packet received from a T1 / E1 link (frame relay side) into an ATM cell will be described in detail.

The frame relay packet transmitted through the T1 / E1 link is received by the matching unit 318 to the HDLC control unit 316, and the HDLC control unit 316 receiving the frame relay packet checks an error for the received frame relay packet. Will be done.

When the error check is completed, the HDLC control unit 316 separates user data and header information from the frame relay packet, outputs them to the PCI bus, and generates an interrupt for notifying the reception of the frame packet. In this case, the user data, the header information, and the interrupt are output to the PCI bus through the PCI interface provided in the HDLC control unit 316.

The output user data is provided to the PCI memory bridge 326 connected to the PCI bus and processed in a form that can be stored in the packet memory 328 and stored in a specific area of the packet memory 328. At this time, the start address and size information of the packet memory 328 in which user data is stored may be separately managed.

On the other hand, the output interrupt and frame relay header information is provided to the PCI bus bridge 314 connected to the PCI bus is converted into the data format required by the main processor local bus and output. That is, the data on the PCI bus and the main processor local bus may be shared by the PCI bus bridge 314, where the PSI bus bridge 314 is a PCI interface (not shown) for interfacing with the PCI bus. And indicated by hatching).

Interrupts provided to the main processor local bus via the PCI bus bridge 314 are provided to the main processor 310. The main processor 310 provided with the interrupt by the reception of the frame packet includes a start address of the packet memory 328 in which user information of the received frame packet is stored together with header information of the received frame packet in response to the interrupt. Request size information of user information.

The header information of the frame packet is provided from the HDLC controller 316 through the same path as the interrupt is provided, and the start address and size information are output to the packet memory 328 to output a request command to the packet memory ( 328). As described above, the start address and the size information refer to the start address of the packet memory 328 in which user frame data of the frame packet is recorded and the size of the stored user frame data.

On the other hand, the header information and start address and size information of the received frame packet are output to the main processor local bus by the main processor 310, and the header information, start address and size information of the output frame packet are internal IPC. It is provided to the memory 330 and recorded.

When the recording is completed, the main processor 310 performs an operation for notifying that there is data to be transmitted. As a result, a method using a specific bit of the internal IPC memory 330 and a method using an interrupt are performed. Will be there.

Upon detecting the existence of data to be transmitted by one of the two methods, the subprocessor 320 accesses the internal IPC memory 330 to transmit header information, start address, and size information of a frame relay packet. Requires.

By the request, the internal IPC memory 330 outputs header information, start address, and size information of the stored frame relay packet to the subprocessor local bus. Header information, start address, and size information of the frame relay packet output to the subprocessor local bus are provided to the subprocessor 320.

The subprocessor 320 receiving the header information, the start address, and the size information of the frame relay packet converts it into ATM cell header information. Briefly, VPI and VCI of ATM cell header information shown in FIG. 5 are generated by DLCI among the header information of the frame relay packet shown in FIG. 4. In addition, the CLP of the ATM cell header information is generated by DE of the header information of the frame relay packet. Since generating the configuration of the ATM cell header information from the configuration of the header information of the frame relay packet is already known, a detailed description thereof will be omitted.

When the conversion to the ATM cell header information is completed, the subprocessor 320 outputs the converted ATM cell header information to the subprocessor local bus. The output ATM cell header information and the start address and size information are provided to the PCI bus via the PCI bus bridge 322.

Meanwhile, header information of an ATM cell provided to the PCI bus is provided to the SAR controller 324, and the start address and size information are provided to the packet memory 328 through the PCI memory bridge 326. The packet memory 328 receiving the start address and size information reads out and outputs user frame data corresponding to the size information from the start address. The user frame data output from the packet memory 328 is output to the PCI bus via the PCI memory bridge 326. The user frame data output to the PCI bus is provided to the SAR controller 324 through a PCI interface provided therein.

That is, the SAR control unit 324 accesses the packet memory 328 by the start address and size information indicating the address and size of the packet memory 328 in which the user frame data is stored by the frame relay packet. To be provided).

On the other hand, the SAR control unit 324 receiving the user frame data from the PCI bus divides the user frame data into predetermined bytes (48 bytes). When the division into the predetermined byte is completed, the SAR controller 324 adds the ATM cell header information provided from the subprocessor 320 to the divided predetermined byte of user data to generate a complete ATM cell.

The generated ATM cell is output from the SAR control unit 324, and the output ATM cell is transmitted to the ATM link.

Next, an operation of converting an ATM cell received from an ATM switch (ATM side) into a frame relay packet will be described in detail.

The ATM cell transmitted through the ATM link (ATM switch side) is received by the SAR control unit 324, and the SAR control unit 324 performs an error check on the ATM cell received through the ATM link. When the error check is completed, the SAR control unit 324 recombines the received ATM cells to form user data and outputs them to the PCI bus. Header information and interrupts decomposed from the ATM cells are also output to the PCI bus. In this case, the user data, the header information, and the interrupt are output to the PCI bus through the PCI interface provided in the SAR control unit 324.

The output user data is provided to the PCI memory bridge 326 connected to the PCI bus and processed in a form that can be stored in the packet memory 328 and stored in a specific area of the packet memory 328. At this time, the start address and size information of the packet memory 328 in which user data is stored may be separately managed.

On the other hand, the output interrupt and the header information of the ATM cell is provided to the PCI bus bridge 322 connected to the PCI bus is converted into the data format required by the subprocessor local bus and output. That is, data on the PCI bus and the subprocessor local bus may be shared by the PCI bus bridge 322, where the PSI bus bridge 322 is a PCI interface for interfacing with the PCI bus. And indicated by hatching).

Interrupts provided to the subprocessor local bus via the PCI bus bridge 322 are provided to the subprocessor 320. The subprocessor 320 provided with the interrupt by the reception of the ATM cell includes a start address of the packet memory 328 in which user data of the received ATM cell is stored together with header information of the received ATM cell in response to the interrupt. Request size information of user information.

The header information of the ATM cell is provided from the SAR control unit 324 through the same path as that provided with the interrupt, and the start address and size information are output to the packet memory 328 to output a request command to the packet memory ( 328). As described above, the start address and the size information refer to the start address of the packet memory 328 in which user data of the ATM cell is recorded and the size of the stored user data.

On the other hand, the header information and start address and size information of the provided ATM cell are output to the subprocessor local bus by the subprocessor 320, and the header information, start address and size information of the output ATM cell are internal IPC. It is provided to the memory 330 and recorded.

When the recording is completed, the subprocessor 320 performs an operation for notifying that the data to be transmitted exists. The operation is performed by the same method as that of the main processor 310.

When detecting that there is data to be transmitted, the main processor 310 accesses the internal IPC memory 330 and requests transmission of header information, start address, and size information of an ATM cell.

By the request, the internal IPC memory 330 outputs header information, start address, and size information of the stored ATM cell to the main processor local bus. Header information, start address, and size information of the ATM cell outputted to the main processor local bus are provided to the main processor 310.

The main processor 310 which receives the header information, the start address and the size information of the ATM cell converts the header information into the header information of the frame relay packet. In brief, the DLCI is generated in the header information of the frame relay packet shown in FIG. 4 by VPI and VCI in the ATM cell header information shown in FIG. 5. The CLP of the ATM cell header information generates the DE of the header information of the frame relay packet. Since the configuration of the header information of the frame relay packet from the configuration of the ATM cell header information is already known, a detailed description thereof will be omitted.

When the conversion of the frame relay packet into header information is completed, the main processor 310 outputs the header information of the converted frame relay packet to the main processor local bus. The header information and the start address and size information of the output frame relay packet are provided to the PCI bus via the PCI bus bridge 314.

Meanwhile, header information of the frame relay packet provided to the PCI bus is provided to the HDLC controller 316, and the start address and size information are provided to the packet memory 328 through the PCI memory bridge 326. The packet memory 328 receiving the start address and size information reads out the user data as much as the size information from the start address and outputs the same. The user data output from the packet memory 328 is output to the PCI bus via the PCI memory bridge 326. The user data output to the PCI bus is provided to the HDLC control unit 316 through a PCI interface provided therein.

The HDLC control unit 316 receiving user frame data from the PCI bus combines the user data into predetermined bytes desired by a frame relay packet. When the combining to the predetermined byte is completed, the HDLC control unit 316 adds the header information of the frame relay packet provided from the main processor 310 to the combined predetermined byte of user frame data to generate a complete frame relay packet. do.

The generated frame relay packet is output from the HDLC control unit 316, and the output frame relay packet is transmitted to the frame relay side.

Meanwhile, in the above, the main processor 310 generates the header information of the frame relay packet using the header information of the ATM cell, and the subprocessor 320 generates the header information of the ATM cell using the header information of the frame relay packet. The operation according to an embodiment of the present invention has been described as performing a function.

However, as another embodiment of the present invention, the main processor 310 generates the header information of the ATM cell using the header information of the frame relay packet, and the subprocessor 320 uses the header information of the ATM cell to frame the packet relay packet. It will be obvious that the implementation can be performed to perform the function of generating the header information.

As described above, the present invention has an effect of improving the processing performance of the companion device as the two processors share and process the load generated by the interworking between the frame relay and the asynchronous transmission mode. In addition, as the performance of the interworking apparatus is improved, it is possible to accommodate a high speed subscriber link, and there is an advantage of accommodating a lot of low speed subscriber links.

Claims (4)

In the interlocking device employing the internal connection bus, Converts the frame relay header information provided from the high level data link controller to the AT cell header information and outputs it to the main processor local bus, and converts the frame relay header information provided through the main processor local bus to the high level data link controller. Providing the main processor, AMT cell header information provided from a cell division / assembly control unit is converted into frame relay header information to be output to a subprocessor local bus, and AMT cell header information provided through the subprocessor local bus is converted into the cell division / assembly control unit. With a subprocessor, And a frame relay configured to communicate internally between the frame relay header information and the AT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor. And interlocking device in asynchronous transmission mode. In the interlock device of the frame relay and asynchronous transmission mode, Internal connection bus, A high level data link controller having an internal access bus interface for decomposing or assembling frame relay packets into header information and user frame data; A cell dividing / assembly control unit having an internal access bus interface for dividing or assembling an AT cell into header information and user data; A packet memory for storing the user frame data provided from the high level data link controller and the user data provided from the cell division / assembly control unit in common; An internal access bus memory bridge performing a bridge function between the packet memory and the internal access bus; The main processor local bus, Subprocessor local bus, A first internal connection bus bridge for performing a bridge function between the main processor local bus and the internal connection bus; A second internal connection bus bridge for performing a bridge function between the subprocessor local bus and the internal connection bus; Converts the frame relay header information provided from the high level data link controller to AMT cell header information and outputs it to the main processor local bus, and converts the frame relay header information provided through the main processor local bus to the high level data link. The main processor to the controller, AMT cell header information provided from the cell division / assembly control unit is converted into frame relay header information and output to the subprocessor local bus, and AMT cell header information provided through the subprocessor local bus is divided into the cell division / assembly. A subprocessor provided to the assembly control unit, And a frame relay configured to communicate internally between the frame relay header information and the AT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor. And interlocking device in asynchronous transmission mode. In the interlocking device employing the internal connection bus, Outputs the frame relay header information provided from the high level data link controller to the main processor local bus, converts the AMT header information provided through the main processor local bus to the frame relay header information, and provides the same to the high level data link controller. The main processor, Outputs the AMT cell header information provided from the cell division / assembly control unit to the subprocessor local bus, converts the frame relay header information provided through the subprocessor local bus into the AMT header information, and sends the Providing the main processor, And a frame relay configured to communicate internally between the frame relay header information and the AT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor. And interlocking device in asynchronous transmission mode. In the interlock device of the frame relay and asynchronous transmission mode, Internal connection bus, A high level data link controller having an internal access bus interface for decomposing or assembling frame relay packets into header information and user frame data; A cell dividing / assembly control unit having an internal access bus interface for dividing or assembling an AT cell into header information and user data; A packet memory for storing the user frame data provided from the high level data link controller and the user data provided from the cell division / assembly control unit in common; An internal access bus memory bridge performing a bridge function between the packet memory and the internal access bus; The main processor local bus, Subprocessor local bus, A first internal connection bus bridge for performing a bridge function between the main processor local bus and the internal connection bus; A second internal connection bus bridge for performing a bridge function between the subprocessor local bus and the internal connection bus; Outputs the frame relay header information provided from the high level data link controller to the main processor local bus, converts the AMT header information provided through the main processor local bus into frame relay header information, The main processor, Outputting AMT cell header information provided from the cell division / assembly control unit to the subprocessor local bus, and converting frame relay header information provided through the subprocessor local bus into AMT header information to divide the cell. A main processor serving as an assembly control unit, And a frame relay configured to communicate internally between the frame relay header information and the AT header information between the main processor local bus and the subprocessor local bus by instructions of the main processor and the subprocessor. And interlocking device in asynchronous transmission mode.