KR20000065431A - Word line driver - Google Patents

Abstract

PURPOSE: A word line driving apparatus is provided which performs a stable wafer burn-in test operation without increasing the design area and cost. CONSTITUTION: A word line driving apparatus controls the power by adding a switch in a power line inputted to each decoding part commonly instead of comprising an additional transistor operated during the burn-in test mode at every decoding part(42,44) and boosting signal generation part(46). The word line driving apparatus is used in driving a number of word lines simultaneously in order to reduce the test time during the burn-in test operation in a semiconductor memory device. The apparatus performs the burn-in test operation rapidly without increasing the area, and the apparatus also stabilizes the operation of the circuit by reducing the voltage drop by using a voltage in a level of a power source voltage as a driving voltage.

Description

Word line driver {Word line driver}

The present invention relates to a word line driving apparatus used to simultaneously drive a plurality of word lines during a burn-in test operation in a semiconductor memory device, and more particularly, a transistor provided for each wafer burn-in test. The present invention relates to a word line driving apparatus which performs the same burn-in test operation at high speed without increasing the area by removing and instead of providing a common control switch to a power line which is commonly input to each decoding unit.

In general, the burn-in test operation of a memory device is a device in which voltage and ambient temperature are applied to a more severe stress than actual use conditions for the entire DRAM device in order to detect early defects of the device itself. It means to detect the change in the characteristics of, to drive a plurality of word lines at the same time to give a burn-in stress (burn-in stress) in the wafer (wafer) state.

FIG. 1 is a block diagram schematically illustrating a conventional word line driving apparatus, and a hierarchical decoding method generally used for word line selection will be described with reference to the drawings.

First, when a row address signal (X-add1 or X-add2) is input from the outside and one main decoding unit 12 is selected, the output signals MWL1 and MWL2 of the main decoding unit 12 are connected to the rear stage. The sub decoding unit 14 is input to the sub decoding unit 14, wherein only one of the plurality of sub decoding units 14 is applied with the boosting signals px1 and px2 in an active state, so that one word of the plurality of word lines WL1 to WL4 is applied. Line) is selected. In the figure, the number of the sub decoding units 14 connected to the single main decoding unit 12 is simply shown as two.

In general, a signal transmitted in the same direction as the word line is called a main word line signal (Main Word Line (MWL)) and a signal transmitted in a vertical direction with the word line is called a boosting signal (px, / px). The line driving control signal may be transmitted through the boosting signals px and / px or may be transmitted from the main decoding unit 12.

In the present specification, the word line driving control signal will be described as a case where the main decoding unit is transmitted.

FIG. 2 shows a circuit diagram of a word line driving apparatus conventionally used for driving a plurality of word lines for a wafer burn-in test. The input row address signals ax23 to ax67 are shown in FIG. A main decoder 22 for decoding and selecting one main word line MWL; A plurality of sub-decoders 24 are applied to each of the power supply voltages through the selected main word line MWL and receive a boosting signal (px, / px), which is a driving control signal, to be selectively activated to select a single word line. In the figure, only one sub decoding unit 24 is shown, but it is common that a plurality of sub decoding units having the same structure at the rear end and connected in parallel to each other are connected); A boosting signal generator that receives a part of the row address signal ax01 and generates a boosting signal (px, / px) in an active state in only one of the plurality of sub-decoders 24 to select one word line. It is provided with 26.

The word line driving device having the above configuration selects the main word line using the input row address signal, and the selected main word line signal is transferred to the sub decoding unit supplying the driving potential to the word line, thereby boosting the boosting signal as the driving control signal. The word line is put into an operation state only where it is applied, and the word line which is not in the sub decoding unit is controlled to remain in the standby state.

At this time, the boosting signal generator 26 outputs an activated signal to only one pair of N pairs of boosting signals applied to the N sub decoders when a plurality of N sub decoders are connected to the main word line. And the rest to maintain the standby signal. For example, when the word line WL is selected, the main word line signal MWL is selected as the high state, and the boosting signal is operated by changing px = high and / px = low, respectively.

In addition, the word line driving device having the above configuration has a feature that can drive a plurality of word lines at the same time. In the related art, a separate transistor that operates in a test mode for each main decoding unit 22 for this operation (FIG. 2). It is used for the simultaneous driving of the word line. In the case of the boosting signal (px, / px), a separate transistor (shown as T2 in FIG. 2) simultaneously operating in the test mode was provided for each boosting signal generator 26 to simultaneously perform word lines. .

The transistor T1 is connected to each main decoding unit 22 so that the transistor T1 is turned off during normal operation and does not operate. A signal indicating a test mode is applied during a test (wafer burn-in test) operation. By turning on, all main word line (MWL) signals connected to it are enabled, allowing multiple word lines to be selected simultaneously.

Similarly, the transistor T2 is connected to each boosting signal generator 26 so that a signal indicating a test mode is applied only during a test (wafer burn-in test) operation without being turned off during normal operation. By turning on, all word lines connected to it are selected.

FIG. 3 is a timing diagram of an operation in the test mode of the word line driving apparatus shown in FIG. 2. As shown in (b), the row address signal axij is applied in a 'low' state, and (a) In the situation where the word line driving control signal xdp shown transitions to 'high' at the time t1, the control signal test for entering the test mode is changed to the 'high' state as shown in (c). When transitioned and applied, the transistor T1 in the main decoding unit 22 is turned on to drop the potential of the node N1 to 'logic low'.

As shown in (d), the potential signal of the node N1 turns on the PMOS transistor MP1 constituting the CMOS-type inverter connected to the rear end, and applies the high voltage Vpp applied to the source terminal thereof as shown in (d). At the same time, a control signal test for notifying the entry into the test mode transitioned to the high level is also applied to the transistor T2 in the boosting signal generator 26 so that the boosting signal is px = high. , / px = row to pass to the secondary decoding unit 24 at the rear end.

Subsequently, the sub decoding unit 24 receives a main word line (MWL) signal having a high potential (Vpp) level applied to a power supply by being controlled by a boosting signal (/ px) applied at a low level. The word line WL is boosted and driven as shown in (f).

However, as described above, in the conventional burn-in test operation, a plurality of word lines are controlled to be simultaneously driven by separate transistors T1 and T2 provided for each of the main decoding unit 22 and the boosting signal generator 26. Since the word line driving device has a problem that the decoding circuit is a circuit that is frequently used repeatedly throughout the device, it acts as a significant design area burden and cost burden.

In addition, in the test mode, a voltage having a high potential (Vpp) level is used to drive a plurality of word lines, so that the voltage drop is severe and the circuit operation becomes unstable.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a common input to each decoding unit instead of having separate transistors operating in the burn-in test mode for each decoding unit and boosting signal generator. The present invention provides a word line driving apparatus that performs stable wafer burn-in test operation in the same manner without increasing design area and cost by controlling power by adding a switch to a power line.

In order to achieve the above object, the word line driving apparatus according to the present invention includes a main decoding unit for receiving a row address signal according to the state of the word line driving control signal and decoding it to select one main word line;

A plurality of sub decoding units connected to a main word line selected by the main decoding unit to respective power supply voltage applying stages, receiving a word line boosting signal, and selectively activating the sub word lines;

A boosting signal generator which receives a portion of the row address signal and generates a boosting signal in an active state only by one of the plurality of sub-decoders to select one word line;

Each of the main word line and the sub word line is driven in an active state in the test mode when the potential supplied to the power terminals of the main decoding unit and the boosting signal generator is controlled in accordance with a control signal indicating the entry into the test mode. First and second electric potential adjusting parts for adjusting the electric potential level to be electric potential levels;

According to a control signal indicating the entry into the test mode, the potential level supplied to the other power supply terminal of the main decoding unit is controlled to be a differential potential level for each operation mode and test mode, thereby reducing the voltage drop during the word line driving in the test mode. And a reduced voltage drop reduction unit.

1 is a block diagram schematically illustrating a word line driving apparatus used in the related art.

2 is a circuit diagram of a word line driver conventionally used for driving multiple word lines for wafer burn-in testing.

3 is an operation timing diagram in a test mode of the word line driver shown in FIG.

4 is a circuit diagram of a word line driving apparatus according to the present invention.

FIG. 5 is an operation timing diagram when entering the test mode of the word line driver shown in FIG.

<Explanation of symbols for main parts of drawing>

10, 40: memory cell arrays 12, 22, 42: main decoding section

14, 24, 44: sub decoding unit 26, 46: boosting signal generating unit

47, 48: potential adjuster 49: voltage drop reducer

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram of a word line driving apparatus according to the present invention. The row address signals ax23 to ax67 are received and decoded according to the state of the word line driving control signal xdp. A main decoder 42 for selecting one word line MWL; The main word line MWL selected by the main decoding unit 42 is connected to each of the power supply voltage applying stages, and is selectively activated by receiving the word line boosting signals px and / px and corresponding sub word lines SWL. A plurality of sub decoding sections 44 (only one is shown for simplicity in the drawing); A boosting signal generator 46 which receives a part of the row address signal ax01 and generates a boosting signal in an active state only by one of the plurality of sub decoding units 44 so as to select one sub word line SWL. )Wow; When the electric potential supplied to the power terminals N1 and N2 of each of the main decoding unit 42 and the boosting signal generator 46 is controlled in accordance with the control signal test indicating the entry into the test mode, First and second potential adjusting units (47, 48) for adjusting each of the main word line (MWL) and the sub word line (SWL) to a potential level for driving the activated state; The potential level supplied to the other power supply terminal N3 of the main decoding unit 42 according to the control signal (test) indicating the entry into the test mode is the differential potential level for each operation mode and test mode (Vpp in the operation mode). And a voltage drop reduction unit 49 which controls the voltage to be Vcc in the test mode and performs a voltage drop when driving the word line in the test mode.

The main decoding unit 42 is connected between the power supply terminal N1 and the node N4 to which the power supply voltage whose potential level is adjusted for each operation mode and test mode is supplied by the first potential control unit 47. A PMOS transistor MP1 to which a word line driving control signal xdp is applied to a gate end; A plurality of NMOS transistors MN1 to MN3 connected in series between the node N4 and a ground terminal and to which row address signals ax23, ax45, and ax67 are applied to respective gate terminals; The potential of the node N4 is applied to each gate terminal, and is provided between the power supply terminal N3 and the ground terminal to which a power supply voltage is supplied at an optional potential level Vpp, Vcc by the voltage drop reduction unit 49. And a PMOS transistor MP2 and an NMOS transistor MN4 connected in series by the main word line MWL.

The main decoding unit 42 having the above-described configuration generates a signal for selecting a main word line (MWL) using the row address signals ax23 to ax67 input.

In addition, the sub decoding unit 44 is connected in series between the main word line MWL connected to the output terminal of the main decoding unit 42 by a sub word line SWL, and the boosting signal generating unit ( A PMOS transistor MP3 and an NMOS transistor MN5 to which a boosting signal / px output from 46 is applied to each gate terminal; The NMOS transistor MN6 is connected between the main word line MWL and the sub word line SWL, and the boosting signal px output from the boosting signal generator 46 is applied to the gate terminal. do.

Each sub decoding unit 44 having the above configuration is applied with the main word line (MWL) signal selected by the main decoding unit 42 as the power supply voltage, and the boosting signals px and / px are activated. The sub word line is put into an operation state only at the incoming position, and the remaining sub decoding unit controls the sub word line to stay in the standby state.

In addition, the boosting signal generator 46 includes a NAND gate NAND1 to which a part of the row address signal ax01 is applied to one input terminal; A PMOS transistor MP4 and an NMOS transistor MN7 having an output signal of the NAND gate NAND1 applied to each gate terminal, and connected by a node N5 between a high voltage Vpp applying terminal and a ground terminal; A PMOS transistor MP5 connected to the gate terminal of the potential of the node N5 by a node N6 between an output terminal N2 of the second potential adjusting unit 48 and a ground terminal; An NMOS transistor MN8 is provided, and each of the nodes N5 and N6 generates a boosting signal px and / px having mutually inverted signal values.

The boosting signal generator 46 having the above configuration outputs an activated boosting signal pair (px, / px) for only one of the plurality of sub decoding units 44 connected to the selected main word line MWL, and the rest of the boosting signal generator 46 For the operation, a boosting signal pair in a standby state is generated.

The first and second potential adjusting units 47 and 48 are connected between the high voltage Vpp applying terminal and the ground terminal by the nodes N1 and N2, respectively, and control signals for entering the test mode. It consists of PMOS transistors (MP6 and MP7, respectively) and NMOS transistors (MN9 and MN10, respectively) operating under the test.

In addition, the voltage drop reduction unit 49 is supplied with a control signal (test) indicating the entry into the test mode, the high voltage (Vpp) applying stage and the other power terminal (N3) of the main decoding unit 42. A first PMOS transistor MP8 coupled between the first PMOS transistor MP8; A control signal test for entering the test mode is applied through an inverter IV1 and an inverted signal is applied to a gate terminal, and a power supply voltage Vcc is applied and the other power supply terminal N3 of the main decoding unit 42. Is provided with a second PMOS transistor MP9 connected therebetween.

FIG. 5 illustrates an operation timing diagram when entering the test mode of the word line driving apparatus illustrated in FIG. 4. Hereinafter, operation of each mode of the word line driving apparatus according to the present invention will be described in detail with reference to the drawings.

First, as shown before the time point t1 of the figure, in the normal operation mode, a control signal (test) informing the entry into the test mode input to the first and second potential adjusting units 47 and 48 is provided. It is applied in the inactive state (logic low) and turns on the PMOS transistors MP6 and MP7, respectively, so that the high voltage Vpp is output to the output terminals N1 and N2 ((c) and (d)). Shown in).

Accordingly, high voltage Vpp is applied to the power terminals of the main decoding unit 47 and the boosting signal generator 48.

On the other hand, during the burn-in test operation (see also the operation timing from the time point t1 to the time point t2 in the figure), as shown in (c), the control signal test for entering the test mode is activated (logic). While transitioning to high), each of the NMOS transistors MN9 and MN10 in the first and second potential adjusting units 47 and 48 is turned on to generate a 'logic low' potential signal, respectively.

Thus, as shown in (d), a signal of 'logic low' is applied to each of the power terminals N1 and N2 in the main decoding unit 42 and the boosting signal generator 46.

At the same time, the control signal test for entering the test mode is also applied to the voltage drop reduction unit 49 to turn on the PMOS transistor MP9 connected to the power supply voltage Vcc applying stage. The other power supply terminal N3 in the main decoding section 42 supplies a potential of the power supply voltage Vcc level as shown in (e).

In addition, the main decoding unit 42 which is supplied with the logic low level potential by the first potential adjusting unit 47 is initialized to the logic low level by the word line driving control signal xdp. The threshold potential Vt is transferred to the node N4 via the turned-on PMOS transistor MP1 (shown in (f)), which turns on the PMOS transistor MP2 connected to the rear stage. The potential at the power supply voltage Vcc level applied to the power supply terminal N3 is transferred to the main word line MWL as shown in (g) to drive the word line.

As described above, the voltage drop reducing unit 49 drives the word line at the power supply voltage Vcc level instead of the high voltage Vpp in the test mode, and thus lowers the voltage drop than when the word line was driven at the previous high voltage Vpp. The degree of voltage drop can be reduced, so that the circuit operation can be performed with such stability.

On the other hand, the second potential adjusting section 48 is also the same operation as the first potential adjusting section 47, the power supply voltage applied via the node (N2) to the boosting signal generator 46 in the test mode. By adjusting the ground voltage level of 'logic low', the potential of the boosting signal (/ px) is generated at the 'logic low' level and transferred to the sub decoding unit 44.

Accordingly, the PMOS transistor MP3 in the sub decoding unit 44 is turned on so that the corresponding sub word line SWL has the same potential Vdd as the main word line MWL as shown in (j). It will be boosted to the level and driven for selection.

In the embodiment of the present invention, the word line driving potential is applied by the main word line decoding unit. However, in another embodiment of the present invention, the word line driving potential may be applied by the boosting signal generator.

As described above, according to the word line driving apparatus according to the present invention, the design area and the cost burden can be reduced by eliminating and implementing the transistors required for the main decoding unit and the boosting signal generation unit for the burn-in test operation. There is a very good effect.

In addition, since the word line driving voltage in the test mode can be used as a power supply voltage rather than a high voltage level, the voltage drop can be reduced to further stabilize circuit operation.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (4)

A main decoding unit which receives a row address signal according to a state of a word line driving control signal and decodes the row address signal to select one main word line; A plurality of sub decoding units connected to a main word line selected by the main decoding unit to respective power supply voltage applying stages, receiving a word line boosting signal, and selectively activating the sub word lines; A boosting signal generator which receives a portion of the row address signal and generates a boosting signal in an active state only by one of the plurality of sub-decoders to select one word line; Each of the main word line and the sub word line is driven in an active state in the test mode when the potential supplied to the power terminals of the main decoding unit and the boosting signal generator is controlled in accordance with a control signal indicating the entry into the test mode. First and second electric potential adjusting parts for adjusting the electric potential level to be electric potential levels; According to a control signal indicating the entry into the test mode, the potential level supplied to the other power supply terminal of the main decoding unit is controlled to be a differential potential level for each operation mode and test mode, thereby reducing the voltage drop during the word line driving in the test mode. And a voltage drop reducing part for reducing the word line driving device. The method of claim 1, The first potential adjusting unit may include a PMOS transistor configured to receive a control signal for entering the test mode to a gate terminal and be connected between a high voltage applying stage and a power supply terminal of the main decoding unit; And a NMOS transistor connected between a power supply terminal and a ground terminal of the main decoding unit, the control signal informing that the test mode is entered into the gate terminal. The method of claim 1, A second PMOS transistor configured to receive a control signal for entering the test mode to a gate terminal and be connected between a high voltage applying stage and a power supply terminal of the boosting signal generator; And a NMOS transistor connected between a power supply terminal and a ground terminal of the boosting signal generation unit, the control signal informing that the test mode is entered into the gate terminal. The method of claim 1, The voltage drop reduction unit may include a first PMOS transistor configured to receive a control signal informing of entering the test mode to a gate terminal, and to be connected between a high voltage applying stage and another power supply terminal of the main decoding unit; And a second PMOS transistor connected between a power supply voltage supply terminal and another power supply terminal of the main decoding unit, the inverted signal of the control signal informing the entry of the test mode to the gate terminal.