KR20000061507A - Apparatus for indivisual control of pci bus clock frequency - Google Patents

Abstract

PURPOSE: An individual PCI bus clock frequency controller is provided to generate an optimal clock for each PCI device without a conventional structure of the PCI devices so that it can enhance the operation speed of the PCI device. CONSTITUTION: An individual PCI bus clock frequency controller comprises a local bus, a peripheral bus, peripherals, a system controller(158), and a clock generator(180). The peripherals, more than one, stores a clock frequency information at a command register. The system controller(158), connected between the local bus and the peripheral bus, generates an individual clock control signal corresponding to each clock information stored in the peripherals. The clock generator(180), connected to the system controller(158), generates a plurality of local clocks and peripheral clocks, and generates the individual clock for each peripheral in response to the clock control signal.

Description

Individual control device for PCI bus clock frequency {APPARATUS FOR INDIVISUAL CONTROL OF PCI BUS CLOCK FREQUENCY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling the clock frequency of a data bus provided in a computer system, and more particularly, to a method for individually controlling the PCI bus clock frequency.

Peripheral Component Interconnect (PCI) is the latest high-bandwidth processor-independent bus that can function as a peripheral bus. Compared to other common bus specifications, PCI provides higher system performance for high-speed I / O subsystems (eg, graphic display adapters, network interface controllers, disk controllers, etc.). In the current standard, up to 64 data lines can be used at 33 MHz, resulting in transmission rates of 264 Mbytes / sec or 2.112 Gbps.

1 is a block diagram showing the configuration of a general computer system.

Referring to FIG. 1, computer system 100 generally includes a CPU local bus, a Peripheral Component Interconnect bus (PCI), and an Industry Standard Architecture bus (ISA) bus. A central processing unit (CPU) 50 is connected to the local bus, and a host-to-PCI bridge 51, a cache 52, and a memory 53 are connected between the local bus and the PCI bus. The PCI bus is connected with a plurality of PCI slots 61-64 in which devices for PCI are mounted. A PCI-to-ISA bridge 60 is connected between the PCI bus and the ISA bus. Then, ISA devices 70 such as audio 71, keyboard 72 and BIOS 73 are connected to the ISA bus.

FIG. 2 is a block diagram showing the configuration of the PCI-to-ISA bridge shown in FIG. 1.

Referring to FIG. 2, the PCI-to-ISA bridge 60 is connected to a PCI bridge 58 to which a hard disk, a CD-ROM, a universal serial bus (USB), or the like is connected, and to the operation of the computer system 100. A system controller 59 for controlling the clock is included.

3 is a block diagram illustrating a control method of a PCI bus clock frequency according to the prior art.

Referring to FIG. 3, the clock generator 80 generates a local clock, a PCI clock, and an ISA clock in response to a control signal of the system controller 59 via an SMB (I ² c bus) that performs serial data transfer. . The clock generator 80 is connected to each device requiring each clock. Devices that use the highest clock, the local clock (typically 60-100 MHz), have a CPU (50), a system controller (59), a cache (52), and a memory (53), and use a PCI clock that uses half of the local clock. Devices used include PCI cards mounted in PCI bridge 58 and PCI slots 61-64. A device using an ISA clock, which is an asynchronous clock (14.31818 MHz), includes an ISA device 70 such as audio 71, keyboard 72, BIOS 73, and the like shown in FIG. In general, clock generator 80 generates 12-16 local clocks, 5-7 PCI clocks, and 2-3 ISA clocks. The PCI clock is used by adjusting from 33.33MHz to 25MHz according to the PCI standard. In general, if the local clock is 66.66 MHz, the PCI clock is 33.33 MHz, and if the local clock is 60 MHz, the PCI clock is adjusted to be 30 MHz. However, for example, if the local clock rate is 100 MHz, the PCI clock is 30 MHz instead of half of that 50 MHz. That is, since the PCI clock speed is limited by the PCI standard, even if the speed of the local bus increases, there is a problem that cannot exceed the clock speed limit determined by the PCI standard.

Recently, many efforts have been made to change the clock speed of the PCI bus to 66 MHz. Currently, a PCI architecture has been developed that can increase the clock speed of the PCI bus to 66 MHz, but it is rarely used because the structure of the slot is different from that of the conventional PCI bus. In addition, even if a PCI card having a speed of 66 MHz is used, this is very limited because it is limited to a computer and a PCI card having a slot structure for 66 MHz. And even if this 66MHz slot structure has the same structure as the existing slot structure, if the slow (33MHz) operating peripheral devices are connected in the PCI bus, the current PCI clock is uniformly controlled, Restrictions follow. In other words, if a PCI clock is controlled at 66 MHz, a PCI card with a 33 MHz speed will cause a problem. If the clock speed is controlled at 33 MHz, a PCI card with a 66 MHz speed will be lost. . Accordingly, there is a need for an apparatus and method capable of increasing the PCI clock speed according to the characteristics of each PCI card without changing the conventional structure such as the slot structure.

Accordingly, an object of the present invention is to provide a device capable of improving the PCI clock speed by individually controlling the PCI clock speed for each PCI peripheral device, without changing the existing structure of the PCI devices. .

1 is a block diagram showing the configuration of a general computer system;

2 is a block diagram showing the configuration of the PCI-to-ISA bridge shown in FIG.

3 is a block diagram showing a control method of a PCI bus clock frequency according to the prior art;

4 is a view illustrating a command register of a PCI setting unit included in a PCI device; And

Figure 5 is a block diagram showing a control method of the PCI bus clock frequency in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

150: CPU 152: cache

153: memory 158: PCI bridge

159: System Controller 161-164: PCI Slot

170: ISA device 180: clock generator

According to a feature of the present invention for achieving the object of the present invention as described above, the individual control device of the PCI bus clock frequency, a local bus, a peripheral bus, a plurality of peripheral devices, It includes a system controller and a clock generator. The peripheral devices are connected to a peripheral bus and have clock frequency information stored in a command register. The system controller is connected between a local bus and a peripheral bus and generates a separate clock control signal corresponding to clock frequency information stored in the peripheral devices. The clock generator is connected to the system controller to generate a plurality of local clocks and peripheral clocks, and generates a separate clock for each peripheral device in response to the clock control signal. The clock frequency information is stored in a 6-bit reserved region included in the command register of the peripheral device. The system controller individually controls the peripheral clock speed in response to the clock frequency information of each peripheral device, and controls the lowest clock speed among the peripheral clock speeds when the clock frequency information is not set in the command register. Peripheral buses include a PCI bus and an ISA bus, and peripheral clocks include a PCI clock and an ISA clock.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 5.

The apparatus for individually controlling the novel PCI bus clock frequency of the present invention includes a system controller and a clock generator for generating a plurality of local clocks, PCI clocks and ISA clocks in response to control signals from the system controller. . Among them, clock frequency information is set in a command register of each of the PCI devices using the PCI clock. The system controller generates a control signal for individually controlling the PCI clock in response to the respective set frequency information, and the clock generator generates the clock for each PCI device separately in response to the control signal.

4 is a diagram illustrating a command register of a PCI setting unit included in a PCI device.

The structure of the PCI has a setting area of 256 bytes for informing the PCI device itself of its configuration and operation status. This includes a 16-bit command register. As shown in FIG. 4, each function is defined for each bit in the command register. Six bits corresponding to the tenth to fifteenth bits are defined as reserved regions. If you set these 6 bits from 0, up to 63 can be set. At this time, if these 6 bits add 20 to each value (0-63) to represent the PCI clock frequency of the PCI card at least 20 MHz, the value becomes 20 MHz to 83 MHz. That is, a PCI card can store, in the manufacture of a PCI card, the maximum PCI clock frequency it can use in a 6-bit spare area in the frequency range of 20 MHz to 83 MHz.

The maximum available PCI clock frequency of the PCI card stored as described above is generated by the system controller and the clock generator according to the present invention, and corresponding PCI clock frequencies are generated according to the detected information. Detailed description thereof is as follows.

5 is a block diagram illustrating a control method of a PCI bus clock frequency according to the present invention.

Referring to FIG. 5, an apparatus for individually controlling the PCI bus clock frequency according to the present invention includes a system controller 159 and a plurality of local clocks and PCI clocks in response to control signals from the system controller 159. And a clock generator 158 generating an ISA clock. Among them, a device using a PCI clock includes PCI cards mounted in the PCI bridge 158 and the PCI slots 161-164, each of which has a reserved region of the command register as shown in FIG. The maximum PCI clock frequency information of each PCI card is set. The system controller 159 receives each set frequency information from the spare area, and individually controls the clock of the clock generator 158 to match each PCI device to generate an optimal clock. At this time, if there is no frequency information set in the spare area of the PCI device, the system controller 159 arbitrarily sets the clock frequency of the PCI device to the minimum PCI clock frequency. This is because, when the correct clock information of the PCI card is not known, a low PCI clock frequency may be used to prevent the PCI card from being damaged or malfunctioned.

As such, the system controller 159 receives PCI clock information for each PCI device and individually controls the corresponding clock of the clock generator 158 to match each PCI device, thereby changing the existing PCI structure. The PCI clocks can be controlled individually and can generate an optimal clock. As a result, the operating speed of PCI devices is further improved.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, it is possible to generate the optimum clock for each PCI device by controlling the PCI clocks individually, without changing the existing structure of the PCI devices, thereby further improving the operation speed of the PCI devices do.

Claims (4)

In a computer system: A local bus; A peripheral bus; One or more peripheral devices coupled to the peripheral bus and having clock frequency information stored in a command register; A system controller coupled between the local bus and the peripheral bus to generate an individual clock control signal corresponding to the clock frequency information stored in the peripheral devices; And A PCI bus clock frequency coupled to the system controller, the clock generator generating a plurality of local clocks and peripheral clocks, the clock generator generating an individual clock for each peripheral device in response to the clock control signal. Individual control units. The method of claim 1, And the clock frequency information is stored in a 6-bit reserved region included in the command register of the peripheral device. The method of claim 1, The system controller individually controls peripheral clock speeds in response to clock frequency information of each peripheral device, and when the clock frequency information is not set in the command register, the lowest speed among peripheral clock speeds. Individual control device for the PCI bus clock frequency, characterized in that the control. The method of claim 1, The peripheral bus includes a PCI bus and an ISA bus, and the peripheral clock includes a PCI clock and an ISA clock. Individual control of the PCI bus clock frequency.