KR20000061477A - Adder - Google Patents

Abstract

PURPOSE: An adder is provided to reduce a propagation delay of a carry by a simple logic and also reduce a critical path of a carry causing the propagation delay so that it can make a design easy and perform a data process with a high speed when implementing a 32, 64 or more bit adder. CONSTITUTION: An adder comprises a high carry adder(40), a low carry adder(41), the first multiplexer(42) and the second multiplexer(43). The high carry adder(40) receives a high-in carry input signal, adds two data at the same bit figure, and outputs an addition value and a carry. the low carry adder(41) receives a low-in carry input signal, adds two data at the same bit figure, and outputs an addition value and a carry. The first multiplexer(42) receives the addition values from the high carry adder(40) and the low carry adder(41), and multi-transmits them by the carry input signal. The second multiplexer also receives the addition values from the high carry adder(40) and the low carry adder(41), and multi-transmits them by the carry input signal.

Description

Adder {ADDER}

The present invention relates to an adder, and more particularly, to an adder capable of processing data at high speed by eliminating propagation delay caused by a carry.

Fig. 1 is a circuit diagram showing the structure of a conventional adder. As shown therein, the carry input signals C (1) to C (n) and the data of the same bit position (A (1) to A (n)), ( A plurality of full adders that add B (1) to B (n) and output corresponding values S (1) to S (n) and carry (C (2) to C (n + 1)) FA1 to FAn are sequentially connected to each other, and the operation of the conventional apparatus will be described.

First, the Boolean function by the addition values S (1) to S (n) and the carry C (1) to C (n + 1) for the adder can be expressed as follows.

S (n) = A (n) + B (n) + C (n) --------- Equation (1)

C (n + 1) = A (n) B (n) + {A (n) + B (n)} C (n) ------- Equation (2)

Here, we define generation and propagation as follows.

G (Generation) = A (n) B (n), P (Propagation) = A (n) + B (n), and using this, carry (C (1) ~ C (n + 1)) The addition values S (1) to S (n) change as follows.

S (n) = P (n) + C (n) ------- Equation (3)

C (n + 1) = G (n) + P (n) C (n) --------- Equation (4)

When the circuit is constructed based on the above formulas (3) and (4), the circuit is shown as shown in Figs. 2 and 3, and as shown in Fig. 2, the addition values S (1) to S (n) are obtained. Except for 0), the propagation delays of all addition values S (1) to S (n) are the same.

In other words, all propagation and generation are made after one gate delay and all carry (C (1) to C (n)) except the last carry (C (n + 1)). Is created after two gate delays after the Propagation and Generation are generated.

Further, all addition values S (1) to S (n) except the first addition value S (0) are made after one gate delay after the carry generation, and the first addition value S (0) Except), all addition values S (1) to S (n) have the same propagation delay.

However, in the conventional apparatus operating as described above, as the number of bits increases, the number of inputs of the high order gate increases, causing problems with fan-in and fan-out, and also reducing the number of inputs for gates with many fan-in or fan-out. If a gate is used, as many gates must be added, and if the number of bits increases, the look-ahead carrier becomes complicated, which causes a problem in design.

Accordingly, an object of the present invention is to provide an adder capable of processing data at high speed by eliminating a propagation delay caused by a carry.

1 is a block diagram showing the configuration of a conventional adder.

2 is a circuit diagram showing a configuration of a conventional carry look ahead adder.

FIG. 3 is a circuit diagram showing a configuration of car generation in FIG.

Figure 4 is a circuit diagram showing the configuration of one embodiment of the adder of the present invention.

Fig. 5 is a circuit diagram showing the construction of another embodiment of the adder of the present invention.

***** Description of the symbols for the main parts of the drawings *****

1 to n: Computation part 40: High carry part

41: Low Carry Adder 42,43: First and Second Multiplexers

In order to achieve the above object, the present invention receives a high carry input signal and adds two data of the same bit position, and outputs an add value and a carry according thereto, and a low carry input signal. A low carry adder which receives two inputs of the same bit digit and adds the added value and the carry, and receives the added value from the high carry adder and the low carry adder, and multiplies them by a carry input signal. And a plurality of arithmetic units comprising a first multiplexer to transmit, and a second multiplexer which receives a carry from the high carry adder and a low carry adder and transmits the multiplied by the carry input signal.

Hereinafter, the operation and effects on the adder according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a circuit diagram showing an embodiment of the adder of the present invention. As shown therein, a carry input signal C1 that is high is received, and two data A1 and B1 of the same bit digit are added. The high carry adder 40 outputting the added value S1 and the carry C2, and the carry input signal C1, which is low, receive two data A1 and B1 of the same bit position. Input the added value S from the low carry adder 41 and the high carry adder 40 and the low carry adder 41 to add and output the added value S1 and the carry C2 accordingly. Receives a carry from the first multiplexer 42 and the high carry adder 41 and the low carry adder 42 to multiply and transmit it by the carry input signal C1 to the carry input signal C1. By a second multiplexer 43, which is multi-transmitted by means of a plurality of arithmetic units 1-1 and a plurality of arithmetic units 1, n) are connected and configured, and the operation of the present invention configured as described above will be described using the first calculation unit 1 as an example.

First, the high carry adder 40 assumes that the carry input signal C1 is low, and adds the carry and add values to the first and second multiplexers by adding the data of the same bit positions to the values A1 and B1. 42 and 43, and the low carry adder 41 similarly assumes that the carry input signal C1 is low and adds the carry and addition values to the first and second values by adding the same value to the data values of the same bit positions. Output to multiplexers 42 and 43.

If the carry input signal C1 is actually low, the carry calculated by the low carry adder 41 becomes the output signal C2 of the second multiplexer 43, and then the carry input signal of the next calculation unit 1-2. It is inputted as (C2).

At this time, if the carry input signal C1 is high, the carry calculated by the high carry adder 40 becomes the output signal C2 of the second multiplexer 43, and then the carry input signal of the next calculation unit 2 ( C2).

On the contrary, if the carry input signal C1 is low, the addition value added by the low carry adder 41 is output as the output signal S1 of the first multiplexer 42, and the carry input signal C1 is high. The addition value added by the high carry adder 40 is output as the output signal S1 of the first multiplexer 42.

5 is a circuit diagram showing another embodiment of an adder configured with 4 bits. The low carry adder 50 to 53 assumes that the first carry input signal C1 is low and calculates up to 4 bits accordingly. The addition value and the carry are applied to the first and second multiplexers 58 and 59. Similarly, the high carry adder 54 to 57 calculate up to 4 bits by assuming that the carry input signal C1 is low. The added value and carry are applied to the first and second multiplexers 58 and 59.

Subsequently, when the actual carry input signal C1 is low, the first multiplexer 58 selects and outputs addition values S1 to S4 of the low carry adders 50 to 53, and the second multiplexer 59. Receives and carries the carry of the low carry adder 53.

Similarly, when the carry input signal C1 is high, the first multiplexer 58 selects and outputs the addition values S1 to S4 of the high carry adders 54 to 57, and the second multiplexer 59 The carry of the high carry adder 57 is selected and output.

As described in detail above, the present invention has to design complicated carry lookahead logic to reduce carry propagation delay when implementing 32-bit, 62-bit or more adder, but the cost is reduced because only simple logic needs to be added. In addition, it is easy to design because the adder cell is implemented as a symmetrical type at the time of design, and it is possible to process the data at high speed by reducing the critical path of the carry which causes the propagation delay of the carry. There is.

Claims (2)

A high carry adder that receives a carry-in signal that is high and adds two data of the same bit digit and outputs an addition value and a carry according thereto, and adds two data of the same bit digit by receiving a low-carried input signal. A low carry adder for outputting an add value and a carry according thereto, a first multiplexer which receives the add value from the high carry adder and the low carry adder and multi-transmits it by a carry input signal, and the high carry And an adder comprising a plurality of arithmetic units comprising a second multiplexer which receives a carry from a mountain and a low carry adder and transmits the multiplied by a carry input signal. A first to fourth high carry adder which receives a carry-in signal input high and adds it to data values of corresponding bit positions of two 4-bit data, and sequentially outputs an addition value and a carry according thereto, and a low-in A first to fourth row carry adder which sequentially receives a carry input signal and adds the carry input signal to data values of corresponding bit positions of two 4-bit data, and outputs an added value and a carry accordingly; A first multiplexer which receives an addition value from the first to fourth high carry adders and the first to fourth low carry adders, and transmits the multiplied value by a carry input signal, the fourth high carry adder and the fourth row And a second multiplexer configured to receive a carry from the carry adder and multiplex it by a carry input signal.