KR20000061306A - Method for fabricating metal fuse in semiconductor device - Google Patents
Method for fabricating metal fuse in semiconductor device Download PDFInfo
- Publication number
- KR20000061306A KR20000061306A KR1019990010256A KR19990010256A KR20000061306A KR 20000061306 A KR20000061306 A KR 20000061306A KR 1019990010256 A KR1019990010256 A KR 1019990010256A KR 19990010256 A KR19990010256 A KR 19990010256A KR 20000061306 A KR20000061306 A KR 20000061306A
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- metal layer
- fuse
- passivation
- metal
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 43
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 고집적 반도체 소자에 적합한 금속 퓨우즈 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for producing metal fuses suitable for highly integrated semiconductor devices.
통상적으로, 반도체 디바이스의 제조분야에서 고집적도 및 고속 동작의 요구는 날로 증대되고 있다. 기판상에 고집적으로 형성된 씨모오스 트랜지스터들을 가지는 반도체 메모리 소자를 제조하는 경우에 금속 퓨우즈를 형성하는 제조공정이 포함된다. 이러한 금속 퓨우즈는 기존의 폴리실리콘 퓨즈의 단점을 개선하여 뒤이어 개발된 것으로, 다층 금속배선을 도모하는 현 추세에 보다 적합하다. 그러한 금속 퓨우즈는 일단에서 타단으로 전류를 도통시키는 역할을 하는데, 후속의 공정에서 리던던시 스킴등 필요에 따라 레이저등의 광선에 의해 용융되어 절단될 수 있음은 물론이다. 상기한 금속 퓨우즈는 도 1에서 형성된 배리어 금속층(20)을 식각공정으로 노출시킴에 의해 만들어진다.In general, the demand for high integration and high speed operation in the field of manufacturing semiconductor devices is increasing day by day. A manufacturing process for forming a metal fuse is included in the case of manufacturing a semiconductor memory device having highly integrated transistors formed on the substrate. Such metal fuses are subsequently developed to improve the disadvantages of the existing polysilicon fuses, and are more suitable for the current trend of multi-layer metal wiring. Such a metal fuse serves to conduct electric current from one end to the other end, and of course, in a subsequent process, the redundancy scheme may be melted and cut by a beam of a laser lamp as necessary. The metal fuse is made by exposing the barrier metal layer 20 formed in FIG. 1 to an etching process.
즉, 종래에는 도 2에서 보여지는 바와 같은 금속 퓨우즈(20)를 형성하기 위해, 통상 2회의 식각만을 실시하게 된다. 먼저, 첫번째는 도 1에서 형성된 산화막 재질의 패시베이션 막(40)을 식각하여 산화막 스페이서(41)를 형성하는 것이고, 두 번째는 도 1에서 보여지는 금속 층(30)을 식각하는 것이다. 따라서, 최종적으로 금속 퓨우즈로서 기능할 배리어 금속(20)만이 기판(10)상에 남게 된다. 이와 같은 종래의 금속 퓨우즈 제조방법은 도 2에서 보여지는 바와 같이 산화막의 뿔(41)이 마지막까지 남는 것을 알 수 있는데, 그러한 경우에 후속의 공정에서 퓨즈 커팅시 결함이 발생될 수 있다. 왜냐하면, 상기 산화막의 뿔(41) 내측에는 상기 두번째의 건식식각공정에 의해 폴리머등의 잔존물(43)이 형성되기 때문이다. 그럼에 의해 커팅불량이 발생되어 원하는 퓨우즈의 기능이 상실되는 문제점을 갖는다.That is, conventionally, only two etchings are performed to form the metal fuse 20 as shown in FIG. 2. First, the oxide film spacer 41 is etched by etching the passivation film 40 of the oxide film formed in FIG. 1, and second, the metal layer 30 shown in FIG. 1 is etched. Thus, only the barrier metal 20, which will finally function as the metal fuse, remains on the substrate 10. In the conventional method of manufacturing a metal fuse, as shown in FIG. 2, it can be seen that the horn 41 of the oxide film remains until the end. In such a case, a defect may occur during fuse cutting in a subsequent process. This is because a residue 43 such as a polymer is formed inside the horn 41 of the oxide film by the second dry etching process. As a result, poor cutting occurs, which causes a problem that the desired fuse function is lost.
따라서, 본 발명의 목적은 상기한 종래의 문제를 해결할 수 있는 반도체 소자의 금속 퓨우즈 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a metal fuse of a semiconductor device that can solve the above-described conventional problems.
본 발명의 다른 목적은 금속 퓨우즈의 결함발생을 줄이거나 최소화할 수 있는 금속 퓨우즈 제조방법을 제공함에 있다.Another object of the present invention is to provide a method for producing a metal fuse that can reduce or minimize the occurrence of defects of the metal fuse.
상기한 목적들의 일부를 달성하기 위하여 본 발명의 실시예에 따른 반도체 소자의 금속 퓨우즈 제조방법은,Metal fuse manufacturing method of a semiconductor device according to an embodiment of the present invention to achieve some of the above object,
퓨우즈로서 사용될 배리어 금속층의 상부에 형성된 금속층을 덮는 패시베이션 산화막을 형성한 후, 상기 패시베이션 산화막의 일부를 노출시키는 포토레지스트 패턴을 형성하는 단계와;Forming a passivation oxide film overlying the metal layer formed on top of the barrier metal layer to be used as a fuse, and then forming a photoresist pattern exposing a portion of the passivation oxide film;
상기 포토레지스트 패턴을 식각용 마스크로서 사용하여, 이방성 식각법으로 상기 패시베이션 산화막을 설정된 두께만큼 이방성식각 후, 상기 금속층을 설정된 두께만큼 이방성식각하는 단계와;Using the photoresist pattern as an etching mask, anisotropically etching the passivation oxide film by a predetermined thickness by anisotropic etching, and then anisotropically etching the metal layer by a predetermined thickness;
상기 식각용 마스크를 그대로 둔 상태에서, 상기 이방성 식각법과 동일한 방법으로 상기 패시베이션 산화막을 다시 설정된 두께만큼 이방성식각 후, 상기 금속층을 또 다시 설정된 두께만큼 이방성식각하는 연속적 이방성 식각단계를 가짐에 의해, 상기 패시베이션 산화막의 스페이서가 완전히 제거되고 상기 배리어 금속만이 상기 패턴내에 존재하도록 한 것을 특징으로 한다.By leaving the etching mask intact, having the continuous anisotropic etching step of anisotropically etching the passivation oxide film by the same thickness as the anisotropic etching method, and then anisotropically etching the metal layer by the predetermined thickness again, The spacer of the passivation oxide film is completely removed and only the barrier metal is present in the pattern.
본 발명의 타의 목적 및 이점들은 첨부도면과 함께 설명되는 하기 설명에 의해 보다 명확하게 나타날 것이다.Other objects and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
도 1 및 도 2는 통상적인 금속 퓨우즈 제조를 차례로 보인 도면들1 and 2 show, in turn, typical metal fuse manufacture
도 3 내지 도 6은 본 발명의 일실시예에 따른 금속 퓨우즈 제조공정도들3 to 6 are manufacturing process diagrams of the metal fuse according to an embodiment of the present invention
이하에서는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 퓨우즈 제조방법이 첨부된 도면들과 함께 설명될 것이다. 첨부된 도면들내에서 서로 관련된 부분은 이해의 편의를 위해서 동일내지 유사한 참조부호 또는 명칭으로 라벨링된다. 다음의 설명에서는 본 발명의 보다 철저한 이해를 제공하기 위해 특정한 상세들이 예를 들어 한정되고 자세하게 설명된다. 그러나, 당해 기술분야에 통상의 지식을 가진 자들에게 있어서는 본 발명이 이러한 상세한 항목들이 없이도 실시될 수 있을 것이다. 또한, 본 분야에 너무나 잘 알려진 이방성 식각에 관련된 가스들 및 식각원리, 반도체 소자의 금속 퓨우즈의 형성에 관한 통상의 방법등은 본 발명의 요지를 모호하지 않게 하기 위해 상세히 설명되지 않는다.Hereinafter, a method of manufacturing a metal fuse of a semiconductor device according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings. Parts related to each other in the accompanying drawings are labeled with the same or similar reference numerals or names for ease of understanding. In the following description, specific details are set forth in detail, for example, in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced without these specific details. In addition, gases and etching principles related to anisotropic etching so well known in the art, conventional methods for the formation of metal fuses of semiconductor devices, etc. are not described in detail in order not to obscure the subject matter of the present invention.
도 3 내지 도 6은 본 발명의 일실시예에 따른 금속 퓨우즈 제조공정도들을 도시하고 있다. 먼저, 도 3을 참조하면, 금속층(30-1)이 노출되어 있고 상기 금속층(30-1)의 측벽에는 스페이서(41-1)가 존재하는 것이 보여진다. 도 3에서 보여지는 공정단면은 도 1에서 보여지는 공정단면의 패시베이션 막(40)을 반응성 이온에칭등의 이방성 식각공정으로 식각한 결과로써 얻어진 것이다.3 to 6 illustrate a process diagram of manufacturing a metal fuse according to an embodiment of the present invention. First, referring to FIG. 3, it is seen that the metal layer 30-1 is exposed and the spacer 41-1 is present on the sidewall of the metal layer 30-1. The process cross section shown in FIG. 3 is obtained by etching the passivation film 40 of the process cross section shown in FIG. 1 by an anisotropic etching process such as reactive ion etching.
도 4를 참조하면, 도 3의 도면에 보여진 금속층(30-1)이 식각되어 두께가 줄어든 금속층(30-2)이 나타남을 알 수 있다. 이는 상기 금속층(30-1)에 대하여 이방성 식각을 행한 결과이다. 또한, 도 5를 참조하면, 도 4의 스페이서(41-1)가 두께가 줄어든 스페이서(41-2)가 보인다. 이는 다시 상기 스페이서(41-1)에 대하여 이방성 식각을 행한 결과이다. 도 5에서, 아직도 남아있는 금속층(30-2)은 도 4에서 실시하는 이방성 식각을 다시 행하여 줌에 의해 또 다시 두께가 줄어든다. 즉, 도 4의 공정이후에는 도 5의 공정을 실시하고 다시 도 4의 공정으로 돌아가서 이방성 식각을 행한 다음 도 5의 공정을 다시 실시하는 순으로 하여, 이방성 식각공정은 동일하되 식각의 대상을 번갈아 달리하면, 도 2와 같은 스페이서 뿔(41)이 금속층(30-2)이 없어진 경우에도 남지 않는다. 도 6에는 반복공정의 결과물이 나타나 있다.Referring to FIG. 4, the metal layer 30-1 shown in FIG. 3 is etched to show that the metal layer 30-2 having a reduced thickness is shown. This is a result of anisotropic etching of the metal layer 30-1. 5, the spacer 41-2 in which the thickness of the spacer 41-1 of FIG. 4 is reduced is shown. This is again the result of anisotropic etching of the spacer 41-1. In FIG. 5, the remaining metal layer 30-2 is further reduced in thickness by again performing anisotropic etching performed in FIG. 4. That is, after the process of FIG. 4, the process of FIG. 5 is performed, the process returns to the process of FIG. 4, and the anisotropic etching is performed, and then the process of FIG. 5 is performed again. In other words, the spacer horn 41 as shown in FIG. 2 does not remain even when the metal layer 30-2 is missing. 6 shows the result of the repetitive process.
이와 같이, 포토레지스트 패턴(50)을 식각용 마스크로서 사용하여, 패시베이션 산화막과 금속층을 연속적으로 번갈아 이방성 식각을 함으로써, 상기 포토레지스트 패턴(50)에 의해 노출된 영역내에는 뿔 형태의 패시베이션 산화막(40)이 완전히 제거되고, 퓨우즈로서 기능할 배리어 금속층(20)만이 존재한다.As described above, by using the photoresist pattern 50 as an etching mask, the passivation oxide film and the metal layer are alternately anisotropically etched to form an horn-shaped passivation oxide film in the region exposed by the photoresist pattern 50. 40 is completely removed and there is only a barrier metal layer 20 that will function as a fuse.
여기서, 식각되어질 막이 재질이 산화막 또는 BPSG로 되어 있는 경우에 식각용 가스로서 사용될 혼합가스는 CCl2F2, CF4, C2F6,CHF3/CF4등이 선택될 수 있고, 식각되어질 막의 재질이 금속인 경우에 혼합가스는 CL2,CCL4,SF6등을 사용할 수 있다.Here, the mixed gas to be used as the etching gas when the material to be etched is an oxide film or BPSG may be selected from CCl 2 F 2 , CF 4 , C 2 F 6, CHF 3 / CF 4, and the like. When the material of the membrane is a metal, the mixed gas may be CL 2 , CCL 4, SF 6, or the like.
따라서, 산화막 뿔등이 생성되지 아니하므로, 폴리머등의 잔존물은 쉽게 제거되어, 후속의 커팅불량이 발생될 수 있는 확률이 최소화된다. 결국, 퓨우즈의 기능을 다할 수 있게 할 확률을 높여서 수율을 개선한다.Therefore, since no oxide horns or the like are produced, residues of polymers and the like are easily removed, thereby minimizing the probability that subsequent cutting defects may occur. Eventually, the yield is improved by increasing the probability that the fuse will function.
전술한 바와 같이, 본 발명의 실시예들은 도면을 참조하여 예를들어 설명되었지만, 사안이 허용하는 범위에서 다양한 변화와 변경이 가능함은 물론이다.As described above, the embodiments of the present invention have been described by way of example with reference to the drawings, but of course, various changes and modifications can be made within the scope allowed by the matter.
상기한 본 발명의 금속 퓨우즈 제조방법에 따르면, 금속 퓨우즈의 결함발생을 줄이거나 최소화할 수 있는 효과를 갖는다.According to the metal fuse manufacturing method of the present invention described above, it has an effect that can reduce or minimize the occurrence of defects of the metal fuse.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990010256A KR20000061306A (en) | 1999-03-25 | 1999-03-25 | Method for fabricating metal fuse in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990010256A KR20000061306A (en) | 1999-03-25 | 1999-03-25 | Method for fabricating metal fuse in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000061306A true KR20000061306A (en) | 2000-10-16 |
Family
ID=19577697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990010256A KR20000061306A (en) | 1999-03-25 | 1999-03-25 | Method for fabricating metal fuse in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000061306A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7352050B2 (en) | 2004-03-25 | 2008-04-01 | Samsung Electronics Co., Ltd. | Fuse region of a semiconductor region |
| US7492032B2 (en) | 2004-04-21 | 2009-02-17 | Samsung Electronics Co., Ltd. | Fuse regions of a semiconductor memory device and methods of fabricating the same |
-
1999
- 1999-03-25 KR KR1019990010256A patent/KR20000061306A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7352050B2 (en) | 2004-03-25 | 2008-04-01 | Samsung Electronics Co., Ltd. | Fuse region of a semiconductor region |
| US7492032B2 (en) | 2004-04-21 | 2009-02-17 | Samsung Electronics Co., Ltd. | Fuse regions of a semiconductor memory device and methods of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7517638B2 (en) | Method of manufacturing a semiconductor apparatus with a tapered aperture pattern to form a predetermined line width | |
| JP2002217170A (en) | Method of forming fine pattern, method of fabricating semiconductor device and semiconductor device | |
| TW200405417A (en) | Method for fabricating semiconductor device | |
| US6589880B2 (en) | Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method | |
| US6008121A (en) | Etching high aspect contact holes in solid state devices | |
| KR100512904B1 (en) | Fabricating method for semiconductor device | |
| KR20000061306A (en) | Method for fabricating metal fuse in semiconductor device | |
| US6046488A (en) | Semiconductor device having conductive layer and manufacturing method thereof | |
| JPH08288256A (en) | Trench etching method | |
| EP0178654A2 (en) | Method of manufacturing a semiconductor device comprising a method of patterning an organic material | |
| US6753265B2 (en) | Method for manufacturing bit line | |
| US20070290296A1 (en) | Fuse Structures and Methods of Forming the Same | |
| KR100632565B1 (en) | Method for forming fuse box of semiconductor device | |
| US5990018A (en) | Oxide etching process using nitrogen plasma | |
| KR0153508B1 (en) | Method of fabricating a semiconductor device | |
| JP2001077087A (en) | Manufacture and etching method of semiconductor device | |
| KR100276562B1 (en) | Method of forming a contact hole in a semiconductor device | |
| KR100318454B1 (en) | A method for fabricating semiconductor device | |
| KR20000003594A (en) | Method of fabricating fuse box of semiconductor device | |
| KR940005626B1 (en) | Method of making pattern of polysilicone | |
| KR100475000B1 (en) | Metalization method including post-treatment by fluoride base gas | |
| KR100460798B1 (en) | Semiconductor device manufacturing method | |
| JPH05206125A (en) | Manufacture of semiconductor device | |
| KR20010059452A (en) | Method for forming fuse box | |
| KR20040050644A (en) | method of forming a semiconductor device having a silicide layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |