KR20000060474A - method of manufacturing storage electrode in semiconductor memory device - Google Patents

Abstract

PURPOSE: An improved method for fabricating a storage electrode of a semiconductor memory device is provided to prevent damage to a conductive layer for the storage electrode and underlying layers together with using a typical wet etch process. CONSTITUTION: An interlayer dielectric(30) is formed on a semiconductor substrate having an access transistor, and a vertical hole is formed in the interlayer dielectric(30) to reach the access transistor. After a polysilicon pattern(32) is formed on the interlayer dielectric(30) and in the vertical hole, a tungsten pattern(34) is formed on the polysilicon pattern(32) to have a width smaller than that of the polysilicon pattern(32). A sidewall spacer(36) is next formed around the tungsten pattern(34), and the polysilicon pattern(32) is etched by using both the sidewall spacer(36) and the tungsten pattern(34) as an etch mask. The tungsten pattern(34) is then removed, and the centrally exposed polysilicon pattern(32) is etched to a predetermined depth. Finally, the sidewall spacer(36) is removed.

Description

Method of manufacturing storage electrode in semiconductor memory device

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a storage electrode of a semiconductor memory device.

In various semiconductor memory cells, in particular, a DRAM (Dynamic Random Access Memory, hereinafter referred to as "DRAM") cell is usually composed of one access transistor and one capacitor. The access transistor serves as a switch for inputting data (data " 1 ") or output (data " 0 ") to the capacitor, and the capacitor acts as a warehouse for temporarily storing data. That is, the capacitance of the DRAM cell stores and retains the data depending on the capacitance. Therefore, when the capacitance is insufficient, an error occurs in the process of storing data in the DRAM cell or outputting the stored data. Therefore, in order to prevent data errors, the DRAM cell requires a so-called refresh operation for restoring data after a predetermined time elapses. Since the refresh operation is dependent on the capacity of the capacitor, increasing the capacity of the capacitor may require a refresh characteristic, That is one of the important ways to extend the data retention time.

However, as the integration density of semiconductor memory devices increases, the area of unit cells per chip decreases, thereby reducing the area where capacitors can be formed. Therefore, in the present field, a COB (Capacitor Over Bit-line) structure is adopted to form a storage electrode having a larger surface area within a limited area, and furthermore, a cylinder type, a box type, a fin type, etc. It was transformed into a dimensional structure.

1 is a cross-sectional view of a semiconductor memory device in which a cylindrical storage electrode according to a conventional method is formed.

Referring to the drawings, a gate region including a gate insulating film 14, a gate electrode 16, and a sidewall insulating film 18 is formed on a semiconductor substrate 10 having an active region and an inactive region separated by an isolation layer 12. A diffusion region consisting of the source region 20 and the drain region 21 is formed. In general, the gate region and the diffusion region are called an access transistor, and a first insulating layer 22 is formed to planarize the semiconductor substrate 10 on which the access transistor is formed. The bit line 24 penetrates the first insulating layer 22 and contacts the drain region 21. The bit line 24 is disposed above the bit line 24 and is a lower electrode of the capacitor. In order to prevent the short circuit of the electrode 28, the second insulating film 26 using silicon dioxide is formed.

In this case, a process for forming the storage electrode 28 is as follows.

First, an opening extending from the second insulating layer 26 to the source region 20 is formed, and then a conductive film such as polycrystalline silicon, Phosphorus Silicon Glass (PSG), Boron Phosphorus Silicon Glass (BPSG), and Undoped Silicon Glass (USG) are formed. After depositing an insulating film such as these, they are simultaneously patterned. Then, a sidewall spacer is formed on the sidewalls of the insulating film and the conductive film pattern using the same material as the conductive film, and then the insulating film such as the BPSG PSG is wet-etched using an etching etchant having excellent etching selectivity with the conductive film. By removing it, a cylindrical storage electrode is formed.

According to the above-described conventional storage electrode manufacturing method, after depositing the insulating film of the PSG, BPSG, USG, etc. by wet etching, the second insulating film made of silicon dioxide as well as the conductive film to function as the storage electrode. (26) is damaged. However, the conventional wet etching process does not completely prevent damage to the conductive layer and the second insulating layer, and even when a new wet etching process is to be introduced, a large number of trials and errors have to be performed. .

Accordingly, an object of the present invention is to provide a method for manufacturing a storage electrode of a semiconductor memory device that can solve the above-described conventional problems.

Another object of the present invention is to provide an improved method for manufacturing a storage electrode, which does not damage the conductive electrode for the storage electrode and another material layer under the same while using a commercially available wet etching process.

In order to achieve the above objects, in the present invention, in the method of manufacturing a capacitor lower electrode of a semiconductor memory device, after forming an insulating film on the access transistor, one of the active regions of the access transistor is located on the surface of the insulating film. Forming a generally vertical opening leading to the surface of the substrate; Forming a polycrystalline silicon pattern on top of the resultant product in which the opening is formed; Forming a tungsten pattern smaller than the polycrystalline silicon pattern on the polycrystalline silicon pattern; Forming a sidewall insulating film on the tungsten pattern sidewalls; Etching the polycrystalline silicon pattern using the sidewall insulating layer and the tungsten pattern as an etching mask; Removing the tungsten pattern, and then etching the polycrystalline silicon pattern exposed to the bottom to a predetermined depth; A method of manufacturing a capacitor lower electrode of a semiconductor memory device, the method comprising removing the sidewall insulating layer.

Preferably, the tungsten pattern is removed using an etching etchant containing hydrogen peroxide.

1 is a cross-sectional view of a semiconductor memory device in which a cylindrical storage electrode according to a conventional method is formed.

2A to 2C are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a second embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a third embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 2A, an interlayer insulating film 30 is formed by depositing PSG, BPSG, USG, and the like on a semiconductor substrate on which an access transistor, a bit line, and the like are formed through a conventional process as shown in FIG. 1. An opening is formed in the upper portion of the interlayer insulating layer 30 to reach the source region of the access transistor, and then a polycrystalline silicon film doped with impurities is deposited on the resultant to a thickness of about 10000 kV. After the photolithography and dry etching process are performed on the polycrystalline silicon film to form the polycrystalline silicon pattern 32, a tungsten pattern 34 having a thickness of about 4000 to 5000 Å is formed on the polycrystalline silicon pattern 32. Subsequently, an oxide film of about 2000 kV is deposited on the resultant on which the tungsten pattern 34 is formed, and then etched back to form sidewall oxide films 36 on both sidewalls of the tungsten pattern 34.

Referring to FIG. 2B, the polycrystalline silicon pattern 32 is dry-etched under the sidewall oxide layer 36 by using an etching etchant having a high etching rate with respect to the polycrystalline silicon. Then, the tungsten pattern 34 is removed by dry etching using an etching etchant having a high etching rate with respect to tungsten. Preferably, the tungsten pattern 34 is removed using an etching etchant containing hydrogen peroxide (H ₂ O ₂ ).

After removing the tungsten pattern 34, the polycrystalline silicon pattern 32 is etched to a predetermined depth to form the storage electrode 32a. At this time, the polycrystalline silicon pattern 32 is preferably etched so that a predetermined thickness remains below to obtain the cylindrical storage electrode 32a.

Referring to FIG. 2C, the sidewall oxide layer 36 is completely removed by a wet etching process. Subsequently, although not shown, a capacitor of the semiconductor memory device is completed by further forming a plate electrode, which is an upper electrode of the high dielectric film and the capacitor, on the storage electrode 32a.

As described above, in the first embodiment of the present invention, by effectively removing the tungsten pattern using hydrogen peroxide, it is possible to form a cylinder type storage electrode without adding a new process.

3A to 3D are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 3A, an interlayer insulating film 30 is formed by depositing PSG, BPSG, USG, and the like on a semiconductor substrate on which a conventional access transistor, a bit line, etc. are formed, and then a predetermined region of the interlayer insulating film 30. Is etched to form an opening leading to the source region of the access transistor. A first polycrystalline silicon film doped with impurities is deposited to a thickness of about 8000 Å on an upper portion of the resultant product in which the opening is formed, and then the first polycrystalline silicon pattern 32 is formed by performing a photo and dry etching process. Subsequently, a tungsten pattern 34 is formed on the first polycrystalline silicon pattern 32 to a thickness of about 5000 GPa, and a second polycrystalline silicon film 38 doped with impurities is formed on the resultant to about 2000 GPa. .

Referring to FIG. 3B, an oxide film of about 2000 kV is deposited on the second polycrystalline silicon film 38 and then etched back to form a sidewall oxide film 40 on the sidewall of the second polycrystalline silicon film 38.

Referring to FIG. 3C, the first polycrystalline silicon pattern 32 and the second polycrystalline silicon layer 38 are dry-etched using an etching etchant having a high etching rate with respect to the polycrystalline silicon, and thus the storage electrodes 32a and 38a. To form. In this case, since the sidewall oxide layer 40 formed on the sidewall of the second polycrystalline silicon layer 38 functions as a self-aligned etching mask during the dry etching process, as illustrated, the first polycrystalline silicon pattern 32 ) And the second polycrystalline silicon film 38 form a cylinder type.

Referring to FIG. 3D, the sidewall oxide layer 40 and the tungsten pattern 34 are dry-etched and completely removed using an etching etchant having a high etching rate for an oxide film and an etching etchant having a high etching rate for tungsten. do. At this time, it is preferable to use hydrogen peroxide as an etching etchant for dry etching the tungsten pattern 34.

As a result, a cylindrical storage electrode made of the first polycrystalline silicon pattern 32a and the second polycrystalline silicon 38a is formed. Subsequently, although not shown, a high dielectric film and a plate electrode are further formed on the storage electrode, thereby completing the capacitor of the semiconductor memory device.

According to the second embodiment described above, as in the first embodiment, by removing the tungsten pattern effectively using hydrogen peroxide, a cylinder type storage electrode can be formed without adding a new process.

4A to 4C are cross-sectional views illustrating a method of manufacturing a storage electrode of a semiconductor memory device according to a third embodiment of the present invention.

Referring to FIG. 4A, after an ordinary access transistor and a bit line are formed on a semiconductor substrate, an interlayer insulating film 30 is formed by depositing PSG, BPSG, USG, and the like. Then, a predetermined region of the interlayer insulating film 30 is etched to form an opening reaching the source region of the access transistor. Subsequently, a first polycrystalline silicon film doped with impurities is formed at about 1000 ns and tungsten at about 5000 ns in order, and then a photo and dry etching process is performed on the first polycrystalline silicon pattern 40. And a tungsten pattern 42.

Referring to FIG. 4B, a second polycrystalline silicon film 44 doped with impurities is formed on the upper part of the resultant product on which the first polycrystalline silicon pattern 40 and the tungsten pattern 42 are formed. .

Referring to FIG. 4C, an etch back process is performed on the second polycrystalline silicon film 44 to form sidewall spacers 44a. The tungsten pattern 42 is then removed with hydrogen peroxide to form a cylindrical storage electrode.

According to the third embodiment described above, as in the first and second embodiments described above, by removing the tungsten formed between the polycrystalline silicon with hydrogen peroxide, the cylinder-type storage without adding a new process An electrode can be obtained.

As described above, in forming the storage electrode which is the lower electrode of the capacitor, by using the tungsten pattern as an etching mask, the polycrystalline silicon is etched to obtain a storage electrode having a large surface area without adding a new process.

Claims (6)

In the method of manufacturing a capacitor lower electrode of a semiconductor memory device: Forming an insulating film over the access transistor, and then forming a generally vertical opening from the surface of the insulating film to a surface of the substrate in which one of the active regions of the access transistor is located; Forming a polycrystalline silicon pattern on top of the resultant product in which the opening is formed; Forming a tungsten pattern smaller than the polycrystalline silicon pattern on the polycrystalline silicon pattern; Forming a sidewall insulating film on the tungsten pattern sidewalls; Etching the polycrystalline silicon pattern using the sidewall insulating layer and the tungsten pattern as an etching mask; Removing the tungsten pattern, and then etching the polycrystalline silicon pattern exposed to the bottom to a predetermined depth; Removing the sidewall insulating layer; and manufacturing a capacitor lower electrode of the semiconductor memory device. The method of claim 1, wherein the tungsten pattern is removed using an etching etchant containing hydrogen peroxide. In the method of manufacturing a capacitor lower electrode of a semiconductor memory device: Forming an insulating film over the access transistor, and then forming a generally vertical opening from the surface of the insulating film to a surface of the substrate in which one of the active regions of the access transistor is located; Forming a first polycrystalline silicon pattern on top of the resultant product in which the opening is formed; Forming a tungsten pattern smaller than the polycrystalline silicon pattern on the polycrystalline silicon pattern; Forming second polycrystalline silicon on top of the resultant on which the tungsten pattern is formed; Forming a sidewall insulating film on a second polycrystalline silicon sidewall surrounding the tungsten pattern; Etching the second polycrystalline silicon and the first polycrystalline silicon pattern using the sidewall insulating layer as an etching mask; Removing the tungsten pattern and the sidewall insulating layer; and manufacturing a capacitor lower electrode of the semiconductor memory device. The method of claim 3, wherein the tungsten pattern is removed using an etching etchant containing hydrogen peroxide. In the method of manufacturing a capacitor lower electrode of a semiconductor memory device: Forming an insulating film over the access transistor, and then forming a generally vertical opening from the surface of the insulating film to a surface of the substrate in which one of the active regions of the access transistor is located; Sequentially forming a first polycrystalline silicon pattern and a tungsten pattern on the resultant product having the opening formed thereon; Forming second polycrystalline silicon on top of the resultant product on which the first polycrystalline silicon pattern and the tungsten pattern are formed, and then etching the entire surface thereof; Removing the tungsten pattern; and manufacturing a capacitor lower electrode of the semiconductor memory device. The method of claim 5, wherein the tungsten pattern is removed using an etching etchant containing hydrogen peroxide.